CN102148920A - Synchronizing signal amplitude limiting device and method - Google Patents
Synchronizing signal amplitude limiting device and method Download PDFInfo
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Abstract
The embodiment of the invention provides a synchronizing signal amplitude limiting device and method. The synchronizing signal amplitude limiting device comprises a filter module, an amplitude limiting electrical level detector and a comparator, wherein the filter module is used for processing video input to generate filter output, and comprises a first filter circuit, and the first filter circuit is used for receiving the video input and performs infinite impulse response filter processing on the video input; the amplitude limiting electrical level detector is coupled to the filter module for receiving the filter output and determines an amplitude limiting electrical level corresponding to synchronizing signal content is determined according to the filter output; and the comparator is coupled to the first filter and the filter module for receiving the filter output and the amplitude limiting electrical level and for comparing the filter output with the amplitude limiting electrical level to generate synchronizing signal amplitude limiting output.
Description
Technical field
The present invention handles relevant for signal limiter, especially refer to utilize infinite impulse response (InfiniteImpulse Response, IIR) output of Filtering Processing decides clip level and produces the synchronizing signal amplitude limiter and the method for the output of synchronizing signal amplitude limit a kind of comprising.
Background technology
Generally speaking, the main dependency level synchronizing signal of the Synchronous Processing of anolog TV signals (horizontalsync, HSYNC) and vertical synchronizing signal (vertical sync, VSYNC), wherein the signal transmission of each bar scan line can comprise a horizontal-drive signal, yet vertical synchronizing signal only can each (field) just produce once.See also Fig. 1, Fig. 1 is the waveform schematic diagram of existing composite video signal (composite videosignal).As shown in the figure, horizontal synchronization level (sync tip) is the lowest voltage level in the composite video signal, and and has the pressure reduction of 300mV between the reference black level (reference black level), generally speaking, the original position of the horizontal-drive signal composition that the signal that the simulated television decoder often adopts the technology of synchronizing signal amplitude limit (sync slicing) to decide each bar scan line in the composite video signal transmits, for example, can find out earlier with reference to black level and horizontal synchronization level, then, intermediate level with reference black level and horizontal synchronization level is used as clip level, produces horizontal synchronization clock so that isolate the horizontal-drive signal composition from composite video signal for subsequent conditioning circuit (for example phase-locked loop) so that composite video signal is carried out amplitude limiting processing.
Yet, the anolog TV signals that receive tend to exist some interference, for example white noise (whitenoise) and co-channel interference (co-channel interference) or the like, so, actual composite video signal does not have ideal waveform shown in Figure 1, but can be interfered and produce wave distortion, therefore, how to determine suitable clip level to obtain an important topic in the design of a synchronizing signal amplitude limit of synchronizing signal amplitude limit output just becoming accurately.
Summary of the invention
Therefore, one of purpose of the present invention is to provide utilize output that infinite impulse response filter handles with the decision clip level and produce the synchronizing signal amplitude limiter and the method for the output of synchronizing signal amplitude limit a kind of comprising, to address the above problem.
According to embodiments of the invention, it discloses a kind of synchronizing signal amplitude limiter.This synchronizing signal amplitude limiter includes filtration module, clip level detector and comparator.This filtration module is handled video input producing filtering output, and includes first filter circuit, in order to receiving this video input, and infinite impulse response filter is carried out in this video input handle.This clip level detector is coupled to this filtration module, exports in order to receive this filtering, and decides the clip level of corresponding synchronizing signal composition according to this filtering output.This comparator is coupled to this clip level detector and this filtration module, and in order to receiving this filtering output and this clip level, and relatively this clip level is exported to produce the synchronizing signal amplitude limit with this filtering output.
According to embodiments of the invention, it discloses a kind of synchronizing signal amplitude limit method in addition.This synchronizing signal amplitude limit method includes: handle the video input producing filtering output, it comprises and infinite impulse response filter is carried out in this video input handles; Decide the clip level of corresponding synchronizing signal composition according to this filtering output; And relatively this clip level and this filtering output to produce the output of synchronizing signal amplitude limit.
Can determine suitable clip level to obtain a synchronizing signal amplitude limit output accurately by the present invention.
Description of drawings
Fig. 1 is the waveform schematic diagram of existing composite video signal.
Fig. 2 is the schematic diagram of synchronizing signal amplitude limiter first embodiment of the present invention.
Fig. 3 is that first filter circuit is carried out the simplified diagram that infinite impulse response filter is handled.
Fig. 4 is the flow chart of synchronizing signal amplitude limit method first embodiment of the present invention.
Fig. 5 is the schematic diagram of synchronizing signal amplitude limiter second embodiment of the present invention.
Fig. 6 is the flow chart of synchronizing signal amplitude limit method second embodiment of the present invention.
Embodiment
In the middle of claims and specification, used some vocabulary to censure specific element.Those of ordinary skill in the affiliated field should be understood, and hardware manufacturer may be called same element with different nouns.Claims of the present invention and specification are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be open term mentioned " comprising " in the middle of specification and the follow-up request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other device or connection means if describe first device in the literary composition.
See also Fig. 2, Fig. 2 is the schematic diagram of synchronizing signal amplitude limiter first embodiment of the present invention.Synchronizing signal amplitude limiter 200 includes (but being not limited to) filtration module 202, clip level detector 204 and comparator 206.Filtration module 202 is used for handling video input (for example sampled data of composite video signal) S_IN to produce filtering output S_OUT, in present embodiment, filtration module 202 includes first filter circuit 208 at least, its receiver, video input S_IN, and video is imported S_IN carry out infinite impulse response (Infinite Impulse Response, IIR) Filtering Processing produces filtering output S_OUT, in other words, first filter circuit 208 can adopt the framework of infinite impulse response filter to be realized.Clip level detector 204 is coupled to filtration module 202, in order to the output S_OUT that accepts filter from filtration module 202, and decide clip level (slicer level) SL of corresponding synchronizing signal composition according to filtering output S_OUT, in present embodiment, this synchronizing signal composition is the horizontal-drive signal composition, yet this is not restriction of the present invention only as the usefulness of example explanation.In addition, comparator 206 is coupled to clip level detector 204 and filtration module 202, and in order to output S_OUT and the clip level SL of accepting filter, and relatively clip level SL exports Sliced_SYNC with filtering output S_OUT with generation synchronizing signal amplitude limit.Comparator 206 and clip level detector 204 because major technique of the present invention is characterised in that filtration module 202, that is see through filtration module 202 and produce filtering output S_OUT and use for subsequent conditioning circuit (comprising comparator 206 and clip level detector 204), moreover, in utilization of the present invention, comparator 206 can adopt any existing circuit framework to be operated with clip level detector 204, so for specification for purpose of brevity, about the description of comparator 206 and clip level detector 204 just in this omission.Circuit and running with next detailed description filtration module 202.
As previously mentioned, first filter circuit 208 in the filtration module 202 is to be used for carrying out infinite impulse response filter to handle, therefore, in the present embodiment, first filter circuit 208 can be handled input data (that is S_IN) with recursive mode, in other words, the filtering output S_OUT that first filter circuit 208 is produced can be relevant with input data of receiving at present (for example present data of composite video signal) and the input data of before having received (for example last data of composite video signal), in the present embodiment, first filter circuit 208 adopts the computing of weighted average (weighted average) to realize the infinite impulse response filter processing, yet, this is only as the usefulness of example explanation, but not restriction of the present invention, that is, under the spiritual prerequisite of invention of the present invention, first filter circuit 208 also can adopt other infinite impulse response system to be realized, and the variation in these designs also belongs to category of the present invention.As shown in Figure 2, first filter circuit 208 in the filtration module 202 includes (but being not limited to) first multiplication unit 210, second multiplication unit 212, adder unit 214, storage element 216 and weighted value setup unit 218.First multiplication unit 210 is multiplied by the first weighted value W (0≤W≤1) in order to video is imported each data among the S_IN (for example each sampled value of composite video signal), to produce first multiplication output M1.212 of second multiplication units are coupled to storage element 216, be multiplied by second weighted value (1-W) in order to each data (for example each sampled value of handling via weighted average) among the result D_IIR that storage element 216 is stored, to produce second multiplication output M2.Adder unit 214 is coupled to first multiplication unit 210, second multiplication unit 212 and storage element 216, in order to add up first multiplication output M1 and second multiplication output M2 to produce addition output M3, M3=M1*W+M2* (1-W) wherein, and addition is exported M3 write to storage element 216 to upgrade corresponding each data among the stored result D_IIR of storage element 216.
In present embodiment, the addition output M3 that adder unit 214 is produced carries out the Data Update except writing back storage element 216, directly exports S_OUT (that is S_OUT=M3) as the filtering of filtration module 202 in addition; In addition, storage element 216 is line buffer (line buffer), its buffer depth equals the predetermined total number of sample points of a scan line, therefore, under ideal state, the sampled data of a scan line of every input, then storage element 216 can just store the sampled data of this scan line via the result after the infinite impulse response filter processing.In addition, because line buffer is the element that is possessed in the script simulated television decoder, therefore, first filter circuit 208 can utilize existing line buffer to be used as required storage element 216, thereby saves running and go up required hardware cost.
See also Fig. 3, Fig. 3 is that first filter circuit 208 is carried out the simplified diagram that infinite impulse response filter is handled.Suppose in period T
0～T
1In, filtration module 202 is received the sampled data D0 of the 1st scan line in first picture one by one, and sampled data D0 can write direct storage element 216 with as the stored initial treatment of storage element 216 D_IIR as a result
0, that is D_IIR
0=D
0From time T 2, each data (sampled value) beginning in first picture among the sampled data D1 of the 2nd scan line inputs to first filter circuit 208 one by one, during first sampled value in receiving sampled data D1, first filter circuit 208 can be read initial treatment D_IIR as a result in storage element 216
0In corresponding processing over-sampling value, and handle via above-mentioned infinite impulse response filter and to produce a new processing over-sampling value to storage element 216, and follow-up sampled value also similarly can be carried out the infinite impulse response filter processing one by one among the sampled data D1, therefore, and in period T
1～T
2In, first filter circuit 208 can be considered based on initial treatment D_IIR as a result
0Carry out infinite impulse response filter with sampled data D1 and handle, so in time T
2The time, storage element 216 just can store the result D_IIR after the renewal
1In like manner, in period T
2～T
3In, first filter circuit 208 can be considered based on result D_IIR
1Carry out infinite impulse response filter with next record sampled data D1 and handle, so in time T
3The time, storage element 216 just can store the result D_IIR after the renewal
2Because the those skilled in the art can learn follow-up running after reading above-mentioned explanation easily, so do not give unnecessary details in addition in this.
Because can carrying out infinite impulse response filter to video input S_IN, handles by first filter circuit 208, again infinite impulse response filter is handled the filtering output S_OUT produced (that is Filtering Processing cross video input S_IN) and inputed to subsequent conditioning circuit (for example clip level detector 204 and comparator 206), therefore, for clip level detector 204 and comparator 206, because the video that Filtering Processing is crossed input S_IN can be with undesired interference component (for example white noise and co-channel interference or the like) filtering or decay effectively among the script video input S_IN, therefore, can significantly promote the accuracy of the synchronizing signal amplitude limit output Sliced_SYNC that clip level SL that clip level detector 204 judged and comparator 206 produced, and then improve final picture display quality.
Please note, in present embodiment, first filter circuit 208 is provided with weighted value setup unit 218 in addition, it is coupled to first multiplication unit 210 and second multiplication unit 212, characteristics of signals in order to foundation video input S_IN is set the first weighted value W and second weighted value (1-W), for instance, weighted value setup unit 218 can be based on signal to noise ratio (the signal-to-noise ratio of video input S_IN, SNR) dynamically adjust the first weighted value W and second weighted value (1-W), therefore, when the signal to noise ratio of video input S_IN is higher (it is more not serious represent video to import the annoyance level of S_IN), then weighted value setup unit 218 can increase by the first weighted value W and reduce by second weighted value (1-W), on the other hand, when the signal to noise ratio of video input S_IN is low (it is more serious represent video to import the annoyance level of S_IN), then weighted value is set single 218 meeting reduction by first weighted value W and is promoted second weighted value (1-W), in other words, the first weighted value W and signal to noise ratio positive correlation, second weighted value (1-W) then is a negative correlation with signal to noise ratio.
According to above-mentioned explanation as can be known, the setting of weighted value setup unit 218 can make win weighted value W and second weighted value (1-W) along with the actual signal quality of video input S_IN itself and dynamically adjust, so make first filter circuit 208 can have preferable infinite impulse response filter treatment efficiency, yet, in fact weighted value setup unit 218 can be the element of a selectivity (optional), for example, in another embodiment, if under the specific operation environment, the actual signal quality of video input S_IN is all very stable, then first filter circuit 208 just can omit weighted value setup unit 218, and only use the one group of default first weighted value W and second weighted value (1-W), and the variation in this design also belongs to category of the present invention.
Fig. 4 is the flow chart of synchronizing signal amplitude limit method first embodiment of the present invention.Flow process shown in Figure 4 is applied to synchronizing signal amplitude limiter 200 shown in Figure 2, and in addition, if can obtain identical haply result, then step not necessarily will be carried out in accordance with order shown in Figure 4.The running of synchronizing signal amplitude limit method first embodiment of the present invention can simply be summarized as follows:
Step 402: receiver, video input (for example sampled data of composite video signal).
Step 404: infinite impulse response filter is carried out in this video input handle (for example weighted average processing) to produce filtering output.
Step 406: the clip level that decides corresponding synchronizing signal composition (for example horizontal-drive signal composition) according to this filtering output.
Step 408: relatively this clip level and this filtering output is to produce the output of synchronizing signal amplitude limit.Then, getting back to step 404 handles this video input to continue adopting this infinite impulse response filter to handle.
Because the those skilled in the art should understand the details of operation of each step easily after the technology contents that reads above-mentioned relative synchronous signal limiter device 200, therefore, related description is not just given unnecessary details in addition in this.
In the foregoing description, storage element 216 is a line buffer, its buffer depth equals the predetermined total number of sample points of a scan line, therefore, under ideal state, the sampled data of a scan line of every input, result after then storage element 216 sampled data that can just store this scan line is handled via infinite impulse response filter, yet, (for example the source of video input S_IN is cassette tape formula image record/play machine (videocassette recorder if the scanning line period (line period) of video input S_IN is unstable, VCR), therefore tend to be subject to the self character of reading mechanism and cause the scanning line period instability) or produce change (for example the source of video input S_IN is not that normal video output is provided), therefore under same sample frequency, article one, the actual samples point of scan line sum can be not equal to predetermined total number of sample points (that is buffer depth of line buffer), the situation that can cause this moment video input S_IN and result D_IIR to align, may make the signal quality deteriorates of the filtering output S_OUT that filtration module 202 produced (that is Filtering Processing cross video input S_IN) on the contrary, therefore, the present invention discloses a kind of adaptability (adaptive) Filtering Processing mechanism in addition, and it can dynamically select suitable Filtering Processing mode for use according to judgment standard.
See also Fig. 5, Fig. 5 is the schematic diagram of synchronizing signal amplitude limiter second embodiment of the present invention.Synchronizing signal amplitude limiter 500 includes (but being not limited to) filtration module 502 and clip level detector 204 and comparator 206 shown in Figure 2, wherein filtration module 502 is except first filter circuit 208 shown in Figure 2, and other comprises second filter circuit 508, multiplexer 510 and control circuit 512.Because the function of first filter circuit 208, clip level detector 204 and comparator 206 and running are in last detailed description, so just do not give unnecessary details in addition at this.For second filter circuit 508, its receiver, video input similarly S_IN, but can import S_IN to video and be scheduled to Filtering Processing, handle and should predetermined Filtering Processing be different from first filter circuit, 208 performed infinite impulse response filter, for instance, should predetermined Filtering Processing be simple low-pass filtering treatment, therefore, second filter circuit 508 can average computing and export mean value with many data (for example a plurality of sampled values of corresponding same scan line in the composite video signal) of corresponding same scan line among the video input S_IN, yet, this is only as the usefulness of example explanation, be not to be restriction of the present invention, that is, in other embodiment, should be scheduled to the filtering operation that Filtering Processing also can adopt other type, in broad terms, do not violating under the invention spirit of the present invention, so long as differ from the treatment mechanism that infinite impulse response filter that first filter circuit 208 adopted is handled, all applicable to second filter circuit 508, and the variations in these designs all belong to category of the present invention.
In addition, multiplexer 510 has a plurality of input port N1, N2 and is respectively coupled to first filter circuit 208 and second filter circuit 508, control port N3 and output port N4, and wherein output port N4 is in order to the filtering output S_OUT of output filtration module 502.Control circuit 512 is coupled to control port N3, be used for produce selecting signal SEL to control port N3, output (for example result that the low-pass filtering treatment was produced) M3 ' of the output of first filter circuit 208 (that is adder unit 214 shown in Figure 2 produced addition output M3) or second filter circuit 508 be passed to output port N4 with as filtering output S_OUT with control multiplexer 510.
As shown in Figure 5, comparator 206 can input to synchronizing signal amplitude limit output Sliced_SYNC clock-generating device (for example phase-locked loop) 501 and handle with generation synchronised clock (for example horizontal synchronization clock) CLK_SYNC, and control circuit 512 just produces selection signal SEL based on the cycle of synchronised clock CLK_SYNC.For instance, under default (default) mode of operation, control circuit 512 can produce to be selected signal SEL to control multiplexer 510 the output M3 of first filter circuit 208 is passed to output port N4 with as filtering output S_OUT, in other words, filtration module 502 default first filter circuits 208 that adopt, yet, the cycle that detects synchronised clock CLK_SYNC when control circuit 512 is follow-up is different with the ideal value of scanning line period or detect the cycle of synchronised clock CLK_SYNC and the difference of this ideal value (phase difference) exceeds the tolerable error range, and then control circuit 512 is just controlled multiplexer 510 by the adjustment of selecting signal SEL immediately and selected output M3 ' with second filter circuit 508 to be passed to output port N4 with as filtering output S_OUT.
Please note, control circuit 512 also can produce according to the statistics in synchronised clock CLK_SYNC cycle selects signal SEL, for instance, when control circuit 512 detect synchronised clock CLK_SYNC average period (its can be by a period of time in measurement to the statistics of Cycle Length calculate) different with the ideal value of scanning line period or detect the average period of synchronised clock CLK_SYNC and the difference of this ideal value (phase difference) when exceeding the tolerable error range, control circuit 512 just can be controlled multiplexer 510 by the adjustment of selecting signal SEL and select output M3 ' with second filter circuit 508 to be passed to output port N4 with as filtering output S_OUT, and the variation in this design also belongs to category of the present invention.
In addition, if filtration module 502 switches to the use of second filter circuit 508 at present, cycle/the average period that detects synchronised clock CLK_SYNC when control circuit 512 is follow-up is identical with the ideal value of scanning line period or the difference (phase difference) of cycle/average period of synchronised clock CLK_SYNC and this ideal value falls into the tolerable error range, then can select the output M3 ' of second filter circuit 508 is passed to output port N4 to export S_OUT as filtering by selecting signal SEL to control multiplexer 510, therefore, filtration module 502 just recovers to use the first default filter circuit 208 at this moment.
Fig. 6 is the flow chart of synchronizing signal amplitude limit method second embodiment of the present invention.Flow process shown in Figure 6 is applied to synchronizing signal amplitude limiter 500 shown in Figure 5, and in addition, if can obtain identical haply result, then step not necessarily will be carried out in accordance with order shown in Figure 6.The running of second embodiment of synchronizing signal amplitude limit method of the present invention can simply be summarized as follows:
Step 602: receiver, video input (for example sampled data of composite video signal).
Step 604: infinite impulse response filter is carried out in this video input handle (for example weighted average processing) to produce filtering output.
Step 606: the clip level that decides corresponding synchronizing signal composition (for example horizontal-drive signal composition) according to this filtering output.
Step 608: relatively this clip level and this filtering output is to produce the output of synchronizing signal amplitude limit.
Step 610: whether different whether the or difference (phase difference) of cycle/average period of synchronised clock CLK_SYNC and this ideal value exceed the tolerable error range and judge whether to switch to and differ from the predetermined Filtering Processing (for example low-pass filtering treatment) that this infinite impulse response filter is handled according to the ideal value of cycle/average period of synchronised clock CLK_SYNC and scanning line period, if, then execution in step 612, otherwise, get back to step 604 and continue to adopt this infinite impulse response filter to handle.
Step 612: this video input is scheduled to Filtering Processing to produce this filtering output.
Step 614: decide this clip level according to this filtering output.
Step 616: relatively this clip level and this filtering output is to produce this synchronizing signal amplitude limit output.
Step 618: whether identical whether the or difference (phase difference) of cycle/average period of synchronised clock CLK_SYNC and this ideal value fall into the tolerable error range and judge whether to need to recover to use this infinite impulse response filter to handle according to the ideal value of cycle/average period of synchronised clock CLK_SYNC and scanning line period, if, then execution in step 604, otherwise, getting back to step 612 and continue employing should predetermined Filtering Processing.
Because the those skilled in the art reads the details of operation that the technology contents of above-mentioned relative synchronous signal limiter device 500 should be understood each step afterwards easily, therefore, related description is not just given unnecessary details in addition in this.
Though the present invention discloses as above with regard to preferred embodiment, so it is not in order to limit the present invention.The persons of ordinary skill in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when the claims before looking define.
Claims (20)
1. a synchronizing signal amplitude limiter is characterized in that, includes:
Filtration module is used for handling the video input to produce filtering output, and this filtration module includes:
First filter circuit, it receives this video input, and infinite impulse response filter is carried out in this video input handle;
The clip level detector is coupled to this filtration module, exports in order to receive this filtering, and decides the clip level of corresponding synchronizing signal composition according to this filtering output; And
Comparator is coupled to this clip level detector and this filtration module, and in order to receiving this filtering output and this clip level, and relatively this clip level is exported to produce the synchronizing signal amplitude limit with this filtering output.
2. synchronizing signal amplitude limiter as claimed in claim 1 is characterized in that, this synchronizing signal composition is the horizontal-drive signal composition.
3. synchronizing signal amplitude limiter as claimed in claim 1 is characterized in that, this first filter circuit includes:
Storage element;
First multiplication unit, it is multiplied by first weighted value with each data in this video input, to produce the output of first multiplication;
Second multiplication unit is coupled to this storage element, is multiplied by second weighted value in order to each data in the result that this storage element is stored, to produce the output of second multiplication; And
Adder unit, be coupled to this first multiplication unit, this second multiplication unit and this storage element, export to produce addition with this second multiplication output in order to add up this first multiplication output, and this addition output is write to this storage element to upgrade corresponding each data in the stored result of this storage element.
4. synchronizing signal amplitude limiter as claimed in claim 3 is characterized in that, this storage element is a line buffer, and its buffer depth equals the predetermined total number of sample points of a scan line.
5. synchronizing signal amplitude limiter as claimed in claim 3 is characterized in that, this first filter circuit includes in addition:
The weighted value setup unit is coupled to this first multiplication unit and this second multiplication unit, in order to set this first weighted value and this second weighted value according to the characteristics of signals of this video input.
6. synchronizing signal amplitude limiter as claimed in claim 5 is characterized in that, this characteristics of signals is a signal to noise ratio.
7. synchronizing signal amplitude limiter as claimed in claim 6 is characterized in that, this first weighted value and this signal to noise ratio positive correlation, and this second weighted value and this signal to noise ratio negative correlation.
8. synchronizing signal amplitude limiter as claimed in claim 1 is characterized in that, this filtration module includes in addition:
Second filter circuit, it receives this video input, and Filtering Processing is scheduled in this video input, wherein should predetermined Filtering Processing be different from this performed infinite impulse response filter processing of this first filter circuit;
Multiplexer has control port, output port and a plurality of input port and is respectively coupled to this first filter circuit, second filter circuit, and wherein this output port is in order to export this filtering output of this filtration module; And
Control circuit is coupled to this control port, is used for producing selecting signal to this control port, to control this multiplexer the output of this first filter circuit or the output of this second filter circuit is passed to this output port.
9. synchronizing signal amplitude limiter as claimed in claim 8, it is characterized in that, this comparator inputs to clock-generating device with this synchronizing signal amplitude limit and handles producing synchronised clock, and this control circuit produces this selection signal based on cycle of this synchronised clock.
10. synchronizing signal amplitude limiter as claimed in claim 9 is characterized in that, this control circuit produces this selection signal according to the statistics in the cycle of this synchronised clock.
11. a synchronizing signal amplitude limit method is characterized in that, includes:
Handle the video input to produce filtering output, include:
Infinite impulse response filter is carried out in this video input to be handled;
Decide the clip level of corresponding synchronizing signal composition according to this filtering output; And
Relatively this clip level and this filtering output is to produce the output of synchronizing signal amplitude limit.
12. synchronizing signal amplitude limit method as claimed in claim 11 is characterized in that, this synchronizing signal composition is the horizontal-drive signal composition.
13. synchronizing signal amplitude limit method as claimed in claim 11 is characterized in that, this infinite impulse response filter pack processing contains:
Each data in this video input are multiplied by first weighted value, to produce the output of first multiplication;
Each data is multiplied by second weighted value in the result that storage element is stored, to produce the output of second multiplication; And
Add up this first multiplication output and export to produce addition, and this addition output is write to this storage element to upgrade corresponding each data in the stored result of this storage element with this second multiplication output.
14. synchronizing signal amplitude limit method as claimed in claim 13 is characterized in that, this storage element is a line buffer, and its buffer depth equals the predetermined total number of sample points of a scan line.
15. synchronizing signal amplitude limit method as claimed in claim 13 is characterized in that, this infinite impulse response filter is handled and is included in addition:
Characteristics of signals according to this video input is set this first weighted value and this second weighted value.
16. synchronizing signal amplitude limit method as claimed in claim 15 is characterized in that, this characteristics of signals is a signal to noise ratio.
17. synchronizing signal amplitude limit method as claimed in claim 16 is characterized in that, this first weighted value and this signal to noise ratio positive correlation, and this second weighted value and this signal to noise ratio negative correlation.
18. synchronizing signal amplitude limit method as claimed in claim 11 is characterized in that, handles this video input and includes in addition with the step that produces this filtering output:
Filtering Processing is scheduled in this video input, wherein should predetermined Filtering Processing be different from this infinite impulse response filter processing; And
The output of selecting this infinite impulse response filter maybe should predetermined Filtering Processing output be used as this filtering output.
19. synchronizing signal amplitude limit method as claimed in claim 18, it is characterized in that, the output of this synchronizing signal amplitude limit is handled producing synchronised clock via clock-generating device in addition, and the step that the output that the output of selecting this infinite impulse response filter maybe should predetermined Filtering Processing is used as this filtering output includes:
Maybe should be scheduled to the output of Filtering Processing based on the output that the cycle of this synchronised clock is selected to export this infinite impulse response filter.
20. synchronizing signal amplitude limit method as claimed in claim 19 is characterized in that, step of the output that the output of selecting to export this infinite impulse response filter based on the cycle of this synchronised clock maybe should predetermined Filtering Processing includes:
The output of selecting to export this infinite impulse response filter according to the statistics in cycle of this synchronised clock maybe should predetermined Filtering Processing output.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103220456A (en) * | 2012-01-21 | 2013-07-24 | 宏观微电子股份有限公司 | Signal processing device |
| CN103472810A (en) * | 2013-09-29 | 2013-12-25 | 贵州电力试验研究院 | Amplitude limiting method of multi-execution-loop control system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072530A (en) * | 1997-12-31 | 2000-06-06 | Telecruz Technology, Inc. | Flicker filter and interlacer implemented in a television system displaying network application data |
| TWI258137B (en) * | 2003-04-10 | 2006-07-11 | Via Optical Solution Inc | Method and related optical disk accessing apparatus for calibrating optical disk tilt servo system according to non-constant relation between locations and tilt angles of optical disk |
| US7605867B1 (en) * | 2003-05-20 | 2009-10-20 | Pixelworks, Inc. | Method and apparatus for correction of time base errors |
| JP2005276289A (en) * | 2004-03-24 | 2005-10-06 | Sanyo Electric Co Ltd | Slice level control circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103220456A (en) * | 2012-01-21 | 2013-07-24 | 宏观微电子股份有限公司 | Signal processing device |
| CN103472810A (en) * | 2013-09-29 | 2013-12-25 | 贵州电力试验研究院 | Amplitude limiting method of multi-execution-loop control system |
| CN103472810B (en) * | 2013-09-29 | 2016-02-10 | 贵州电力试验研究院 | A kind of amplitude limit method performing loop control system more |
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| CN102148920B (en) | 2013-03-13 |
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