CN102136791A - Power supply control circuit - Google Patents
Power supply control circuit Download PDFInfo
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- CN102136791A CN102136791A CN2010100231489A CN201010023148A CN102136791A CN 102136791 A CN102136791 A CN 102136791A CN 2010100231489 A CN2010100231489 A CN 2010100231489A CN 201010023148 A CN201010023148 A CN 201010023148A CN 102136791 A CN102136791 A CN 102136791A
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- switch
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a power supply control circuit, comprising a switch and a control unit, wherein the switch is coupled between a standby power supply and a main machine system and is controlled by the control unit. The control unit controls whether a first switch is turned on according to a power supply switch signal and a sleeping signal output by the main machine system. When the main machine system enters into a soft shutdown state, the control unit closes the first switch to cut off the power supply of the standby power supply to a main machine system, thus the power consumption is reduced.
Description
Technical field
The invention relates to a kind of energy-saving circuit, and particularly relevant for a kind of power control circuit that reduces power consumption under the soft-off pattern.
Background technology
Along with the subject under discussion of global warming more and more is much accounted of, environmental consciousness is increasingly important, how every electrical home appliances relevant with electrical source consumption, plant equipment and computer product or the like all use towards minimum electric power to reach the direction design as purpose of maximum usefulness.
With reference to " the energy saving standby standard regulations of office and home electronic appliance product " draft that executive committee of European Union of European Union stipulates in by the end of June, 2008 in, this draft will be resolved for No. 1275/2008 by executive committee the end of the year 2008.In draft, stipulate 4 big classes such as household appliances, information-technology products, consumption electronic product and toy, amusement, sports equipment, after regulations came into force 1 year (end of the year 2009), all are subjected to the power consumption of the standby of the product of standard/restart pattern (standby/reactivation) must not surpass 1W.
Therefore, all power consumptions that will must meet above-mentioned standby/restart pattern (standby/reactivation) at the consumption electronic product that European Union sells must not surpass the power specifications of 1W.Manufacturer must provide relevant information to confirm whether product meets the energy saving standby standard, as the test parameter data of energy saving standby, the characteristic of test accordance assessment apparatus etc.Yet present consumption electronic products do not have relevant power saving design to meet the regulation of European Union's energy saving standby standard regulations.
Summary of the invention
The invention provides a kind of power control circuit, can under the soft-off pattern, standby power be closed to reduce power consumption.When system prepared to restart, power control circuit can provide standby power to system again, allowed system's normal operation.Power control circuit can be managed standby power automatically to reach the effect of energy saving.
The present invention proposes a kind of power control circuit, comprises one first switch and a control unit.First switch is coupled between a standby power and the host computer system, and control unit is coupled to first switch, and controls the whether conducting of first switch according to the sleep signal that a power switch signal and host computer system are exported.Wherein, when host computer system entered a soft-off state, control unit was closed first switch to stop to provide this standby power to this host computer system.
In an embodiment of the present invention, wherein when the power switch signal activation made host computer system enter an open state by the soft-off state, control unit conducting first switch was to provide standby power to host computer system.
In an embodiment of the present invention, above-mentioned power control circuit more comprises a second switch, be coupled between power switch signal and the host computer system, and a control end of second switch is coupled to the shared contact of first switch and host computer system.One first resistance is coupled between standby power and the power switch signal and one second resistance, is coupled between the control end of the shared contact of second switch and host computer system and second switch.
In an embodiment of the present invention, above-mentioned control unit comprises a D flip-flop, an inverter, one the 3rd resistance, one the 4th resistance, one the 5th resistance and an electric capacity.D flip-flop has an input, a clock pulse end, an activation end and an output, and the activation end is coupled to sleep signal, and output is coupled to a control end of first switch.The input of inverter is coupled to the output of D flip-flop, and the output of inverter is coupled to the input of D flip-flop.The 3rd resistance is coupled between the input and standby power of D flip-flop, and the 4th resistance is coupled between the clock pulse end and power switch signal of D flip-flop.The 5th resistance is coupled between the output and an earth terminal of D flip-flop.Electric capacity is coupled between the clock pulse end and an earth terminal of D flip-flop.
In an embodiment of the present invention, above-mentioned first switch is a PMOS transistor, and second switch is a nmos pass transistor.(this soft-off state then comprises the S5 state in the ACPI standard to above-mentioned sleep signal for advancedconfiguration and power interface, the ACPI) index signal of the S4 state in the standard in order to meet advanced configuration and electricity interface.
Based on above-mentioned, the present invention can stop to provide the host computer system of standby power to the rear end when the soft-off state, is reduced in power consumption under the soft-off state whereby to reach the effect of energy saving.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 illustrates the power control circuit of one embodiment of the invention.
Fig. 2 illustrates the circuit diagram of the power control circuit 100 of present embodiment.
Fig. 3 illustrates the mode chart that is entered open state by off-mode.
Fig. 4 illustrates the oscillogram that is entered armed state by open state.
Fig. 5 illustrates the oscillogram that is entered off-mode by open state.
The main element symbol description:
100: power control circuit
110: control unit
120: the first switches
130: second switch
140: host computer system
The 210:D D-flip flop
220: inverter
310,410,510,520: pulse signal
320: signal waveform
SB: standby power
SBB: second standby power
SW: power switch signal
SWB: second source switching signal
SLP: sleep signal
The index signal of S3:S3 state
The Q1:PMOS transistor
The Q2:NMOS transistor
R1～R5: resistance
C1: electric capacity
The output of Q:D D-flip flop 210
The input of D:D D-flip flop 210
The activation end of OE:D D-flip flop 210
The clock pulse end of CP:D D-flip flop 210
T1, T2: time
Embodiment
Please refer to Fig. 1, Fig. 1 illustrates the power control circuit of one embodiment of the invention, power control circuit 100 comprises control unit 110, first switch 120 and second switch 130, control unit 110 is coupled to first switch 120 and second switch 130, and the conducting of controlling first switch 120 and second switch 130 according to the sleep signal SLP that power switch signal SW and host computer system 140 are exported whether.First switch 120 is coupled between standby power SB and the host computer system 140, whether will export host computer system 140 in order to decision.120 adjusted standby power SB represent with the second standby power SBB via first switch.130 of second switches are coupled between power switch signal SW and the host computer system 140, and its control end is coupled to the second standby power SBB.When the second standby power SBB activation, second switch 130 conductings, and the signal that second switch 130 is exported is represented with second source switching signal SWB.
Sleep signal SLP can be used to represent the power supply status of host computer system 140, be example in the present embodiment with the notebook computer, sleep signal SLP is advanced configuration and power interface (advanced configuration andpower interface, ACPI) index signal of the S4 state in the standard.Host computer system 140 for example is a motherboard.Sleep signal SLP can be produced by South Bridge chip in the host computer system 140 or chipset.Standby power SB for example is the standby power of 5V, can use for the notebook computer standby at Connect Power source plug or produce when loading onto battery of notebook computer.Power switch signal SW is produced by mains switch, and host computer system 140 can be carried out boot program or enter soft-off state (soft-off state) by open state according to power switch signal SW decision.In the present embodiment, the soft-off state is S5 pattern or the S4 pattern in the ACPI standard.With the ACPI standard, when computer entered the soft-off state, sleep signal SLP just can be converted to logic low potential thereupon.
Next, further specify the circuit structure of power control circuit 100, please refer to Fig. 2, Fig. 2 illustrates the circuit diagram of the power control circuit 100 of present embodiment.First switch 120 utilizes PMOS transistor (Pchannel metal oxide semiconductor transistor, be called for short PMOS) Q1 enforcement, 130 of second switches utilize nmos pass transistor (N channel metal oxide semiconductor transistor is called for short NMOS) Q2 to implement.110 of control units utilize D flip-flop 210 and peripheral circuit to form, and peripheral circuit mainly comprises resistance R 3～R5, capacitor C 1 and inverter 220.PMOS transistor Q1 is coupled between standby power SB and the host computer system 140, and its grid (control end) is coupled to the output Q of D flip-flop 210.Nmos pass transistor Q2 is coupled between power switch signal SW and the host computer system 140, and its grid (control end) is coupled to the second standby power SBB.Standby power SB via PMOS transistor Q1 output represents with the second standby power SBB, and the power switch signal SW that exports via nmos pass transistor Q2 represents with second source switching signal SWB.
Next, cooperate the action of power control circuit 100 in the oscillogram key diagram 2.Please refer to Fig. 3, Fig. 3 illustrate by off-mode enter open state mode chart.Wherein L shows logic low potential, H presentation logic high potential.After system plugged in plug, standby power SB just can maintain logic high potential (H), and sleep signal SLP can maintain logic low potential with activation D flip-flop 210.Power switch signal SW can produce a rising edge because of the delay circuit that resistance R 4 and capacitor C 1 are constituted.D flip-flop can be converted to high potential with output Q because of the transition (by L to H) of power switch signal SW, not conducting of PMOS transistor Q1 this moment, and the second standby power SBB can maintain electronegative potential.The input D of D flip-flop 120 can be in logic low potential because of the relation of inverter 220.
When mains switch was pressed, power switch signal SW can produce the pulse signal 310 of a negative sense, and the rising edge of this pulse signal 310 can make the output Q of D flip-flop 210 be converted to electronegative potential (because this moment, inverter 220 was output as logic low potential).PMOS transistor Q2 can be switched on and make that the second standby power SBB is drawn high and be high potential, shown in signal waveform 320.Be because due to the response delay of D flip-flop 210 time of delay between signal waveform 320 and the pulse signal 310, can be according to the different and difference to some extent of employed element model.In the present embodiment, D flip-flop 210 for example is FairchildSemiconductor, the D flip-flop of model NC7SZ374, but the present invention is not limited.
After the PMOS transistor Q2 conducting, the high potential of second standby power SBB meeting conducting nmos pass transistor Q2 allows second source switching signal SWB draw high and is high potential.At this moment, host computer system 140 can be carried out boot program because of drawing high of second source switching signal SWB.At this moment, sleep signal SLP can draw high because of system boot and be high potential, the signal S3 of expression S3 state also can with draw high and be high potential.
Fig. 4 illustrates the oscillogram that is entered armed state by open state, in open state, and PMOS transistor Q1 and all conductings of nmos pass transistor Q2, the standby power SB and the first standby power SBB maintain logic high potential.The output Q of D flip-flop 120 maintains logic low potential, and the input D of D flip-flop 120 then is in logic high potential.When mains switch is pressed and when making power switch signal SW produce pulse duration less than 4 seconds pulse signal 410 (time T1 was less than 4 seconds), second source switching signal SWB can produce identical pulse signal and with notice host computer system 140 power supply status be switched to battery saving mode, for example the S3 state.Because this moment, sleep signal SLP maintained high potential, so D flip-flop 120 anergies, its output Q maintains electronegative potential makes PMOS transistor Q1 and nmos pass transistor Q2 still maintain under the state of conducting.
Fig. 5 illustrates the oscillogram that is entered off-mode by open state, when being pressed, mains switch surpassed 4 seconds and when making power switch signal SW produce pulse duration (time T2 was greater than 4 seconds) greater than 4 seconds pulse signal 510, host computer system 140 can enter soft-off state (being the S5 state), this moment, sleep signal SLP can be converted to logic low potential, and the index signal of expression S3 state also can be converted to electronegative potential.Because the electronegative potential of sleep signal SLP meeting activation D flip-flop 210, D flip-flop 210 can be converted to logic high potential with output Q because of the rising edge of pulse signal 510, PMOS transistor Q1 with close and make the second standby power SBB transfer logic low potential to reduce power consumption.Because can changing with power switch signal SW, second source switching signal SWB closes up to nmos pass transistor Q2.Therefore before the second standby power SBB reduced to logic low potential, second source switching signal SWB can produce the pulse signal 520 of a forward.Because host computer system 140 has entered the soft-off pattern this moment, so pulse signal 520 can't impact system, can ignore.
Can know wave form varies and the circuit operation mode of the system of learning under open state, armed state and soft-off state via the explanation of above-mentioned Fig. 3～Fig. 5.Power control circuit 100 can under the soft-off state, can stop to provide standby power SB to the host computer system 140 of rear end to reduce power consumption.Under open state and armed state, power control circuit 100 can normally provide standby power SB host computer system 140 to the rear end.Because at the soft-off state, system only need provide the working power of power control circuit 100, and standby power SB need be provided the host computer system 140 to the rear end, therefore the electric power that is consumed can greatly be reduced to tens of micromicroamperes (microampere, μ A), about 0.05 watt (Watt) is far below the desired 1 watt standby power consumed power of European Union.In addition, it should be noted that power control circuit 100 of the present invention need can be applicable to the various electronic installations of power supply, for example computer, notebook computer or little electricity etc. all can be brought into play it and reduce the effect that stand-by electric consumes.Above-mentioned D flip-flop 210 only is an embodiment of the invention process control unit 110, control unit 110 for example also can use embedded chip or other Digital Logical Circuits to realize its function, the present technique field has knows that usually the knowledgeable is after via exposure of the present invention, should know all the other possible implementation easily by inference, be not repeated at this.
In sum, the present invention sets up control circuit between standby power and system, when system be in soft-off pattern following time can active stop supplies standby power to the system of rear end to reduce power consumption, reach the effect of energy saving whereby.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (13)
1. power control circuit comprises:
One first switch is coupled between a standby power and the host computer system; And
One control unit is coupled to this first switch, and a sleep signal of exporting according to a power switch signal and this host computer system is controlled the whether conducting of this first switch;
Wherein, when this host computer system entered a soft-off state, this control unit was closed this first switch to stop to provide this standby power to this host computer system.
2. power control circuit as claimed in claim 1, it is characterized in that, when this power switch signal activation made this host computer system enter an open state by this soft-off state, this first switch of this control unit conducting was to provide this standby power to this host computer system.
3. power control circuit as claimed in claim 1 is characterized in that, more comprises:
One second switch is coupled between this power switch signal and this host computer system, and a control end of this second switch is coupled to the shared contact of this first switch and this host computer system.
4. power control circuit as claimed in claim 3 is characterized in that, more comprises:
One first resistance is coupled between this standby power and this power switch signal; And
One second resistance is coupled between this control end of the shared contact of this second switch and this host computer system and this second switch.
5. power control circuit as claimed in claim 3 is characterized in that, this second switch is a nmos pass transistor, and this control end of this second switch is the grid of this nmos pass transistor.
6. power control circuit as claimed in claim 1 is characterized in that, this control unit comprises:
One D flip-flop has an input, a clock pulse end, an activation end and an output, and this activation end is coupled to this sleep signal, and this output is coupled to a control end of this first switch;
One inverter, the input of this inverter are coupled to this output of this D flip-flop, and the output of this inverter is coupled to this input of this D flip-flop;
One the 3rd resistance is coupled between this input and this standby power of this D flip-flop; And
One the 4th resistance is coupled between this clock pulse end and this power switch signal of this D flip-flop.
7. power control circuit as claimed in claim 6 is characterized in that, this control unit more comprises:
One the 5th resistance is coupled between this output and an earth terminal of this D flip-flop.
8. power control circuit as claimed in claim 6 is characterized in that, this control unit more comprises:
One electric capacity is coupled between this clock pulse end and an earth terminal of this D flip-flop.
9. power control circuit as claimed in claim 1 is characterized in that, this first switch is a PMOS transistor.
10. power control circuit as claimed in claim 1 is characterized in that, this power switch signal is to be produced by a mains switch.
11. power control circuit as claimed in claim 1 is characterized in that, this sleep signal is the index signal that meets the S4 state in advanced configuration and the electricity interface standard, and this soft-off state then comprises the S5 state in advanced configuration and the electricity interface standard.
12. power control circuit as claimed in claim 1 is characterized in that, this standby power is a 5V standby power.
13. power control circuit as claimed in claim 1 is characterized in that, when this system host was in this soft-off state, this sleep signal was a logic low potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100231489A CN102136791A (en) | 2010-01-22 | 2010-01-22 | Power supply control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100231489A CN102136791A (en) | 2010-01-22 | 2010-01-22 | Power supply control circuit |
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|---|---|
| CN102136791A true CN102136791A (en) | 2011-07-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010100231489A Pending CN102136791A (en) | 2010-01-22 | 2010-01-22 | Power supply control circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138376A (en) * | 2011-11-25 | 2013-06-05 | 环旭电子股份有限公司 | Power switching circuit and power switching method thereof |
| CN103676752A (en) * | 2012-09-13 | 2014-03-26 | 昆达电脑科技(昆山)有限公司 | Power front-end monitoring device |
| CN103699175A (en) * | 2012-09-28 | 2014-04-02 | 鸿富锦精密工业(武汉)有限公司 | Mainboard |
| CN106325461A (en) * | 2015-06-23 | 2017-01-11 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| TWI640147B (en) * | 2017-02-23 | 2018-11-01 | 廣達電腦股份有限公司 | Control circuit and a method for managing a power supply unit associated with a system board thereby |
| CN110874109A (en) * | 2018-08-30 | 2020-03-10 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN111142646A (en) * | 2018-11-02 | 2020-05-12 | 佛山市顺德区顺达电脑厂有限公司 | Server system and power saving method thereof |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138376A (en) * | 2011-11-25 | 2013-06-05 | 环旭电子股份有限公司 | Power switching circuit and power switching method thereof |
| CN103138376B (en) * | 2011-11-25 | 2015-04-29 | 环旭电子股份有限公司 | Power switching circuit and power switching method thereof |
| CN103676752A (en) * | 2012-09-13 | 2014-03-26 | 昆达电脑科技(昆山)有限公司 | Power front-end monitoring device |
| CN103699175A (en) * | 2012-09-28 | 2014-04-02 | 鸿富锦精密工业(武汉)有限公司 | Mainboard |
| CN106325461A (en) * | 2015-06-23 | 2017-01-11 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| TWI640147B (en) * | 2017-02-23 | 2018-11-01 | 廣達電腦股份有限公司 | Control circuit and a method for managing a power supply unit associated with a system board thereby |
| CN110874109A (en) * | 2018-08-30 | 2020-03-10 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN110874109B (en) * | 2018-08-30 | 2021-11-16 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN111142646A (en) * | 2018-11-02 | 2020-05-12 | 佛山市顺德区顺达电脑厂有限公司 | Server system and power saving method thereof |
| CN111142646B (en) * | 2018-11-02 | 2023-11-07 | 佛山市顺德区顺达电脑厂有限公司 | Server system and power saving method thereof |
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Application publication date: 20110727 |