CN102130175B - Vertical transistor structure - Google Patents
Vertical transistor structure Download PDFInfo
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- CN102130175B CN102130175B CN 201010613431 CN201010613431A CN102130175B CN 102130175 B CN102130175 B CN 102130175B CN 201010613431 CN201010613431 CN 201010613431 CN 201010613431 A CN201010613431 A CN 201010613431A CN 102130175 B CN102130175 B CN 102130175B
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Abstract
The invention relates to a vertical transistor structure. The vertical transistor structure comprises a substrate, a source, a first gate, a first insulating layer, a second gate, a gate insulating layer, a drain, a second insulating layer and a semiconductor channel layer, wherein the source is arranged on the substrate; the first gate is arranged on the source and has at least one first throughhole; the first insulating layer is arranged between the first gate and the source; the second gate is arranged on the first gate and has at least one second through hole; the gate insulating layer is arranged between the first gate and the second gate and has at least one third through hole; the first through hole, the second through hole and the third through hole are communicated with one another; the drain is arranged on the second gate; the second insulating layer is arranged between the second gate and the drain; and the semiconductor channel layer is filled into the first, second and third through holes. The invention provides a vertical transistor structure, which has high conduction current and can reduce the occurrence of off-current.
Description
Technical field
The present invention relates to a kind of transistor arrangement, particularly a kind of vertical type bipolar transistor structure.
Background technology
In order to improve the service speed of integrated circuit, and meet the consumer for miniaturization electronics need for equipment, the transistor size in the semiconductor device has the trend that continues to dwindle.Yet along with dwindling of transistor size, transistorized channel region length also shortens thereupon, so causes transistor to suffer serious short-channel effect (short channel effect) and conducting electric current (on current) degradation problem down.At this problem, known a kind of solution is the dopant concentration that improves in the channel region, but this kind practice can cause the increase of leakage current (leakage current) on the contrary, and influences the reliability of assembly.
Therefore, in order to overcome the problems referred to above, industry proposes the transistor arrangement of horizontal direction is changed into the transistor arrangement of vertical direction in recent years.Thus, service speed and the integration of integrated circuit can be promoted, and problems such as short-channel effect can be avoided.For instance, the rectilinear OTFT of delivering at Advanced Materials in 2007 with people such as Fujimoto Kiyoshi, it is that the static that utilizes polystyrene (polystrene) itself to bring can produce mutually exclusive characteristic and is used as the shelves version, makes rectilinear OTFT in this way.Yet, because the rectilinear OTFT of this kind mainly is to utilize the contact interface of aluminium and semiconductor layer can form vague and general layer to be used as insulating barrier, so its voltage that can use can not be too big.Moreover (on-off current ratio) is also little for the switch current ratio of this structure, and leakage current (off current) is also higher.Therefore, present vertical type bipolar transistor still has very big improvement space, the target of field institute active research for this reason in structural design and channel control.
Summary of the invention
In order to overcome the problems referred to above, the object of the present invention is to provide a kind of vertical type bipolar transistor structure, it has higher conducting electric current, and can effectively reduce the situation generation of leakage current (off current).
To achieve these goals, technical scheme of the present invention is: a kind of vertical type bipolar transistor structure, it comprises a substrate, one source pole, one first gate, one first insulating barrier, one second gate, a lock insulating barrier, a drain, one second insulating barrier and semiconductor channel layer.Source electrode is disposed on the substrate.First gate is disposed on the source electrode, and has at least one first perforation, and wherein first perforation runs through first gate.First insulating barrier is disposed between first gate and the source electrode.Second gate is disposed on first gate, and has at least one second perforation, and wherein second perforation runs through second gate.The lock insulating barrier is disposed between first gate and second gate, and has at least one the 3rd perforation, and wherein the 3rd perforation runs through the lock insulating barrier, and first perforation, second perforation and the 3rd perforation are interconnected.Drain is disposed on second gate.Second insulating barrier is disposed between second gate and the drain.The channel semiconductor layer is filled in first perforation, second perforation and the 3rd perforation; This first exhausted insulating barrier has at least one the 4th perforation, and the part semiconductor channel layer more extends in the 4th perforation; This second insulating barrier has at least one the 5th perforation, and the part semiconductor channel layer more extends in the 5th perforation, and the part semiconductor channel layer in part drain and the 5th perforation is connected.
In one embodiment of this invention, above-mentioned vertical type bipolar transistor structure more comprises one first protective layer, is disposed on the inwall of first perforation.
In one embodiment of this invention, the material of the first above-mentioned protective layer comprises aluminium oxide.
In one embodiment of this invention, above-mentioned vertical type bipolar transistor structure more comprises one second protective layer, is disposed on the inwall of second perforation.
In one embodiment of this invention, the material of the second above-mentioned protective layer comprises aluminium oxide.
In one embodiment of this invention, above-mentioned lock insulating barrier has more at least one contact hole, and first gate sees through contact hole with second gate and is connected.
In one embodiment of this invention, above-mentioned channel semiconductor layer is shaped as annular.
In one embodiment of this invention, above-mentioned source electrode is shaped as annular.
Based on above-mentioned, in vertical type bipolar transistor structure of the present invention, the semiconductor channel layer be filled in first gate, second gate with the perforation of door insulating barrier in (in first perforation, second perforation and the 3rd perforation that meaning namely is interconnected), therefore the vertical type bipolar transistor structure can have higher conducting electric current, and effectively reduces the situation generation of leakage current (off current).
Description of drawings
Fig. 1 is the schematic top plan view of a kind of vertical type bipolar transistor structure of one embodiment of the invention.
Fig. 2 is the generalized section along the line I-I of the vertical type bipolar transistor structure of Fig. 1.
[primary clustering symbol description]
100: the vertical type bipolar transistor structure
110: substrate
120: source electrode
130: the first gates
132: the first perforations
140: the first insulating barriers
142: the four perforations
150: the second gates
152: the second perforations
160: the lock insulating barrier
162: the three perforations
164: contact hole
170: drain
180: the second insulating barriers
182: the five perforations
190: the channel semiconductor layer
195: the first protective layers
197: the second protective layers.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Fig. 1 is the schematic top plan view of a kind of vertical type bipolar transistor structure of one embodiment of the invention.Fig. 2 is the generalized section along the line I-I of the vertical type bipolar transistor structure of Fig. 1.Please also refer to Fig. 1 and Fig. 2, in the present embodiment, vertical type bipolar transistor structure 100 comprises a substrate 110, one source pole 120, one first gate 130, one first insulating barrier 140, one second gate 150, a lock insulating barrier 160, a drain 170, one second insulating barrier 180 and semiconductor channel layer 190.The substrate 110 of present embodiment for example is a flexible base plate or a rigid substrates, for example polyester polymers (PET) or polyimides (polyimide) of the material of flexible base plate wherein, and the material of rigid substrates for example is glass.
Specifically, source electrode 120 is disposed on the substrate 110, wherein the material of source electrode 120 for example be indium tin oxide (Indium Tin Oxide, ITO).First gate 130 is disposed on the source electrode 120, and has at least one first perforation 132, and wherein first perforation 132 runs through first gate 130.In the present embodiment, the material of first gate 130 for example is aluminium or other metal material, and the thickness of first gate 130 for example is about 60 nanometers (nm).First insulating barrier 140 is disposed between first gate 130 and the source electrode 120, and wherein first insulating barrier 140 has at least one the 4th perforation 142, and the 4th perforation 142 is communicated with first perforation 132.In addition, the material of first insulating barrier 140 for example is silica (SiOx), and the thickness of first insulating barrier 140 about 50 nanometers (nm) for example.
Second gate 150 is disposed on first gate 130, and has at least one second perforation 152, and wherein second perforation 152 runs through second gate 150.In the present embodiment, the material of second gate 150 for example is aluminium or other metal material, and the thickness of second gate 150 for example is about 60 nanometers (nm).Lock insulating barrier 160 is disposed between first gate 130 and second gate 150, and has at least one the 3rd perforation 162, wherein the 3rd perforation 162 runs through lock insulating barrier 160, and first perforation 132, second perforation 152, the 3rd perforation 162 and the 4th perforation 142 are interconnected.In the present embodiment, the material of lock insulating barrier 160 for example is silica (SiOx), and the thickness of lock insulating barrier 160 about 50 nanometers (nm) for example.
Drain 170 is disposed on second gate 150, and wherein the material of drain 170 comprises gold, aluminium or indium tin oxide (ITO).Second insulating barrier 180 is disposed between second gate 150 and the drain 170, and wherein second insulating barrier 180 has at least one the 5th perforation 182, the five perforations 182 and first perforation 132, second perforation 152, the 3rd perforation 162 and the 4th perforation 142 are interconnected.In addition, the material of second insulating barrier 180 for example is silica (SiOx), and the thickness of second insulating barrier 180 about 50 nanometers (nm) for example.
Channel semiconductor layer 190 is filled in first perforation 132, second perforation 152 and the 3rd perforation 162, and wherein part semiconductor channel layer 190 more extends in the 4th perforation 142 and the 5th perforation 182, and fills up the 4th perforation 142.Moreover the part drain 170 of present embodiment is connected with part semiconductor channel layer 190 in the 5th perforation 182.In addition, the material of the channel semiconductor layer 190 of present embodiment comprises organic semiconductor material, for example be Wu Huansu (pentacene), or inorganic semiconductor, for example be indium oxide gallium zinc (Indium Gallium Zinc Oxide, IGZO), zinc oxide (ZnO), amorphous silicon (a-Si) or crystal silicon (crystal Si).Particularly, in the present embodiment, the shape of channel semiconductor layer 190 for example is annular, and the shape of source electrode 120 also for example is annular.
Since the channel semiconductor layer 190 of present embodiment be first perforation 132 that is filled in first gate 130, second gate 150 second perforation with 152 with the 3rd perforation 162 of door insulating barrier 160 in, therefore except can be by the thickness that changes first gate 130 and second gate 150, control the length of channel semiconductor layer 190, outside the problems such as short-channel effect that produced when can avoid size of components to dwindle, the vertical type bipolar transistor structure 100 of present embodiment also can have higher conducting electric current, and can effectively reduce the situation generation of leakage current.Moreover; because channel semiconductor layer 190 is to be filled in first perforation 132, second perforation with in the 152 and the 3rd perforation 162, so present embodiment need not form an etch stop layer (etching stop layer) again and protects channel semiconductor layer 190 to avoid the erosion of etching solution in the processing procedure of back segment.Thus, can reduce fabrication steps and reducing production costs.
In addition; the vertical type bipolar transistor structure 100 of present embodiment more comprises one first protective layer 195 and one second protective layer 197; wherein first protective layer 195 is disposed on the inwall of first perforation 132, and second protective layer 197 is disposed on the inwall of second perforation 152.In the present embodiment, the material of first protective layer 195 and second protective layer 197 for example is aluminium oxide.Wherein, the generation type of first protective layer 195 and second protective layer 197 for example is to adopt modes such as oxygen electricity slurry equipment or electrochemistry to carry out oxidation reaction to first gate 130 of metal material (for example being aluminium) and second gate 150, forms aluminium oxide with the inwall in first perforation 132 and second perforation 152.
In other words; present embodiment can utilize oxidation reaction to form first protective layer 195 and second protective layer 197 of a high compactness and high-k in first gate 130 and second gate 150; with increase vertical type bipolar transistor structure 100 operable voltage ranges, and can improve switch current ratio (on-off current ratio).In addition, because the channel semiconductor layer 190 of ring-type is surrounded by first gate 130 of metal material and second gate 150, therefore can have and reduce or isolated external electromagnetic ripple or interference of noise.Moreover in the vertical type bipolar transistor structure 100 of present embodiment, lock insulating barrier 160 also has more at least one contact hole 164, and wherein first gate 130 and second gate 150 can see through contact hole 164 and be connected and have identical bias voltage.
What deserves to be mentioned is, the present invention does not limit the form of lock insulating barrier 160, though being embodied as, the lock insulating barrier 160 that reaches mentioned herein has the 3rd perforation 162 and contact hole 164, but in other embodiment, lock insulating barrier 160 also can not have contact hole 164, that is to say, first gate 130 is not connected each other with second gate 150, can import different first gate 130 and second gates 150 of being biased into respectively, and produce different electrical effects.In brief, the rectilinear electricity that Fig. 2 illustrates through structure 100 only for illustrating, not as limit.
In addition, in the embodiment that other does not illustrate, those skilled in the art is when can according to actual demand, and selecting aforementioned components for use, to reach required technique effect with reference to the explanation of above-described embodiment.
In sum, since channel semiconductor layer of the present invention be filled in first gate first perforation, second gate second perforation with the 3rd perforation of door insulating barrier in, and extend in the 4th perforation and the 5th perforation, wherein first perforation, second perforation, the 3rd perforation, the 4th perforation and the 5th perforation are interconnected.Therefore, vertical type bipolar transistor structure of the present invention can have higher conducting electric current and the long channel semiconductor layer of length, and can effectively reduce the situation generation of leakage current.In other words, the present invention can be by the thickness that changes first gate and second gate, and control the length of the semiconductor channel layer of vertical type bipolar transistor structure exactly, and then the problems such as short-channel effect that produce can avoid size of components to dwindle the time.
Moreover; utilize oxidation reaction in first gate and second gate, to form first protective layer and second protective layer of a high compactness and high-k; the operable voltage range of vertical type bipolar transistor structure can be increased, and switch current ratio (on-off current ratio) can be improved.In addition, because the channel semiconductor layer of ring-type is surrounded by first gate of metal material and second gate, therefore can have and reduce or isolated external electromagnetic ripple or interference of noise.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (8)
1. a vertical type bipolar transistor structure is characterized in that, comprising:
One substrate;
One source pole is disposed on this substrate;
One first gate is disposed on this source electrode, and has at least one first perforation, and wherein this first perforation runs through this first gate;
One first insulating barrier is disposed between this first gate and this source electrode;
One second gate is disposed on this first gate, and has at least one second perforation, and wherein this second perforation runs through this second gate;
One lock insulating barrier is disposed between this first gate and this second gate, and has at least one the 3rd perforation, and wherein the 3rd perforation runs through this lock insulating barrier, and this first perforation, this second perforation and the 3rd perforation are interconnected;
One drain is disposed on this second gate;
One second insulating barrier is disposed between this second gate and this drain; And
The semiconductor channel layer is filled in this first perforation, this second perforation and the 3rd perforation; This first insulating barrier has at least one the 4th perforation, and this channel semiconductor layer of part more extends in the 4th perforation; This second insulating barrier has at least one the 5th perforation, and this channel semiconductor layer of part more extends in the 5th perforation, and interior this channel semiconductor layer of part of part this drain and the 5th perforation is connected.
2. vertical type bipolar transistor structure according to claim 1 is characterized in that: more comprise one first protective layer, be disposed on the inwall of this first perforation.
3. vertical type bipolar transistor structure according to claim 2, it is characterized in that: the material of this first protective layer comprises aluminium oxide.
4. vertical type bipolar transistor structure according to claim 1 is characterized in that: more comprise one second protective layer, be disposed on the inwall of this second perforation.
5. vertical type bipolar transistor structure according to claim 4, it is characterized in that: the material of this second protective layer comprises aluminium oxide.
6. vertical type bipolar transistor structure according to claim 1, it is characterized in that: this lock insulating barrier has more at least one contact hole, and this first gate sees through this contact hole with this second gate and is connected.
7. vertical type bipolar transistor structure according to claim 1 is characterized in that: this channel semiconductor layer be shaped as annular.
8. vertical type bipolar transistor structure according to claim 1 is characterized in that: this source electrode be shaped as annular.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010613431 CN102130175B (en) | 2010-12-30 | 2010-12-30 | Vertical transistor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010613431 CN102130175B (en) | 2010-12-30 | 2010-12-30 | Vertical transistor structure |
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| Publication Number | Publication Date |
|---|---|
| CN102130175A CN102130175A (en) | 2011-07-20 |
| CN102130175B true CN102130175B (en) | 2013-09-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010613431 Expired - Fee Related CN102130175B (en) | 2010-12-30 | 2010-12-30 | Vertical transistor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113035954B (en) * | 2021-02-25 | 2022-09-02 | 泉芯集成电路制造(济南)有限公司 | Full-surrounding gate horizontal penetration type transistor and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6018176A (en) * | 1995-05-26 | 2000-01-25 | Samsung Electronics Co., Ltd. | Vertical transistor and memory cell |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7579615B2 (en) * | 2005-08-09 | 2009-08-25 | Micron Technology, Inc. | Access transistor for memory device |
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- 2010-12-30 CN CN 201010613431 patent/CN102130175B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6018176A (en) * | 1995-05-26 | 2000-01-25 | Samsung Electronics Co., Ltd. | Vertical transistor and memory cell |
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| CN102130175A (en) | 2011-07-20 |
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Granted publication date: 20130911 Termination date: 20191230 |