CN102075181B - Frequency synthesizer and frequency-locked loop - Google Patents
Frequency synthesizer and frequency-locked loop Download PDFInfo
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- CN102075181B CN102075181B CN2009102331313A CN200910233131A CN102075181B CN 102075181 B CN102075181 B CN 102075181B CN 2009102331313 A CN2009102331313 A CN 2009102331313A CN 200910233131 A CN200910233131 A CN 200910233131A CN 102075181 B CN102075181 B CN 102075181B
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Abstract
The invention discloses a frequency-locked loop comprising a digital loop filter, a data collection unit, a comparison unit, an aging correction word generation unit and a correcting unit. The data collection unit collects digital data output by the digital loop filter, carries out the weight processing on the digital data to obtain a weight value, and provides the weight value as a current weight value to the comparison unit; and the comparison unit compares the current weight value with a standard weight value and provides a comparison result to the aging correction word generation unit which regulates a current aging correction word according to the comparison result to generate the latest aging correction word. When an aging frequency drift occurs in a crystal oscillator, the influence to the output frequency can be eliminated or decreased through the drift compensation of an aging compensation feedback loop.
Description
[technical field]
The present invention relates to electronic circuit design field, particularly the compensation technique of frequency synthesizer and FLL.
[background technology]
The frequency of crystal oscillator output all can be drifted about along with variation of temperature; The various frequencies that generate based on the frequency of crystal oscillator output so all can be drifted about thereupon; In order to solve this technical problem, application number is 200810037670.5, and open day is on September 24th, 2008; Publication number is the frequency synthesizer that the one Chinese patent application of CN101272142A discloses a kind of temperature frequency compensation, and Fig. 1 shows the block diagram of the said frequency synthesizer in this patent application.
As shown in Figure 1, said frequency synthesizer 100 comprises oscillating circuit 101, FLL 107, frequency correction unit 109, digital temperature sensor 103, decode logic unit 105, frequency correction look-up table 111 and interpolation logical block 115.Said oscillating circuit 101 generates reference frequency signal f by crystal oscillator 117
RSaid FLL 107 is based on said reference frequency signal f
RGenerate the desired output frequency f with frequency correction control word FCW_new
OUTSaid frequency correction unit 109 is according to temperature and frequency correcting word FCW
TmpCompensation automatic frequency control word FCW
AFCTo obtain frequency correction control word FCW_new, wherein: FCW_new=FCW
AFC+ FCW
TmpSaid automatic frequency control word FCW
AFCComprise fixed frequency control word FCW and automatic frequency correction word AFC, said automatic frequency control word FCW
AFCCan be expressed as following formula: FCW
AFC=FCW+AFC.
Confirm the temperature and frequency correcting value that each discrete temperature spot is corresponding according to the temperature frequency indicatrix of crystal oscillator 117 in advance; And with these storage in frequency correction look-up table 111, the current temperature value of sensing according to digital temperature sensor 103 afterwards finds suitable temperature and frequency correcting word FCW at frequency correction look-up table 111
Tmp, afterwards by 115 couples of said suitable temperature and frequency correcting word FCW of interpolation logical block
TmpCarry out interpolation processing to obtain the corresponding temperature and frequency correcting word FCW of current temperature value
Tmp, utilize temperature and frequency correcting word FCW subsequently
TmpTo automatic frequency control word FCW
AFCCarry out the temperature frequency drift compensation to obtain the frequency correction control signal FCW_new behind the temperature and frequency correcting.Like this, just realized compensation to the temperature frequency drift of crystal oscillator.
200810037670.5 the temperature and frequency correcting in number patent application belongs to frequency precorrection, promptly owing to can record the temperature frequency drift curve of crystal oscillator, therefore can pre-configured temperature and frequency correcting word to temperature frequency drift proofread and correct.Yet; Crystal oscillator also can produce frequency drift along with wearing out; Such as using the initial stage at an electronic equipment; The frequency of crystal oscillator output in it can be very accurate after through the said temperature frequency correction, after this electronic equipment has used 1 or 2 year, though the frequency of the output of the crystal oscillator in it is through temperature and frequency correcting but still can drift about.
At present, for crystal oscillator produce frequency drift owing to aging, also do not have very effective, suitable solution.
[summary of the invention]
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit avoiding the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used to limit scope of the present invention.
One of technical problem that the present invention will solve is to provide a kind of FLL, and it can compensate the aging frequency drift that produces owing to crystal oscillator.
One of technical problem that the present invention will solve is to provide a kind of frequency synthesizer, and it can compensate the aging frequency drift that produces owing to crystal oscillator.
In order to address the above problem, according to an aspect of the present invention, the invention provides a kind of FLL, it comprises digital loop filters, data acquisition unit, comparing unit, aging correct word generation unit and correcting unit.Said data acquisition unit is gathered the numerical data of said digital loop filters output; And said numerical data is carried out weight handle to obtain weight numerical value; And said weight numerical value offered said comparing unit as current weight numerical value; More current weight numerical value of said comparing unit and standard weight numerical value; And comparative result offered said aging correct word generation unit, and said aging correct word generation unit is adjusted to generate up-to-date aging correct word current aging correct word according to comparative result, and said correcting unit utilizes said up-to-date aging correct word that said frequency control word is proofreaied and correct.
Further; After said output frequency locking; Data acquisition unit is gathered the numerical data of digital loop filters output; And said numerical data is carried out weight handle and to obtain an initial weight numerical value, and this initial weight numerical value is offered said comparing unit as standard weight numerical value.
Further, be the initial aging correct word that aging correct word generation unit is provided with, when wearing out drift compensation for the first time, current aging correct word is initial aging correct word.
Further, said aging correct word generation unit will constantly be adjusted said current aging correct word, when said current weight numerical value converges on standard weight numerical value till.
Further; The said comparative result of said comparing unit output comprises that current weight numerical value overgauge weight numerical value and current weight numerical value are less than standard weight numerical value; When current weight numerical value overgauge weight numerical value; Said aging correct word generation unit need be turned said aging correct word down, and during less than standard weight numerical value, said aging correct word generation unit need be transferred big said aging correct word at current weight numerical value.
Further, said correcting unit wears out to said frequency control word according to following formula and proofreaies and correct or compensation: FCW
ACW=FCW+ACW, wherein FCW
ACWFrequency control word after expression is proofreaied and correct, FCW representes frequency control word, ACW representes aging control word.
Further; It also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, low pass filter, voltage controlled oscillator and frequency digital quantizer; Wherein said digit phase accumulator; Receive the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct; Said voltage controlled oscillator is based on input voltage generated frequency signal, and said frequency digital quantizer provides the numerical frequency data flow of the frequency values of the expression frequency signal that said voltage controlled oscillator is exported; The numerical frequency comparator, more said numerical frequency data flow and said reference frequency data flow, and output error signal; Said digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering; Said digital analog converter is connected with digital loop filters, and the output that receives digital loop filters is to generate analog signal; Said low pass filter is used for said analog signal is carried out filtering, and filtered analog signal is used to control the input voltage of said voltage controlled oscillator.
Further; It also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, gain controller, digital controlled oscillator and frequency digital quantizer; Wherein said digit phase accumulator; Receive the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct; The frequency signal that said digital controlled oscillator generates, said frequency digital quantizer provide the numerical frequency data flow of the frequency values of the expression frequency signal that said digital controlled oscillator is exported; The numerical frequency comparator, more said numerical frequency data flow and said reference frequency data flow, and output error signal; Said digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering; Said gain controller is connected with digital loop filters, and the output that receives digital loop filters is used to control the digital controlled signal of said digital controlled oscillator with generation.
According to an aspect of the present invention, the invention provides a kind of frequency synthesizer, it comprises: oscillating circuit is used for generating reference frequency signal based on crystal oscillator; With aforesaid FLL.
Compared with prior art; When the present invention aging frequency drift occurred at crystal oscillator; Can the aging frequency drift that causes owing to crystal oscillator be compensated through the compensation of ageing feedback loop, thereby can eliminate or reduce influence output frequency.
About other purposes of the present invention, characteristic and advantage will combine accompanying drawing in embodiment, to describe in detail below.
[description of drawings]
In conjunction with reference to accompanying drawing and ensuing detailed description, the present invention will be more readily understood, the structure member that wherein same Reference numeral is corresponding same, wherein:
Fig. 1 shows the block diagram of a kind of frequency synthesizer of the prior art;
Fig. 2 shows the block diagram of an embodiment of the frequency synthesizer among the present invention;
Fig. 3 shows the block diagram of an embodiment of the FLL among the present invention;
Fig. 4 shows the block diagram of another embodiment of the FLL among the present invention;
Fig. 5 shows the block diagram of another embodiment of the FLL among the present invention; With
Fig. 6 shows the block diagram of the another one embodiment of the FLL among the present invention.
[embodiment]
Detailed description of the present invention is mainly come the running of direct or indirect simulation technical scheme of the present invention through program, step, logical block, process or other symbolistic descriptions.Be the thorough the present invention that understands, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the present invention then possibly still can realize.Affiliated those of skill in the art use these descriptions here and state that the others skilled in the art in affiliated field effectively introduce their work essence.In other words, be the object of the invention of avoiding confusion, owing to method, program, composition and the circuit known are readily appreciated that, so they are not described in detail.
Alleged here " embodiment " or " embodiment " are meant special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different in this manual local " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or optionally mutually exclusive with other embodiment embodiment.In addition, represent that the sequence of modules and revocable in method, flow chart or the functional block diagram of one or more embodiment refers to any particular order, also be not construed as limiting the invention.
Fig. 2 shows the block diagram of an embodiment of the frequency synthesizer 200 among the present invention.Said frequency synthesizer 200 comprises oscillating circuit 201 and FLL 203, and said oscillating circuit 201 generates reference frequency signal f by crystal oscillator 301
R, said FLL 203 is based on reference frequency signal f
RAnd the output frequency f that generation is expected according to frequency control word (Frequency Control word is called for short FCW)
OUTThrough defining suitable frequency control word, the output frequency that the user can obtain expecting.Said frequency control word can be represented with binary sequence; Binary sequence such as 32,16 or 8; It can be through the frequency control word behind the temperature and frequency correcting, also can be the frequency control word without temperature and frequency correcting, can also be the frequency control word through other processing.Said FLL 203 can detect output frequency f
OUTOwing to the aging frequency drifts that cause of crystal oscillator 301, and according to said frequency drift frequency control word wear out and proofreaies and correct or compensation, utilize the frequency control word after the aging correction to carry out frequency locking subsequently.
Fig. 3 shows the block diagram of an embodiment of the FLL 300 among the present invention, and said FLL 300 can be as the FLL 203 among Fig. 2.Said FLL 300 can come locking frequency according to the desired output frequency of frequency control word FCW definition; The feedback loop that it comprises phase accumulator 320, numerical frequency comparator 321, digital loop filters 323, D/A (digital-to-analog) transducer 325, low pass filter 327, voltage controlled oscillator (voltage-controlled oscillator is called for short VCO) 329 and comprises frequency divider 333 and frequency digital quantizer 331.
Different at the phase-locked loop of phase region with conventional operation, said FLL 300 is operated in frequency domain, and an advantage of said FLL 300 is that said frequency comparator 321 has high linearity and can be designed as digital logic circuit.Said traditional phase-locked loop realizes with analog circuit usually, its design cost is increased and is difficult to realize free integrated with digital circuit.In addition, said analog phase-locked look is also very sensitive to the variation of technology, voltage and environment.For FLL, can produce any desired output frequency through setting the FCW value, the precision of frequency is by word length and the reference frequency f of FCW
RDecision.For instance, reference frequency f
RBe 50MHz, the word length of FCW is 32, and the precision of frequency can reach 50MHz/2 so
32=0.01Hz.
Through the numerical frequency comparator 321 and digital loop filters 323 that use high linearity, FLL 300 can obtain low noise and high-precision signal.The frequency divider 333 that is used in the feedback path can be with the frequency signal f of voltage controlled oscillator 329 generations
VCOFrequency division is to intermediate-freuqncy signal f
IF, f wherein
IF=f
VCO/ div_n, div_n are the Frequency Dividing Factors of frequency divider 133.Said frequency digital quantizer 331 provides its input signal of expression f
IFThe numerical frequency data flow Pvco of frequency values.The effect of said frequency digital quantizer 331 is to utilize reference frequency f
RTo input signal f
IFClock cycle (such as rising edge or trailing edge) count, the predetermined clock number is standardized as numerical frequency data flow Pvco, said numerical frequency data flow Pvco will be as an input of numerical frequency comparator 321.Said phase accumulator 320 is with reference frequency f
RGenerate the reference frequency data flow Posc of expression incoming frequency control word FCW setpoint frequency value for the basis.
Behind loop-locking, numerical frequency data flow Pvco should be identical with reference frequency data flow Posc.Said numerical frequency comparator 321 produces an error signal through comparative figures frequency data stream Pvco and reference frequency data flow Posc.Subsequently, 323 pairs of said error signals of said digital loop filters are carried out digital filtering.Said digital loop filters 323 provides the control of loop bandwidth and lock adjustment time.Through using said digital loop filters 323, can be according to needs (such as phase noise and adjusting time) the active control loop bandwidth and the lock adjustment time of FLL.The output of said digital loop filters 323 is input to digital analog converter 325 to generate an analog signal.The analog output signal of said digital analog converter 325 is used to control the input voltage of voltage controlled oscillator 329 behind the process further LPF of said low pass filter 327.Behind loop-locking, the output of voltage controlled oscillator 329 is locked to the expected frequency that frequency control word FCW sets.
Yet the aging meeting of crystal oscillator 301 causes reference frequency f
RDrift; Thereby can cause the variation of numerical frequency data flow Pvco and reference frequency data flow Posc; Though loop still can lock at last; And numerical frequency data flow Pvco is still identical with reference frequency data flow Posc in the locking back, but drift has taken place the output frequency of voltage controlled oscillator 329 at this moment, and this drift can't be regulated or proofread and correct through above-mentioned loop.In order to proofread and correct or compensate the aging drift that causes owing to crystal oscillator 301; Said FLL 300 also disposes data acquisition unit 335, comparing unit 337, aging correct word (aging correction word; Be called for short ACW) generation unit 339 and correcting unit 341, these unit can be referred to as the compensation of ageing feedback loop.
Because just be used as the aanalogvoltage of importing voltage controlled oscillator 329 behind the numerical data process digital analog converter 325 of digital loop filters 323 outputs and the low pass filter 327, and at output frequency f
OUTAfter the locking, what said aanalogvoltage should be able to the long period converges near the fixed value, so corresponding, and the numerical data of digital loop filters 323 outputs should also restrain in a long time.Therefore; Said data acquisition unit 335 is provided to gather the numerical data of digital loop filters 323 outputs; And said numerical data is carried out weight handle and to obtain a weight numerical value; Wherein said weight numerical value is directly corresponding with the aanalogvoltage of input voltage controlled oscillator 329 on physical meaning, that is to say that said weight numerical value can directly reflect the value of the aanalogvoltage of importing voltage controlled oscillator 329.Further, said weight numerical value just can directly reflect the value of the output frequency of voltage controlled oscillator 329, in other words, if the output frequency of voltage controlled oscillator 329 has produced drift, will cause said weight numerical value that drift or variation take place so.
Before said frequency synthesizer or the application of said FLL input or before putting goods on the market, can carry out initialization to each unit in the compensation of ageing feedback loop.In one embodiment, at said output frequency f
OUTAfter the locking; The numerical data of digital loop filters 323 outputs is gathered in data sampling unit 335; And said numerical data is carried out weight handle and to obtain an initial weight numerical value, and this initial weight numerical value is offered said comparing unit 337 as standard weight numerical value.In addition, the initial aging correct word in the aging correct word generation unit 339 can also be set, be 0 such as said initial aging correct word is set.
Through after the initialization, can be provided with whenever and carry out once aging drift compensation or correction at a distance from the scheduled time, also wear out in real time drift compensation or correction can be set.At drift compensation or the timing of wearing out; Said data acquisition unit 335 is gathered the numerical data of digital loop filters 323 outputs; And said numerical data is carried out weight handle obtaining a weight numerical value, and said weight numerical value is offered comparing unit 337 as current weight numerical value.Said comparing unit 337 more current weight numerical value and standard weight numerical value; And comparative result offered said ACW generation unit 339; Said ACW generation unit 339 is adjusted to generate up-to-date ACW current ACW according to comparative result, and said correcting unit 341 utilizes up-to-date ACW that said FCW is proofreaied and correct or compensates.
Subsequently; Said data acquisition unit 335 continues to gather the numerical data of digital loop filters 323 outputs; And continue that said numerical data is carried out weight and handle obtaining another weight numerical value, and said another weight numerical value is offered comparing unit 337 as current weight numerical value.Said comparing unit 337 continues more current weight numerical value and standard weight numerical value; And will and comparative result be offered said ACW generation unit 339 once more; Said ACW generation unit 339 is adjusted to generate up-to-date ACW current ACW according to comparative result once more, and said correcting unit 341 utilizes up-to-date ACW that said FCW is proofreaied and correct or compensates.Constantly repeat aforesaid operations, when said current weight numerical value converges on standard weight numerical value till.
After aging drift compensation finished, said data acquisition unit 335 just can quit work with comparing unit 337, and the ACW that said correcting unit 341 then can provide according to ACW generation unit 339 always proofreaies and correct or compensates said frequency control word.Frequency control word after aging correction or the compensation gets into said phase accumulator 320, and said phase accumulator 320 is with reference frequency f
RReference frequency data flow Posc for the frequency control word setpoint frequency value after the aging correction of basis generation expression input.It should be noted that comparative result between current weight numerical value and the standard weight numerical value can reflect the trend of frequency drift, therefore 339 of said ACW generation units need the said ACW of adjustment so that the FCW after the compensation is just passable to opposite trend adjustment.If carry out for the first time the ACW adjustment, so said current ACW value is exactly initial ACW, such as being 0.
In one embodiment; The scheduled duration that said data acquisition unit 335 is gathered digital loop filters 323 outputs is (such as 3 seconds; Time, long-acting more fruit was good more) or predetermined figure (1M position; The long-acting more fruit of figure place is good more) numerical data, and said numerical data is carried out weight handles and to obtain a weight numerical value.When concrete the realization, said data acquisition unit 335 can be gathered the numerical data of a period of time, and obtains a weight numerical value; Data acquisition unit 335 can then be gathered the numerical data of a period of time more afterwards, and obtains another weight numerical value, judges that afterwards two adjacent weighted values get difference whether in allowed band; If, explain that then weight numerical value is stable, the weight numerical value after will stablizing subsequently offers said comparing unit 337; Otherwise; Explain that then weight numerical value is still unstable, obtain next weight numerical value, and continue to judge whether this weight numerical value is stable with continued.Handle in the example weight, can said numerical data be added up, its with can be used as weight numerical value, be exactly 7 such as the weight numerical value of one 10 binary sequences 1100111101.Handling in example in another weight, can said numerical data be added up, will average afterwards, is exactly 7/10=0.7 such as still 10 the weight numerical value of binary sequence 1100111101.Handle in the example in other weight, can also adopt some complicated smoothing processing algorithms.
In one embodiment, the said comparative result of said comparing unit 337 outputs comprises that current weight numerical value overgauge weight numerical value, current weight numerical value are locked in standard weight numerical value less than standard weight numerical value, current weight numerical value.When current weight numerical value overgauge weight numerical value; Said ACW generation unit 339 need be turned said aging correct word ACW down; At current weight numerical value during less than standard weight numerical value; Said ACW generation unit 339 needs to transfer big said aging correct word ACW, is locked in standard weight numerical value at said current weight numerical value, and said ACW generation unit 339 keeps said aging correct word ACW constant.
In one embodiment, can confirm as required that said step-length has directly determined aging frequency compensated speed to the amplitude (being step-length) of each adjustment of ACW.As a rule, the frequency drift of crystal oscillator is generally all very little, and such as several hertz, therefore, said step-length also can be smaller.In another embodiment, said ACW generation unit 339 can be selected the adjustment step-length according to the difference between current weight numerical value and the initial weight numerical value, and according to said step-length said ACW is adjusted, and can accelerate regulating the speed of ACW like this.
In one embodiment, said correcting unit 341 wears out to FCW according to following formula and proofreaies and correct or compensation: FCW
ACW=FCW+ACW, the FCW after the correction
ACWGetting into phase accumulator 420 handles.
Advantage, characteristics or a benefit of the present invention are: when aging frequency drift has appearred in crystal oscillator, through the drift compensation of compensation of ageing feedback loop, make output frequency not be affected, and still can be locked on the assigned frequency exactly.In addition,, be easy to realize, and be convenient to integratedly that and the compensation precision of frequency drift is also very high because the compensation of ageing feedback loop all is digital circuit, in theory can be identical with the FREQUENCY CONTROL precision of FCW, can reach 1Hz or above control precision easily.Theoretically, adopt analog circuit also can realize the compensation of aging frequency drift,, expect reaching the precision of 1Hz so, then must can detect 1/10M=10 such as the voltage controlled oscillator (1 volt of the every change of voltage, frequency variation 10MHz) that adopts 10Mhz/V
-7The change in voltage of volt, and this is to be difficult to realize in the analog circuit field.
Fig. 4 shows the block diagram of another embodiment of the FLL 400 among the present invention, and said FLL 400 can be as the FLL 203 among Fig. 2.FLL 400 shown in Fig. 4 includes phase accumulator 420, numerical frequency comparator 421, digital loop filters 423, D/A converter 425, low pass filter 427, voltage controlled oscillator 429, frequency divider 433, frequency digital quantizer 431, data acquisition unit 435, comparing unit 437, ACW generation unit 439 and correcting unit 441.Can find out; FLL 400 among Fig. 4 is identical with FLL 300 structure major parts among Fig. 3; Both are difference: replaced frequency digital quantizer 331 with direct frequency digital quantizer 431 in the FLL 400 in Fig. 4, and the frequency signal f of voltage controlled oscillator 429 outputs
VCODirectly offer said direct frequency digital quantizer 431, the frequency signal f of 433 pairs of voltage controlled oscillators of frequency divider, 429 outputs
VCOCarry out frequency division and obtain output frequency f
OUT
It is numerical frequency data flow Pvco that said direct frequency digital quantizer 431 is used for direct output conversion of signals with voltage controlled oscillator 429.For said direct frequency digital quantizer 431, said frequency sampling is (such as VCO output f through high frequency output signal
VCO) the known frequency reference frequency f of sampling
RRealize.One of advantage of this framework is owing to the VCO output Pvco with high frequency comes the frequency reference frequency f
RSample, thereby improved the precision of frequency digital quantizer 431.Usually the precision of frequency digital quantizer is and uses sample frequency proportional.Sample frequency is high more, and the result is accurate more, and noise is low more.In addition, this framework has been simplified the design of the frequency divider in the feedback path and has been reduced hardware cost and related power consumption.For different output frequencies, frequency divider 433 can be used to the output f of frequency division voltage controlled oscillator
VCONeeding to obtain output frequency.
Fig. 5 shows the block diagram of another embodiment of the FLL 500 among the present invention, and said FLL 500 can be as the FLL 203 among Fig. 2.FLL 500 shown in Fig. 5 includes phase accumulator 501, numerical frequency comparator 503, digital loop filters 505, gain control unit 507, digital controlled oscillator (digitally controlled oscillator is called for short DCO) 509, frequency divider 511, frequency digital quantizer 513, data acquisition unit 535, comparing unit 537, ACW generation unit 539 and correcting unit 541.Can find out; FLL 500 among Fig. 5 is identical with FLL 300 structure major parts among Fig. 3, and both are difference: FLL among Fig. 5 500 usefulness gain control units 507, digital controlled oscillator 509 have replaced low pass filter 327, voltage controlled oscillator 329 in the FLL 300 among Fig. 3 respectively.
Said digital controlled oscillator is to design completion through the voltage-operated variable capacitor that uses the numerical control capacitor array to substitute in traditional voltage controlled oscillator.Weighting switch binary system electric capacity (such as variable capacitor) array can advance the stages of digital control signal through two and switch to high capacitance pattern or low capacitive.Numerical control position through using the delta-sigma modulation just can obtain high-resolution capacitance.As shown in Figure 5, the corresponding module among the frequency divider 511 in phase accumulator 501, numerical frequency comparator 503, digital loop filters 505, the feedback path and frequency digital quantizer 513 and Fig. 3 has identical functions.
The output of said digital loop filters 505 is connected to the input of gain control unit 507, and said gain control unit 507 can generate the digital controlled signal of the weighting switch binary system capacitor array that is used to control digital controlled oscillator.Said gain control unit 507 is used for the gain of normalization digital controlled oscillator and eliminates the influence to digital controlled oscillator phase place and frequency from technology, voltage and temperature.The frequency signal f that said digital controlled oscillator 609 generates according to the digital signal from gain control unit 507
DCOBehind loop-locking, through using numerical frequency comparator 503, numerical frequency data flow Pvco is locked to reference frequency data flow Posc.Like this, the output of digital controlled oscillator 509 is locked to the expected frequency that frequency control word FCW sets.
As shown in Figure 5, thus can remove digital analog converter and low pass filter among Fig. 3 through utilizing digital controlled oscillator to substitute voltage controlled oscillator, and whole like this FLL 500 can be realized through digital logical course.Like this, frequency signal will be not easy to receive the influence of noise and other environment.This framework especially is fit to low pressure, deep-submicron COMS technology; Because the traditional analog oscillator the range of linearity owing to low-voltage becomes very little; And has higher gain; This makes analog vco very easily receive the influence of noise and operating point drift, still, adopts digital vco just will be not easy to receive the influence of low-voltage and other factor of environmental.
Same; Data acquisition unit 535 in Fig. 5, comparing unit 537, ACW generation unit 539 and correcting unit 541 can be formed the compensation of ageing feedback loop equally; Also can be the same as Fig. 3, to frequency drift that cause well compensates or proofreaies and correct by the aging of crystal oscillator.
Fig. 6 shows the block diagram of the another one embodiment of the FLL 600 among the present invention, and said FLL 600 can be as the FLL 203 among Fig. 2.FLL 600 shown in Fig. 6 includes phase accumulator 601, numerical frequency comparator 603, digital loop filters 605, gain control unit 607, digital controlled oscillator 609, frequency divider 611, direct frequency digital quantizer 613, data acquisition unit 635, comparing unit 637, ACW generation unit 639 and correcting unit 641.Can find out; FLL 600 among Fig. 6 is identical with FLL 500 structure major parts among Fig. 5; Both are difference: replaced the frequency digital quantizer 513 among Fig. 5 with direct frequency digital quantizer 613 in the FLL 600 in Fig. 6, and the frequency signal f of digital controlled oscillator 509 outputs
DCODirectly offer said direct frequency digital quantizer 613, the frequency signal f of 611 pairs of digital controlled oscillators of frequency divider, 609 outputs
DCOCarry out frequency division and obtain output frequency f
OUT
Same; Data acquisition unit 635 in Fig. 6, comparing unit 637, ACW generation unit 639 and correcting unit 641 can be formed the compensation of ageing feedback loop equally; Also can be the same as Fig. 3, to frequency drift that cause well compensates or proofreaies and correct by the aging of crystal oscillator.
In one embodiment, also can not use frequency divider that the output signal of said digital controlled oscillator or voltage controlled oscillator is carried out frequency division, and the output signal of directly using said digital controlled oscillator or voltage controlled oscillator is as the desired output frequency.Said frequency digital quantizer in different embodiment and said direct frequency digital quantizer are realizing that on the principle be duplicate, and they can be called frequency number word transducer.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a FLL is characterized in that, it comprises digital loop filters, data acquisition unit, comparing unit, aging correct word generation unit and correcting unit,
Said data acquisition unit is gathered the numerical data of said digital loop filters output; And said numerical data is carried out weight handle to obtain weight numerical value; And said weight numerical value offered said comparing unit as current weight numerical value; More current weight numerical value of said comparing unit and standard weight numerical value, and comparative result offered said aging correct word generation unit, said aging correct word generation unit is adjusted to generate up-to-date aging correct word current aging correct word according to comparative result; Said correcting unit utilizes said up-to-date aging correct word that frequency control word is proofreaied and correct
Wherein said data acquisition unit is gathered the numerical data of digital loop filters output, and said numerical data is carried out weight handle and obtain an initial weight numerical value, and this initial weight numerical value is offered said comparing unit as standard weight numerical value,
Wherein said aging correct word generation unit will constantly be adjusted said current aging correct word, when said current weight numerical value converges on standard weight numerical value till.
2. FLL as claimed in claim 1 is characterized in that, for aging correct word generation unit is provided with initial aging correct word, when wearing out drift compensation for the first time, current aging correct word is initial aging correct word.
3. FLL as claimed in claim 1; It is characterized in that; The said comparative result of said comparing unit output comprises current weight numerical value overgauge weight numerical value and current weight numerical value less than standard weight numerical value, and when current weight numerical value overgauge weight numerical value, said aging correct word generation unit need be turned said aging correct word down; During less than standard weight numerical value, said aging correct word generation unit need be transferred big said aging correct word at current weight numerical value.
4. FLL as claimed in claim 1 is characterized in that, said correcting unit according to following formula to said frequency control word correction: the FCW that wears out
ACW=FCW+ACW,
FCW wherein
ACWFrequency control word after expression is proofreaied and correct, FCW representes frequency control word, ACW representes aging correct word.
5. like each described FLL of claim 1-4, it is characterized in that it also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, low pass filter, voltage controlled oscillator and frequency digital quantizer, wherein
Said digit phase accumulator receives the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct;
Said voltage controlled oscillator is based on input voltage generated frequency signal, and said frequency digital quantizer provides the numerical frequency data flow of the frequency values of the expression frequency signal that said voltage controlled oscillator is exported;
The numerical frequency comparator, more said numerical frequency data flow and said reference frequency data flow, and output error signal;
Said digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering;
Said digital analog converter is connected with digital loop filters, and the output that receives digital loop filters is to generate analog signal;
Said low pass filter is used for said analog signal is carried out filtering, and filtered analog signal is used to control the input voltage of said voltage controlled oscillator.
6. like each described FLL of claim 1-4, it is characterized in that it also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, gain controller, digital controlled oscillator and frequency digital quantizer, wherein
Said digit phase accumulator receives the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct;
The frequency signal that said digital controlled oscillator generates, said frequency digital quantizer provide the numerical frequency data flow of the frequency values of the expression frequency signal that said digital controlled oscillator is exported;
The numerical frequency comparator, more said numerical frequency data flow and said reference frequency data flow, and output error signal;
Said digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering;
Said gain controller is connected with digital loop filters, and the output that receives digital loop filters is used to control the digital controlled signal of said digital controlled oscillator with generation.
7. frequency synthesizer is characterized in that it comprises:
Oscillating circuit is used for generating reference frequency signal based on crystal oscillator; With
Like each described FLL of claim 1-4.
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| US9106211B2 (en) * | 2013-03-13 | 2015-08-11 | Infineon Technologies Austria Ag | System and method for an oversampled data converter |
| US9325324B1 (en) * | 2014-12-17 | 2016-04-26 | Stmicroelectronics International N.V. | Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature |
| KR102375949B1 (en) * | 2015-01-02 | 2022-03-17 | 삼성전자주식회사 | Apparatus and method for controlling output of frequency synthesizer |
| CN106330145A (en) * | 2015-06-26 | 2017-01-11 | 深圳市中兴微电子技术有限公司 | Crystal oscillator circuit and control method of output signal amplitude |
| CN110175401B (en) * | 2019-05-27 | 2022-12-13 | 河北交通职业技术学院 | Source-end decoupling normalized frequency-locked loop modeling method |
| CN110645975A (en) * | 2019-10-16 | 2020-01-03 | 北京华捷艾米科技有限公司 | Monocular vision positioning IMU (inertial measurement unit) auxiliary tracking method and device |
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| CN1535501A (en) * | 2001-05-16 | 2004-10-06 | Reference oscillator with automatic compensation for aging and temp | |
| CN101026377A (en) * | 2006-02-20 | 2007-08-29 | 日本电气株式会社 | Clock generation circuit |
| CN201550097U (en) * | 2009-11-24 | 2010-08-11 | 无锡爱睿芯电子有限公司 | Frequency-locked loop |
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| CN1535501A (en) * | 2001-05-16 | 2004-10-06 | Reference oscillator with automatic compensation for aging and temp | |
| CN101026377A (en) * | 2006-02-20 | 2007-08-29 | 日本电气株式会社 | Clock generation circuit |
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