CN102055487A - Subblock interleaver and interleaving method for convolutional turbo encoding - Google Patents
Subblock interleaver and interleaving method for convolutional turbo encoding Download PDFInfo
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- CN102055487A CN102055487A CN200910207649XA CN200910207649A CN102055487A CN 102055487 A CN102055487 A CN 102055487A CN 200910207649X A CN200910207649X A CN 200910207649XA CN 200910207649 A CN200910207649 A CN 200910207649A CN 102055487 A CN102055487 A CN 102055487A
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Abstract
The invention discloses a subblock interleaver and an interleaving method for convolutional turbo encoding. The interleaver comprises a bit slicer, a subblock interleaver and a bit burster, wherein the bit slicer partitions a bit sequence into a plurality of subblocks which comprise two information bit sequence subblocks and at least one group of verification bit sequence subblocks; the subblock interleaver exchanges the positions of any two verification bit sequence subblocks in one of the at least one group of verification bit sequence subblocks, interleaves each subblock and inverses the order(s) of one or more of the interleaved subblocks; and the bit burster groups bit sequences produced after interleaving.
Description
Technical field
The present invention relates to a kind of convolution turbo code coder that is used for, more specifically, relate to a kind of sub-block interleaver and deinterleaving method thereof that is used for convolution turbo sign indicating number coding.
Background technology
Mobile global microwave access intercommunication (Wi MAX) is that a kind of employing wireless mode replaces wired mode to realize " last km " broadband access technology.It has merged and has moved and fixed broadband network, by adopting the network configuration of wireless access wide band technology and flexibility and changeability on a large scale, provides the mobile broadband of convenient high speed to connect.Wi MAX technology is based on the IEEE802.16 series standard at microwave and millimeter wave frequency band proposition, it is the mobile Wi MAX standard of fixedly releasing after the Wi MAX standard continue 802.16d, its target is on the basis of fixed wireless access research on standard, supports the mobility of broadband access.Convolution turbo sign indicating number (CTC) is the Turbo code that a class is used some convolution schemes, because its high-performance error correction characteristic, is included into 802.16 and the DVB-RCS standard.
Fig. 1 is the structure chart of CTC encoder.As shown in Figure 1, the CTC encoder comprises: the CTC encoder 101 of 1/3 ratio, interleaver 102, card punch (perhaps being the bit selector) 103.Bit information of exporting after the process 1/3CTC encoder encodes and check bit number are 3 times of information bit, interleaver carries out interleaving treatment to the back data of encoding, card punch (perhaps bit selector) punches to the data after interweaving according to required transmission rate then, thereby finishes cataloged procedure.
Convolution turbo sign indicating number adopts duobinary system circulation recursive systematic convolutional code (due binary CircularRecursive Systematic Convolutional code) to become demal (constituent code) as it.The detailed structure of composition encoder 104 has been shown among Fig. 1, wherein, the information bit of A and B representative input, here, need carry out coding twice to information bit A and B: at first directly information bit A, B are carried out duobinary system circulation recursive system convolutional encoding, obtained verification sequence Y
1, W
1, information bit carries out the composition coding second time through CTC interleaver 105 then, obtains verification sequence Y
2And W
2Each encoding block of input coding device has comprised k information bit, and perhaps N is to information bit, i.e. k=2 * N, and wherein k must be 8 multiple, and N must be 4 multiple, and to satisfy 32≤N≤4096.
Also show the concrete structure of interleaver 106 among Fig. 1, comprising: bit dispenser, sub-block interleaver (subblock interleaving) and bit groupings device (bit grouping).The bit that will produce after the bit dispenser will be encoded is assigned on six sub-pieces, here, establishes six sub-pieces and is followed successively by A, B, Y
1, Y
2, W
1And W
2, the described information bit A of the content of sub-piece and the preceding paragraph, B and check bit Y
1, Y
2, W
1And W
2Corresponding.Sub-block interleaver interweaves described six sub-pieces respectively in each sub-piece, the interleaved order that each sub-piece adopted is identical.If A, B, Y
1, Y
2, W
1And W
2, after six pieces passed through sub-block interleaving respectively, the bit sequence that obtains was designated as A ', B ', Y ' 1, Y '
2, W '
1And W '
2, wherein, A ', B ', Y '
1, Y '
2, W '
1, W '
2=A '
0, A '
1..., A '
N-1, B '
0, B '
1..., B '
N-1, Y '
1,0, Y '
1,1..., Y '
1, N-1, Y '
2,0, Y '
2,1..., Y '
2, N-1, W '
1,0, W '
1,1..., W '
1, N-1, W '
2,0, W '
2,1..., W '
2, N-1Then, the bit groupings device is with the bit sequence grouping that obtains.
Fig. 2 illustrates the block diagram of sub-block interleaver.As shown in Figure 2, the output of each sub-block interleaver is pooled on the string sequence, and symbol packets is with Y
1And Y
2Two alternately outputs of sub-piece are simultaneously also with W
1And W
2Two alternately outputs of sub-piece.Then symbol grouping back output sequence is A '
0, A '
1..., A '
N-1, B '
0, B '
1..., B '
N-1, Y '
1,0, Y '
1,1..., Y '
1, N-1, Y '
2,0, Y '
2,1..., Y '
2, N-1, W '
1,0, W '
2,0, W '
1,1, W '
2,1, W '
2,2, W '
2,2..., W '
1, N-1, W '
2, N-1
In mobile communication system,, adopt the scheme of M rank quadrature amplitude modulation (M-QAM) usually in order not increase bandwidth, to improve message transmission rate.But high order modulation itself is a kind of unequal error protection modulation, and for M＞4, bit error rate (BER) performance that is mapped to each bit on the M-QAM symbol is different.It is less to be in the some energy that encloses in the planisphere, is declined easily, and the bit reliability that constitutes these symbols is relatively poor, and it is better to constitute the bit reliability of peripheral point by contrast.Fig. 3 illustrates the planisphere of 16QAM scheme, and wherein, the mapping of bit is i in proper order
1i
2q
1q
2, i
1Got the 0 and 1 respectively corresponding constellation point of right half-sum left side half-plane, i
2Got 0 and 1 respectively corresponding in the middle of and the constellation point of both sides.I like this
1The average distance of getting 1 constellation point and getting between 0 constellation point is greater than i
2Get 1 constellation point and get average distance between 0 constellation point, at receiving terminal i
1Reliability greater than i
2
Fig. 4 shows the realization block diagram of composition encoder duobinary system circulation recursive systematic convolutional code in the 1/3 convolution turbo sign indicating number.When carrying out convolution turbo coding, input bit A
i401 and B
iThe 402nd, one group of input of 1/3CTC encoder, check bit Y
iAnd W
iReflection information bit A
iWith bit B
iThe information of associating, in this class doubinary encoding, information bit A
iWith information bit B
iBe to be counted as an integral body, treat as a group unit.In traditional convolution turbo sign indicating number design, if bit A
iBe mapped to the bit of high reliability, then bit B
iAlso be mapped to the bit of high reliability.If bit A
iBe mapped to the bit of low reliability, then bit B
iAlso be mapped to the bit of low reliability.Therefore, if from (A
i, B
i) angle of the group unit that constitutes, the bit reliability of then different group unit is uneven, the group unit reliability height that has, and the reliability that has is low.
In traditional convolution turbo sign indicating number design, do not consider the performance of bit reliability in the high order modulation.Here, reliability refers to that to contain a certain mapped bits in modulation constellation be 0 constellation point and to contain this mapped bits be average distance between 1 the constellation point, and the reliability of this mapped bits is high more if this distance is big more.Consider because traditional convolution turbo sign indicating number will not encoded and modulation is joined together, therefore influenced the bit error code performance of system.The present invention combines convolution turbo sign indicating number and modulation, has proposed a kind of new sub-block interleaver, and this sub-block interleaver can utilize the bit after interleaver will be encoded reasonably to be mapped on the modulation constellation points, thereby improves the bit error rate of system.
Summary of the invention
The invention provides a kind of interleaver that is used for convolution turbo sign indicating number coding, described interleaver comprises: the bit dispenser, the input bit sequence is divided into a plurality of sub-pieces, and described a plurality of sub-pieces comprise 2 sub-pieces of information bit sequence and at least one group of sub-piece of check bit sequence; Sub-block interleaver, exchange the position of any two the sub-pieces of check bit sequence in a group in the described at least one group of sub-piece of check bit sequence, respectively each height piece is interweaved, to the one or more mould M inverted orders of carrying out in each the height piece that interweaves, M can get any natural number; The bit groupings device, the bit sequence grouping that the back that will interweave produces.
The invention allows for a kind of deinterleaving method of convolution turbo sign indicating number coding, comprise step: the input bit sequence is divided into a plurality of sub-pieces, and described a plurality of sub-pieces comprise 2 sub-pieces of information bit sequence and at least one group of sub-piece of check bit sequence; Exchange the position of any two the sub-pieces of check bit sequence in a group in the described at least one group of sub-piece of check bit sequence, respectively each height piece is interweaved, to the one or more mould M inverted orders of carrying out in each the height piece that interweaves, wherein, M can get any natural number; The bit sequence grouping that will produce after will interweaving.
Description of drawings
By below in conjunction with the detailed description of accompanying drawing to embodiment, above-mentioned and/or other aspects of the present invention will become clear and be more readily understood, wherein:
Fig. 1 is the structure chart of traditional CTC encoder;
Fig. 2 illustrates the block diagram of the sub-block interleaver in the interleaver of traditional CTC encoder;
Fig. 3 illustrates the planisphere of 16QAM scheme;
Fig. 4 illustrates the realization block diagram of composition encoder duobinary system circulation recursive systematic convolutional code in the 1/3 convolution turbo sign indicating number;
Fig. 5 illustrates the structure according to the sub-block interleaver of the embodiment of the invention;
Fig. 6 is the planisphere that the 16QAM modulation scheme is shown;
Fig. 7 illustrates to use the diagrammatic sketch according to the sub-block interleaver of the embodiment of the invention;
Fig. 8 illustrates to use two diagrammatic sketch according to the sub-block interleaver of the embodiment of the invention;
Fig. 9 illustrates to use three diagrammatic sketch according to the sub-block interleaver of the embodiment of the invention;
Figure 10 illustrates to use four diagrammatic sketch according to the sub-block interleaver of the embodiment of the invention;
Figure 11 illustrates to use five diagrammatic sketch according to the sub-block interleaver of the embodiment of the invention;
Figure 12 illustrates to use six diagrammatic sketch according to the sub-block interleaver of the embodiment of the invention;
Figure 13 is the diagrammatic sketch that illustrates according to the structure of another CTC encoder of the embodiment of the invention;
Figure 14 illustrates the structure according to the sub-block interleaver of the interleaver that is used for the 1/4CTC encoder of the embodiment of the invention;
Figure 15 is the diagrammatic sketch that illustrates according to the structure of another CTC encoder of the embodiment of the invention;
Figure 17-the 19th, the diagrammatic sketch of the structure of the sub-block interleaver of additional embodiments according to the present invention;
Figure 20 and Figure 21 illustrate traditional employing 16e bit groupings scheme and comparison diagram according to the simulation result of bit groupings scheme under the situation of different block sizes of the embodiment of the invention.
Embodiment
Below with reference to accompanying drawings to being described according to embodiments of the invention.Should be understood that embodiment described here only is exemplary, and scope of the present invention is not limited to embodiment described here.
The present invention has proposed a kind of interleaver (m is the natural number greater than 1) of the 1/m of being used for CTC coding on the basis of original CTC encoder.In described interleaver, consider the bit mapping principle in the modulation and observe balanced principle in the decode procedure: promptly, the reliability during decoding during two of each group bit modulation should be balanced; If first bit is in the high location transmission of modulation reliability, then second bit on the same group just should be in the low location transmission of modulation reliability, otherwise, if first bit is in the low location transmission of modulation reliability, then second bit on the same group just should be in modulation reliability high location transmission, guarantee that the mean reliability of two bits of each group is basic identical.Described interleaver comprises: the bit dispenser, the input bit sequence is divided into a plurality of sub-pieces, and comprise 2 sub-pieces of information bit sequence and at least one group of sub-piece of check bit sequence; Sub-block interleaver exchanges the position of any two the sub-pieces of check bit sequence in a group in the described at least one group of sub-piece of check bit sequence, respectively each height piece is interweaved; The bit groupings device, the bit sequence grouping that the back that will interweave produces.The algorithm of sub-block interleaver is as follows:
Make T
kBe the interim dateout address of sub-piece, BRO
m(y) m bit inverted order of expression, y is m the numerical value that bit is represented, for example: BRO
3(6)=3, because 6 binary form is shown 110, and 3 binary representation 011.
If?T
k＜N
AD[i]＝T
k
i++；
k++；
else
k++
end
Wherein, N indicates the size of sub-piece, AD[i] be the data address of sub-block interleaver output.
Sub-block interleaver according to a further aspect in the invention comprises that also the bit sequence to the position that has exchanged the sub-piece of check bit sequence carries out the step that inverted order is handled
Explain structure below with reference to accompanying drawings in detail according to the sub-block interleaver of the embodiment of the invention.
Fig. 5 illustrates the structure of sub-block interleaver according to an embodiment of the invention, is used for the interleaver of 1/3CTC encoder here as example.Shown in 501 among Fig. 5, compare with the sub-block interleaver in the interleaver among Fig. 2, be used for the sub-piece W of check bit among Fig. 5
1 Sub-block interleaver 501 at first exchanged W
1And W
2The output W ' of two sub-pieces
1And W '
2The position.Particularly, make W
1' each bit in the sequence occupied W
1' and W
2' even bit of composite sequence, W
2' each bit in the sequence occupied W
1' and W
2' odd bits of composite sequence.
Then, the bit sequence W ' of 501 pairs of outputs of sub-block interleaver
1Do the inverted order of mould M, wherein, M is relevant with baseband modulation mode and modulation constellation.
Explain operation principle below in conjunction with Fig. 5 and Fig. 6 according to the mould M inverted order of sub-block interleaver of the present invention.Fig. 6 is the planisphere that the 16QAM modulation scheme is shown.In Fig. 6, the corresponding constellation point of 4 bits, 4 bit-order that this point is corresponding are i
1i
2q
1q
2i
1And q
1Reliability identical, i
2And q
2Reliability identical.Therefore M equals 2.Certainly, if the mapping mode difference of planisphere, for example, the order of 4 bits is i
1q
1i
2q
2, then also can to change accordingly just be 4 to M.If consider the situation of a plurality of planispheres, for example, consider 16QAM, 64QAM and 256QAM simultaneously, then their M value is respectively 2,3 and 4, getting least common multiple like this is exactly 12.Therefore, for considering a plurality of modulation systems simultaneously, M gets the common multiple of a plurality of modulation systems, and representative value is 12.The specific algorithm of sub-block interleaver is as follows:
If T
kBe interim dateout address, AD[i] be data address through the back output that interweaves of sub-block interleaver 501, AD ' [i] is the data address of output after the mould M inverted order of the sub-block interleaver 501 of process is handled, BRO
m(y) m bit inverted order of expression, y is m the numerical value that bit is represented, as: BRO
3(6)=3,6 binary form is shown 110, and 3 binary representation 011.Wherein,
If T
k＜N
AD[i]＝T
k
i++；
k++；
Otherwise
k++
end
Simultaneously, establish j represent sub-block interleaver sequence number (family 1 ..., 6), M is an inverted order bit length fundamental length, q is coefficient (the typical q=2 of M; Maximum=floor of q (N/M)),
If (j mod 6 ≠ knew), (knew is the sequence number of new sub-block interleaver)
AD′[i]＝AD[i]
Otherwise
AD′[i]＝AD[Mq*floor(i/Mq)+11-(i?mod?Mq)]，
end
Here, the general value of N is the integral multiple of Mq, if N is not the integral multiple of Mq, above-mentioned inverted order operation is only operated this length of Mq*floor (N/Mq), and other tail bits are not done the inverted order operation and directly exported.
Shown in 502 among Fig. 5, information bit sequence A and B are one group and import Y simultaneously in decode procedure
1And W
1Be same group of input, Y
2And W
2Be same group of input; Therefore, A and two sub-pieces of B being used in the new interleaving process, because the status of A and two sub-pieces of B is equal to, therefore in no particular order, all is the same to A or the new interleaving block of B use, also can use new interleaving block simultaneously.Fig. 5 only is an example.In like manner to Y
1Perhaps W
1It all is the same using new interleaving block; To Y
2Perhaps W
2It all is the same using new interleaving block.If do not adopt new interleaver, also can the old interleaver of some or all of use, that is, the sub-piece after interweaving is not carried out the mould inverted order.
For whole sub-block interleaving process, A and B, Y
1And W
1, Y
2And W
2All be separate, therefore, can make up/be used sub-block interleaver mutually, in Fig. 5, just used two new sub-block interleaver B and W according to the embodiment of the invention according to the embodiment of the invention
1, this only is an example.Fig. 7 is to use a kind of possibility situation of single sub-block interleaver newly, and single sub-block interleaver can be any one in 6 sub-block interleavers.Fig. 8 is to use a kind of example that may situation of two new sub-block interleavers, and similarly, two new sub-block interleavers can be any two in 6 sub-block interleavers.Fig. 9 is to use the example of a kind of possibility situation of 3 new sub-block interleavers.Figure 10 is to use the example of a kind of possibility situation of 4 new sub-block interleavers.Figure 11 is to use the example of a kind of situation of 5 new sub-block interleavers.Figure 12 is to use the example of 6 new sub-block interleavers.
Figure 13 is the diagrammatic sketch that illustrates according to the structure of another CTC encoder of the embodiment of the invention.As shown in figure 13, wherein, compare with the 1/3CTC encoder, the composition encoder of 1/4CTC encoder carries out duobinary system circulation recursive system convolutional encoding to information bit A, B, obtains three check bit sequence W
1, Y
1And Z
1, any, once more by the composition encoder encodes, export three check bit sequence W behind information bit A, the B process CTC interleaver
2, Y
2And Z
2Interleaver has bit dispenser, sub-block interleaver and three parts of bit groupings device.Figure 14 illustrates the structure according to the sub-block interleaver of the interleaver that is used for the 1/4CTC encoder of the embodiment of the invention.At the bit dispenser input bit sequence is divided into A, B, Y successively
1, Y
2, W
1, W
2, Z
1And Z
2After eight sub-pieces, be used for W
1Sub-block interleaver at first exchange W
1And W
2The position of the output of two sub-pieces, bit sequence W ' then to exporting
1Do the inverted order of mould M.The algorithm of the sub-block interleaver 501 among concrete computational algorithm and Fig. 5 is identical.Similarly, can be to check bit sequence Y
1And Y
2, Z
1And Z
2In any a pair of execution similarly operate.
Figure 15 is the diagrammatic sketch that illustrates according to the structure of another CTC encoder of the embodiment of the invention.As shown in figure 15, the 1/4CTC encoder has two CTC interleavers.The composition encoder of 1/4CTC encoder carries out duobinary system circulation recursive system convolutional encoding to information bit A, B, obtains two check bit sequence W
1, Y
1, information bit A, B respectively through behind two CTC interleavers once more by the composition encoder encodes, export three check bit sequence W
2, Y
2And W
3, Y
3Interleaver has bit dispenser, sub-block interleaver and three parts of bit groupings device.Figure 16 illustrates the structure according to the sub-block interleaver that is used for the 1/4CTC encoder of the embodiment of the invention.At the bit dispenser bit sequence of importing is divided into A, B, Y
1, Y
2, Y
3, W
1, W
2And W
3After eight sub-pieces, at first exchange W
1And W
2The position of the output of two sub-pieces, bit sequence W ' then to exporting
1Do the inverted order of mould M.The algorithm of the sub-block interleaver 501 among concrete computational algorithm and Fig. 5 is identical.Similarly, can be to check bit sequence Y
1, Y
2And Y
3In any antithetical phrase piece implement operation similarly.
Another kind of implementation of the present invention is directly inverted order to be carried out in sub-block interleaver output.The sub-block interleaver of additional embodiments is described according to the present invention with reference to Figure 17-19 pair below.In the following drawings, still describe as example with the 1/3CTC encoder.But the invention is not restricted to this.One skilled in the art will understand that the CTC encoder (for example, 1/4CTC encoder) that method of the present invention can be applied to other types.
Figure 17 illustrates the sub-block interleaver structure of interleaver according to another embodiment of the present invention.At first, A, B, Y
1, Y
2, W
1And W
2After six sub-pieces passed through sub-block interleaving respectively, the bit sequence that obtains was designated as A ', B ', Y '
1, Y '
2, W '
1And W '
2, then, A ' sequence being carried out bit combination, each bit of A ' is placed to first of bit combination sequence according to its order in A '; Then, B ' sequence is carried out bit combination, this bit combination process is equivalent to that B ' is carried out inverted order to be handled, and the B ' sequence after the inverted order is placed to second of bit combination sequence, then, and to Y
1' sequence and Y
2' sequence carries out bit combination, according to original order, Y
1' sequence and Y
2' sequence replace reconfigure Y
1' each bit in the sequence occupied Y
1' and Y
2' odd bits of composite sequence, Y
2' each bit in the sequence occupied Y
1' and Y
2' even bit of composite sequence, Y
1' and Y
2' composite sequence is placed to the 3rd of bit combination sequence, then to W
1' sequence and W
2' sequence carries out bit combination, according to W
1' original order, W
2' inverted order of original order makes up, thereby make W
1' each bit in the sequence occupied W
1' and W
2' even bit of composite sequence, W
2' each bit in the sequence occupied W
1' and W
2' odd bits of composite sequence, and at W
1' and W
2' in the composite sequence, W
2' the inverted order arrangement, W
1' and W
2' composite sequence is placed to the 4th of whole bit combination sequences.
Figure 18 illustrates the sub-block interleaver structure of interleaver according to another embodiment of the present invention.At first, A, B, Y
1, Y
2, W
1And W
2After six sub-pieces passed through sub-block interleaving respectively, the bit sequence that obtains was designated as A ', B ', Y '
1, Y '
2, W '
1And W '
2Then, A ' sequence is carried out bit combination, each bit of A ' is placed to first of bit combination sequence according to its order in A ', then B ' sequence is carried out bit combination, this bit combination process is equivalent to that B ' is carried out inverted order to be handled, and the B ' sequence after the inverted order is placed to second of bit combination sequence, then to Y
1' sequence and Y
2' sequence carries out bit combination, according to original order, Y
1' sequence and Y
2' sequence replace reconfigure Y
1' each bit in the sequence occupied Y
1' and Y
2' odd bits of composite sequence, Y
2' each bit in the sequence occupied Y
1' and Y
2' even bit of composite sequence, Y
1' and Y
2' composite sequence is placed to the 3rd of bit combination sequence, then to W
1' sequence and W
2' sequence carries out bit combination, according to W
1' original order, W
2' inverted order of original order makes up W
1' each bit in the sequence occupied W
1' and W
2' even bit of composite sequence, W
2' each bit in the sequence occupied W
1' and W
2' odd bits of composite sequence, and at W
1' and W
2' in the composite sequence, sequence W
1' and W
2' the inverted order arrangement, W
1' and W
2' composite sequence is placed to the 4th of whole bit combination sequences.
Figure 19 illustrates the sub-block interleaver structure of interleaver according to another embodiment of the present invention.At first, A, B, Y
1, Y
2, W
1And W
2After six sub-pieces passed through sub-block interleaving respectively, the bit sequence that obtains was designated as A ', B ', Y '
1, Y '
2, W '
1And W '
2Then, A ' sequence is carried out bit combination, each bit of A ' is placed to first of bit combination sequence according to its order in A ', then B ' sequence is carried out bit combination, this bit combination process is equivalent to that B ' is carried out inverted order to be handled, and the B ' sequence after the inverted order is placed to second of bit combination sequence, then to Y
1' sequence and Y
2' sequence carries out bit combination, according to original order, Y
1' sequence and Y
2' sequence replace reconfigure Y
1' each bit in the sequence occupied Y
1' and Y
2' odd bits of composite sequence, Y
2' each bit in the sequence occupied Y
1' and Y
2' even bit of composite sequence, Y
1' and Y
2' composite sequence is placed to the 3rd of bit combination sequence, then to W
1' sequence and W
2' sequence carries out bit combination, according to W
1' original order, W
2' inverted order of original order makes up W
1' each bit in the sequence occupied W
1' and W
2' odd bits of composite sequence, W
2' each bit in the sequence occupied W
1' and W
2' even bit of composite sequence, and at W
1' and W
2' in the composite sequence, sequence W
1' and W
2' the inverted order arrangement, W
1' and W
2' composite sequence is placed to the 4th of whole bit combination sequences.
Figure 20 and Figure 21 illustrate traditional employing 16e bit groupings scheme and comparison diagram according to the simulation result of bit groupings scheme under the situation of different block sizes of the embodiment of the invention.Wherein, Figure 18 is that block size is shown is 384 o'clock comparison diagram, and it is 640 o'clock comparison diagram that Figure 20 is illustrated in block size.Simulation result from Figure 20 and Figure 21 is compared with traditional convolution turbo encoding scheme as can be seen, adopts the signal error rate of encoder of sub-block interleaver of the present invention better.
In sum, the invention provides a kind of scheme that is used for the sub-interleaver of convolution turbo coding, compare with traditional sub-interleaver, owing to consider the bit mapping principle in the modulation and observe balanced principle in the decode procedure, guaranteed that the transmission mean reliability of two bits of each group is basic identical.
Though illustrated and described some embodiment of the present invention, but it should be appreciated by those skilled in the art that, under the situation of principle of the present invention that does not break away from the claim qualification and spirit, can make various changes, scope of the present invention limits in claim and equivalent thereof.
Claims (6)
1. one kind is used for the interleaver that convolution turbo sign indicating number is encoded, and described interleaver comprises:
The bit dispenser is divided into a plurality of sub-pieces with the input bit sequence, and described a plurality of sub-pieces comprise 2 sub-pieces of information bit sequence and at least one group of sub-piece of check bit sequence;
Sub-block interleaver exchanges the position of any two the sub-pieces of check bit sequence in a group in the described at least one group of sub-piece of check bit sequence, respectively each height piece is interweaved;
The bit groupings device, the bit sequence grouping that the back that will interweave produces.
2. interleaver as claimed in claim 1 is characterized in that: described sub-block interleaver is to the one or more mould M inverted orders of carrying out in each the height piece that interweaves, and M can be any natural number.
3. interleaver as claimed in claim 2 is characterized in that: the numerical value of M is relevant with baseband modulation mode and modulation constellation.
4. the deinterleaving method of convolution turbo sign indicating number coding comprises:
The input bit sequence is divided into a plurality of sub-pieces, and described a plurality of sub-pieces comprise 2 sub-pieces of information bit sequence and at least one group of sub-piece of check bit sequence;
The position that exchanges any two the sub-pieces of check bit sequence in a group in the described at least one group of sub-piece of check bit sequence also interweaves to each height piece respectively;
The bit sequence grouping that will produce after will interweaving.
5. deinterleaving method as claimed in claim 4 is characterized in that: to the one or more mould M inverted orders of carrying out in each the height piece that interweaves, M can be any natural number after each height piece is interweaved.
6. deinterleaving method as claimed in claim 5 is characterized in that: the numerical value of M is relevant with baseband modulation mode and modulation constellation.
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| CN107786300A (en) * | 2016-08-26 | 2018-03-09 | 中兴通讯股份有限公司 | A kind of data transmission method for uplink and device |
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| US20090022237A1 (en) * | 2007-07-19 | 2009-01-22 | Fujitsu Limited | Symbol interleaving and channel mapping device and method and mobile communication system |
| CN101414836A (en) * | 2007-10-19 | 2009-04-22 | 华为技术有限公司 | Processing method and apparatus for convolution topological encode |
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| CN101075836A (en) * | 2006-12-18 | 2007-11-21 | 浙江华立通信集团有限公司 | Unit for estimating and undistrubing TD-SCDMA/3G/4G terminal signal bit energy |
| US20090022237A1 (en) * | 2007-07-19 | 2009-01-22 | Fujitsu Limited | Symbol interleaving and channel mapping device and method and mobile communication system |
| CN101414836A (en) * | 2007-10-19 | 2009-04-22 | 华为技术有限公司 | Processing method and apparatus for convolution topological encode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107786300A (en) * | 2016-08-26 | 2018-03-09 | 中兴通讯股份有限公司 | A kind of data transmission method for uplink and device |
| CN107786300B (en) * | 2016-08-26 | 2022-06-14 | 中兴通讯股份有限公司 | Data sending method and device |
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