CN102055469B - Phase discriminator and phase locked loop circuit - Google Patents
Phase discriminator and phase locked loop circuit Download PDFInfo
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- CN102055469B CN102055469B CN200910222091.2A CN200910222091A CN102055469B CN 102055469 B CN102055469 B CN 102055469B CN 200910222091 A CN200910222091 A CN 200910222091A CN 102055469 B CN102055469 B CN 102055469B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention relates to a phase discriminator, which comprises a first clock input circuit, a second clock input circuit and a phase difference pulse output circuit, wherein the first clock input circuit is used for receiving a first clock signal, generating a first comparison signal according to the first clock signal and outputting the first comparison signal; the second clock input circuit is used for receiving a second clock signal, generating a second comparison signal according to the second clock signal and outputting the second comparison signal; and the phase difference pulse output circuit is connected to the output ends of the first and second clock input circuits, and is used for generating a positive phase difference pulse signal according to the first and second comparison signals and outputting the positive phase difference pulse signal. The invention also provides a phase locked loop circuit using the phase discriminator. The phase discriminator and the phase locked loop circuit provided by the invention can reduce the workload of programming a microprocessor and reduce the burden of the microprocessor.
Description
Technical field
The present invention relates to a kind of phase discriminator and phase-locked loop circuit, relate in particular to unidirectional clock phase discrimination device and the phase-locked loop circuit of in synchronous communication system, realizing clock phase-locked loop.
Background technology
In communication network, clock synchronous is very important some, and special digital synchronization network is set in the communication network of China, and the supporting network that this digital synchronization network is communication network, is used to communication network that synchronizing clock signals is provided.In order to guarantee that communication network normally works, conventionally utilize digital synchronization network to realize the clock frequency of all nodes in communication network consistent with phase preserving.The digital synchronization network system grade of China is master-slave synchronisation, and lower one-level node obtains frequency reference and is synchronized with its node from higher one-level node.Phase-locked loop circuit is exactly for realizing the basic circuit of clock synchronous, and phase discriminator is one of basic circuit of phase-locked loop circuit.Phase-locked loop circuit, except comprising phase discriminator, also will have loop filter, voltage controlled oscillator etc., and the effect of loop filter is that phase data is carried out to filtering and processing, for regulating the output frequency of voltage controlled oscillator.Phase discriminator can be divided into analogue phase detection device and digital phase discriminator, and analogue phase detection device refers to that the signal of participation phase demodulation is analog signal.Digital phase discriminator refers to that the signal of participation phase demodulation is digital signal.Digital phase discriminator normally compares the phase place of two reference signals and measured signal, thereby obtains the phase difference of the two.In clock synchronous network, reference signal is the clock reference signal of even higher level of node, the clock signal that measured signal is used for this locality obtains after frequency division, phase discriminator be the phase difference for detection of reference signal and measured signal, to obtain Phase Changing and the frequency departure of measured clock signal.Thereby the identified result of phase discriminator is generally divided into two kinds: when measured signal phase place lags behind reference signal always, identified result is forward; When measured signal phase place is ahead of reference signal always, identified result is negative sense.Yet phase discriminator is when carrying out phase demodulation to clock signal, always slowly variation of frequency due to measured signal, especially in loosely coupled PLL, the phase place of a certain moment measured signal may be ahead of reference signal, a certain moment measured signal can lag behind reference signal, thus the identified result obtaining have just also have negative.Because the identified result of phase discriminator need to be exported to loop filter processing, and loop filter is realized by microprocessor, the existing burden that has just again negative identified result can increase processor.
Summary of the invention
The object of the present invention is to provide a kind of phase discriminator and phase-locked loop circuit, make the phase difference pulse signal of output always for just, the loop filter that the positive phase difference pulse signal that it is exported is applicable to being realized by microprocessor is processed, and can alleviate the workload that microprocessor is programmed and the burden that alleviates microprocessor.
The invention provides a kind of phase discriminator, comprise the first clock input circuit, for receiving the first clock signal, and produce the first comparison signal output according to the first clock signal; Second clock input circuit, for receiving second clock signal, and produces the second comparison signal output according to second clock signal; Phase difference impulse output circuit, is connected in the output of described the first clock input circuit and second clock input circuit, for producing positive phase difference pulse signal output according to the first comparison signal and the second comparison signal.
Preferably, above-mentioned phase discriminator also comprises counter, be connected in the output of described phase difference impulse output circuit, for count pick up clock signal, and according to described counting clock signal, described positive phase difference pulse signal counted to the digitized phase signal of rear output.
Preferably, above-mentioned the first clock input circuit comprises that the first inverter is for receiving the first clock signal, and carries out anti-phase to the first clock signal.
Preferably, above-mentioned the first clock input circuit also comprises the first trigger, is connected in the output of described the first inverter, for receiving the first clock signal after anti-phase.
Preferably, above-mentioned the first trigger is also for receiving the first data-signal, the first clock signal after anti-phase and starting phase discrimination signal, and according to described the first data-signal, the first clock signal after anti-phase with start phase discrimination signal and produce the first comparison signal and the second data-signal.
Preferably, above-mentioned second clock input circuit comprises that the second inverter is for receiving second clock signal, and carries out anti-phase to second clock signal.
Preferably, above-mentioned second clock input circuit also comprises the second trigger, is connected in the output of described the second inverter, for receiving the second clock signal after anti-phase.
Preferably, above-mentioned the second trigger is connected in the data output end of described the first trigger, be used for receiving the second data-signal, the second trigger is also for receiving second clock signal after anti-phase and starting phase discrimination signal, and according to described the second data-signal, second clock signal after anti-phase with start phase discrimination signal and produce the second comparison signal.
Preferably, above-mentioned phase difference impulse output circuit is XOR gate, and when the first comparison signal and the second comparison signal are low level or high level, the signal that phase difference impulse output circuit is exported is low level.
Preferably, when one of them of the first comparison signal and the second comparison signal is output as low level, another output be high level time, the signal that phase difference impulse output circuit is exported is high level.
The present invention also provides a kind of phase-locked loop circuit, comprises above-mentioned phase discriminator.
Phase discriminator in the present invention and phase-locked loop circuit, the relation that does not need the phase place lead and lag of definite the first clock input circuit and second clock input circuit, the phase difference value that just can make phase discriminator output is always for just, the positive phase difference pulse signal that it is exported is given the loop filter of being realized by microprocessor, relatively be applicable to microprocessor processes, can alleviate the workload that microprocessor is programmed and the burden that alleviates microprocessor.
Accompanying drawing explanation
Figure 1 shows that the structural representation of a kind of phase discriminator embodiment of the present invention;
Figure 2 shows that the concrete structure schematic diagram of the phase discriminator shown in Fig. 1;
Figure 3 shows that the schematic diagram of phase discriminator identified result;
Figure 4 shows that the structural representation of a kind of phase-locked loop circuit embodiment of the present invention.
The realization of the object of the invention, functional characteristics and advantage, in connection with embodiment, are described further with reference to accompanying drawing.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is described in further detail, so that those skilled in the art can better understand the present invention also, can be implemented, but illustrated embodiment is not as a limitation of the invention.
Figure 1 shows that the structural representation of a kind of phase discriminator 100 embodiment of the present invention.
When phase discriminator in the present embodiment 100 is applied, also can counter 40 be set at phase discriminator 100, be connected in the output of described phase difference impulse output circuit 30, for count pick up clock signal, and according to described counting clock signal, described positive phase difference pulse signal is counted to the digitized phase signal of rear output.
In the present embodiment, phase discriminator 100 is unidirectional digital phase discriminator, the relation that does not need the phase place lead and lag of definite the first clock input circuit 10 and second clock input circuit 20, the phase difference pulse signal that just can make phase discriminator 100 output is always for just, the loop filter that the positive phase difference pulse signal that it is exported is applicable to being realized by microprocessor is processed, and can alleviate the workload that microprocessor is programmed and the burden that alleviates microprocessor.
Figure 2 shows that the concrete structure schematic diagram of the phase discriminator 100 shown in Fig. 1.
The first clock input circuit 10 shown in the first inverter 101 and the first trigger 102 pie graphs 1.The first inverter 101 is for receiving the first clock signal, and carries out anti-phase to the first clock signal.The first trigger 102, is connected in the output of described the first inverter 101, for receiving the first clock signal after anti-phase.The first trigger 102 is also for receiving the first data-signal, above-mentioned the first clock signal after anti-phase and starting phase discrimination signal, and according to described the first data-signal, the first clock signal after anti-phase with start phase discrimination signal and produce the first comparison signal and the second data-signal.The first data-signal and the second data-signal are high level signal, and the first data-signal is the signal that the outside of phase discriminator 100 is inputted.
In the present embodiment, the first clock is reference clock, and frequency is 8KHZ.The first trigger 102 is d type flip flop.After the not circuit that the first clock forms through the first inverter 101, link the input end of clock of the first trigger 102, can guarantee that the first trigger 102 triggers at the trailing edge of the first clock, the signal of the data input pin of the first trigger 102 input simultaneously remains high level, the first trigger 102 is received startup phase discrimination signal by removing termination, when startup phase discrimination signal is low level, the first trigger 102 is not worked, when starting phase discrimination signal when low level becomes high level, the first trigger 102 is started working.
Second clock input circuit 20 shown in the second inverter 201 and the second trigger 202 pie graphs 1.The second inverter 201 is for receiving second clock signal, and carries out anti-phase to second clock signal.Second clock input circuit 20 also comprises the second trigger 202, is connected in the output of described the second inverter 201, for receiving the second clock signal after anti-phase.The second trigger 202 is connected in the data output end of described the first trigger 102, for receiving the second data-signal.The second trigger 202 is also for receiving second clock signal after anti-phase and starting phase discrimination signal, and according to described the second data-signal, second clock signal after anti-phase with start phase discrimination signal and produce the second comparison signal.
In the present embodiment, second clock is measured clock, and its frequency can be set to the frequency identical or approaching with the frequency of the first clock.The second trigger 202 is d type flip flop.After the not circuit that second clock forms through the second inverter 201, link the input end of clock of the second trigger 202, can guarantee that the second trigger 202 triggers at the trailing edge of second clock, the signal of the signal of the data input pin of the second trigger 202 input simultaneously and first input end input is also to remain high level, the second trigger 202 is received startup phase discrimination signal by removing termination, when startup phase discrimination signal is low level, the second trigger 202 is not worked, when starting phase discrimination signal when low level becomes high level, the second trigger 202 is started working.
Phase difference impulse output circuit 30 is XOR gate 301, when the first comparison signal and the second comparison signal are low level or high level, the signal that phase difference impulse output circuit 30 is exported is low level, when one of them of the first comparison signal and the second comparison signal is output as low level, another output be high level time, the signal that phase difference impulse output circuit 30 is exported is high level.
The data input pin of counter 40 connects the output of XOR gate 301, the input end of clock count pick up clock signal of counter 40.In the present embodiment, the figure place of counter 40 is 12, when the frequency of the first comparison signal and the second comparison signal is 8KHZ, when counting clock frequency is 16MHZ, the maximum of the phase demodulation data that phase demodulation is exported is 16MHZ/8KHZ=2048, and the maximum count value of corresponding counter 40 is 2
12=2048, so the precision of phase discriminator 100 is 1/2048.The precision of the phase discriminator 100 in the present embodiment is 1/2048 can meet the requirement of China's clock synchronous network.Certainly, in order to improve the precision of phase discriminator 100, can improve the figure place of the counting clock frequency sum counter 40 of counter 40.
Figure 3 shows that the schematic diagram of phase discriminator 100 identified result.
In Fig. 3, CLK1 is reference clock, and CLK2 is measured clock, START is for starting phase discrimination signal, A is the signal of the output output of the first trigger 102, and B is the signal of the output output of the second trigger 202, and C is the signal of the output output of XOR gate 301.As can be seen from Figure 3, due to the frequency of CLK2 (measured clock) and the frequency of CLK1 (reference clock) very approaching, the second trigger 202 and the first trigger 102 are all when startup phase discrimination signal is high level, to start phase demodulation, and be all to trigger at trailing edge, and the data input pin of the second trigger 202 is the data output end of the first trigger 102, the second comparison signal that the first comparison signal that the first trigger 102 is exported and the second trigger 202 are exported is through XOR gate 301, the Output rusults that can guarantee phase discriminator 100 is just always, thereby make phase difference value that counter 40 sampling obtains also for just.Thereby after phase demodulation order starts, the identified result of phase discriminator 100 is for to start to the positive pulse (dotted portion of C oscillogram) CLK2 trailing edge (dotted portion of B oscillogram) from CLK1 trailing edge (dotted portion of A oscillogram).
Figure 4 shows that the structural representation of a kind of phase-locked loop circuit embodiment of the present invention.
Phase-locked loop circuit in the present embodiment is used the phase discriminator 100 shown in Fig. 1 or Fig. 2 to carry out phase demodulation, and phase-locked loop circuit comprises phase discriminator 100, loop filter 200 and voltage controlled oscillator 300, and the common signal forming of three differs automatic adjusting feedback control loop.The input of loop filter 200 is connected with the output of phase discriminator 100, and the input of voltage controlled oscillator 300 is connected with the output of loop filter 200.Phase-locked loop circuit in the present embodiment is except the circuit structure of phase discriminator 100 is different from existing phase discriminator 100, the circuit structure of loop filter 200 and voltage controlled oscillator 300 and function are all identical with voltage controlled oscillator 300 with existing loop filter 200, therefore do not repeat them here.
Phase-locked loop circuit in the present embodiment is owing to having used unidirectional phase discriminator 100, the relation that does not need the phase place lead and lag of definite the first clock input circuit 10 and second clock input circuit 20, the phase difference pulse signal that just can make phase discriminator 100 output is always for just, the loop filter 200 that the positive phase difference pulse signal that it is exported is applicable to being realized by microprocessor is processed, and can alleviate the workload that microprocessor is programmed and the burden that alleviates microprocessor.
The foregoing is only the preferred embodiments of the present invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes specification of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (5)
1. a phase discriminator, is characterized in that, comprising:
The first clock input circuit, described the first clock input circuit comprises the first inverter and the first trigger, described the first inverter is used for receiving the first clock signal, and carry out anti-phase to the first clock signal, described the first trigger is connected in the output of described the first inverter, for receiving the first clock signal after anti-phase, described the first trigger is also for receiving the first data-signal, the first clock signal after anti-phase and startup phase discrimination signal, and according to described the first data-signal, the first clock signal after anti-phase and startup phase discrimination signal produce the first comparison signal and the second data-signal,
Second clock input circuit, for receiving second clock signal, and produces the second comparison signal output according to second clock signal;
Phase difference impulse output circuit, is connected in the output of described the first clock input circuit and second clock input circuit, for producing positive phase difference pulse signal output according to the first comparison signal and the second comparison signal;
Described second clock input circuit comprises the second inverter, and described the second inverter is used for receiving second clock signal, and carries out anti-phase to second clock signal;
Described second clock input circuit also comprises the second trigger, and described the second trigger is connected in the output of described the second inverter, for receiving the second clock signal after anti-phase;
Described the second trigger is connected in the data output end of described the first trigger, be used for receiving the second data-signal, described the second trigger is also for receiving second clock signal after anti-phase and starting phase discrimination signal, and according to described the second data-signal, second clock signal after anti-phase with start phase discrimination signal and produce the second comparison signal.
2. phase discriminator as claimed in claim 1, it is characterized in that, described phase discriminator also comprises counter, described counter is connected in the output of described phase difference impulse output circuit, for count pick up clock signal, and according to described counting clock signal, described positive phase difference pulse signal is counted to the digitized phase signal of rear output.
3. phase discriminator as claimed in claim 1, is characterized in that, described phase difference impulse output circuit is XOR gate, and when the first comparison signal and the second comparison signal are low level or high level, the signal that phase difference impulse output circuit is exported is low level.
4. phase discriminator as claimed in claim 3, is characterized in that, when one of them of the first comparison signal and the second comparison signal is output as low level, another output be high level time, the signal that phase difference impulse output circuit is exported is high level.
5. a phase-locked loop circuit, is characterized in that, comprises the phase discriminator as described in claim 1 to 4 any one.
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| CN200910222091.2A CN102055469B (en) | 2009-11-05 | 2009-11-05 | Phase discriminator and phase locked loop circuit |
| PCT/CN2010/077496 WO2011054242A1 (en) | 2009-11-05 | 2010-09-29 | Phase discriminator and phase-locked loop circuit |
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| CN200910222091.2A CN102055469B (en) | 2009-11-05 | 2009-11-05 | Phase discriminator and phase locked loop circuit |
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| CN102055469B true CN102055469B (en) | 2014-04-30 |
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| CN102426294B (en) * | 2011-08-05 | 2014-06-04 | 北京星网锐捷网络技术有限公司 | Clock phase difference measurement method and device |
| CN106093572B (en) * | 2016-06-23 | 2018-12-28 | 西安电子科技大学 | High-precision phase position detection circuit and its method for self-calibrating based on integrated phase discriminator AD8302 |
| CN109217951B (en) * | 2018-09-07 | 2020-12-15 | 深圳市紫光同创电子有限公司 | Transmission delay testing method and device based on FPGA |
| CN109039471B (en) * | 2018-09-13 | 2020-05-15 | 上海垣信卫星科技有限公司 | Digital-analog hybrid demodulation method applied to high-speed laser communication |
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| CN1112753A (en) * | 1994-04-07 | 1995-11-29 | Rca汤姆森许可公司 | Phase detector for a phase-lock-loop |
| CN1983815A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Time-delay locking loop |
| CN101459426A (en) * | 2007-12-11 | 2009-06-17 | 海力士半导体有限公司 | Dll clock signal generating circuit capable of correcting a distorted duty ratio |
| CN101471656A (en) * | 2007-12-28 | 2009-07-01 | 联发科技股份有限公司 | Clock generation devices and methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1146112C (en) * | 1999-11-26 | 2004-04-14 | 华为技术有限公司 | Reliable clock phase detecting logic circuit |
| CN100558156C (en) * | 2006-06-08 | 2009-11-04 | 复旦大学 | Be applicable to the clock generation circuit in low dithering of digital TV in high resolution |
| CN101383613B (en) * | 2007-09-04 | 2011-03-30 | 锐迪科科技有限公司 | PLL circuit and oscillation signal phase control method |
| CN101572527A (en) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | High-speed high-jitter-tolerance random-data linear phase detector circuit |
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2009
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1112753A (en) * | 1994-04-07 | 1995-11-29 | Rca汤姆森许可公司 | Phase detector for a phase-lock-loop |
| CN1983815A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Time-delay locking loop |
| CN101459426A (en) * | 2007-12-11 | 2009-06-17 | 海力士半导体有限公司 | Dll clock signal generating circuit capable of correcting a distorted duty ratio |
| CN101471656A (en) * | 2007-12-28 | 2009-07-01 | 联发科技股份有限公司 | Clock generation devices and methods |
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