CN102053220A - Burn-in architecture and burn-in method - Google Patents
Burn-in architecture and burn-in method Download PDFInfo
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- CN102053220A CN102053220A CN200910198596XA CN200910198596A CN102053220A CN 102053220 A CN102053220 A CN 102053220A CN 200910198596X A CN200910198596X A CN 200910198596XA CN 200910198596 A CN200910198596 A CN 200910198596A CN 102053220 A CN102053220 A CN 102053220A
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Abstract
The invention provides a burn-in architecture and a burn-in method. The architecture comprises an ageing test board, a test carrier and a chip function converting board, wherein the ageing test board is provided with a tube pin and a slot, and the tube pin is electrically connected with a pin in the slot; the test carrier is provided with a peripheral pin corresponding to the pin in the slot, and the test carrier is provided with an inside pin electrically connected with the peripheral pin; a chip is encapsulated in the chip function converting board, and the pin of the chip function converting board corresponds to the inside pin of the test carrier; the chip function converting board can be arranged on the test carrier, and the pin of the chip function converting board is electrically connected with the inside pin of the test carrier; and the test carrier can be arranged in the slot of the ageing test board, and the test carrier is electrically connected with the ageing test board. The cost can be reduced, and the burn-in process can be simplified.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of collapsing answered framework and collapsed induction method.
Background technology
After the integrated circuit manufacturing is finished, also need test the quality of judging its performance, and aging of product life experiment is a link of the very important necessary process of product reliability test through product reliability.General common life experiment project has to collapse answers (Burn-in) test, also is called burn-in test.Usually collapse that should to test all be earlier chip to be carried out high temperature and high pressure to handle, quicken that it is aging, force fault in shorter time, to occur.
Collapse to test and comprise that static state collapses and to test, dynamically collapse and to test and monitoring is collapsed and should be tested etc.Collapse the process that should test comprise collapse should with the test two steps: at first collapse should, Fig. 1 is a kind of existing synoptic diagram of answering framework that collapses, as shown in Figure 1, chip 10 is encapsulated on the test carrier 20, the inboard pin of chip input end and output terminal and test carrier 20 is electrical connected; Then test carrier 20 is inserted on the slot 40 in the burn-in board 30 with slot 40 in pin (not shown) be electrical connected, burn-in board 30 has test pin 50, described test pin 50 is electrical connected by lead-in wire and the pin in the slot 50 in the burn-in board 30, then test carrier 20 and burn-in board 30 are electrical connected in test carrier 20 is inserted in described slot 40, thus chip by test carrier 20 just and burn-in board 30 be electrical connected.Fig. 1 schematically illustrates, and in fact burn-in board can comprise a plurality of slots 40.
Then, burn-in board 30 and interior chip 10 thereof are imposed high temperature and high pressure to wear out, for example the burn-in board with chip and place thereof places ageing oven to heat, for example be heated to 150 ℃, keep one day high temperature, the pin by burn-in board is to the chip high-pressure in the burn-in board.
Then, the step of testing, at some aging nodes of chip, in the time of for example aging 24 hours, 48 hours or 168 hours, 500 hours, 1000 hours, chip and burn-in board are taken out from ageing oven, put into the measurement that tester table carries out dc parameter, alternating-current parameter and functional parameter.
For example application number discloses a kind of method that should test that collapses in the american documentation literature of " US5489538 ", wherein static state collapse should test utilized the elder generation to chip pressurize and heating collapse should, test its DC characteristic then, dynamically collapse should test utilized the elder generation to chip pressurize and heating collapse should, test its functional characteristic then.
The existing problem that should test existence that collapses is: the chip difference, the pin of its test carrier and the type of attachment of inner lead are all different, therefore required burn-in board is also different, and so just burn-in board that need be different according to different chip manufacturings has so just caused huge waste.
Summary of the invention
The technical matters that the present invention solves is to reduce cost, and simplifies to collapse and answers technology.
In order to address the above problem, the invention provides a kind of collapsing and answer framework and collapse induction method, comprising:
Burn-in board, it has pin and slot, and the pin in described pin and the slot is electrical connected;
Test carrier, its have with described slot in the peripheral pin of pin correspondence, described test carrier has the inboard pin that is electrical connected with peripheral pin correspondence;
The chip functions change-over panel, portion is packaged with chip within it, the inboard pin correspondence of the pin of described chip functions change-over panel and test carrier;
Wherein said chip functions change-over panel can be installed on the test carrier, and the inboard pin of the pin of chip functions change-over panel and test carrier is electrical connected;
Described test carrier can be installed in the slot of burn-in board by peripheral pin, and test carrier and burn-in board are electrical connected.
Optionally, the pin of described chip functions change-over panel is a pad; The inboard pin of described test carrier is a pad.
Optionally, the peripheral pin of described test carrier is a pad, and the pin in the slot of described burn-in board is a pad.
Optionally, the pin of described chip functions change-over panel is less than or equal to the inboard number of pins of described test carrier.
Optionally, the number of pins in the described burn-in board slot is greater than 2.
Corresponding the present invention also provides a kind of induction method that collapses, and comprises step:
Chip, burn-in board and test carrier are provided, and described burn-in board has slot, described test carrier have with described slot in the peripheral pin of pin correspondence, described test carrier has the inboard pin that is electrical connected with peripheral pin;
Chip is encapsulated, chip is encapsulated form the chip functions change-over panel, and make the inboard pin correspondence of pin and test carrier of described chip functions change-over panel;
The chip functions change-over panel is installed on the test carrier, and the pin of chip functions change-over panel and the inboard pin of test carrier are electrical connected;
Test carrier is installed in the slot of burn-in board, and test carrier and burn-in board are electrical connected.
Optionally, the pin of described chip functions change-over panel is a pad; The inboard pin of described test carrier is a pad.
Optionally, the peripheral pin of described test carrier is a pad, and the pin in the slot of described burn-in board is a pad.
Optionally, the pin of described chip functions change-over panel is less than or equal to the inboard number of pins of described test carrier.
Optionally, the number of pins in the described burn-in board slot is greater than 2.
Compared with prior art, the present invention mainly has the following advantages:
The present invention becomes the chip functions change-over panel with Chip Packaging, because the inboard pin correspondence of the pin of chip functions change-over panel and test carrier, therefore make different kinds of chips, even the unmatched chip of inboard pin of output terminal and test carrier, also can make the inboard pin of its output terminal and test carrier mate by in the process that is encapsulated as the chip functions change-over panel.Further because the pin of test carrier and burn-in board coupling, thereby make the different kinds of chips that output terminal is different, can use identical test carrier and burn-in board, at once do not need to make again test carrier and burn-in board because collapse, therefore reduced cost like this, simplified to collapse and answered technology.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 is existing a kind of synoptic diagram of answering framework that collapses;
Fig. 2 is the synoptic diagram of answering framework that collapses of the present invention;
Fig. 3 is the process flow diagram that collapses induction method of the present invention;
Fig. 4 is a burn-in board structural representation of the present invention;
Fig. 5 is the structural representation of test carrier of the present invention;
Fig. 6 is the structural representation of chip functions change-over panel of the present invention;
Fig. 7 is for being installed in the chip functions change-over panel synoptic diagram on the test carrier;
Fig. 8 is for being installed in test carrier the synoptic diagram on the burn-in board.
Embodiment
By background technology as can be known, should test existing collapsing, need collapse earlier and should just wear out, in that collapse need be with Chip Packaging in test carrier when answering, make burn-in board according to the pin of test carrier then, like this because the IO interface difference of chip, therefore the pin of test carrier is also different, the interface of corresponding burn-in board is also different, thereby need make burn-in board according to the IO interface of chip, makes that like this burn-in board can not be general, so poor compatibility, cause waste, and collapsing of every kind of chip should all need to make earlier burn-in board, answer complex process thereby collapse.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes synoptic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 is the synoptic diagram of answering framework that collapses of the present invention, and as shown in Figure 2, of the present invention collapsing answers framework to comprise burn-in board 110, and it has pin one 10a and slot 110b, and the pin (Fig. 2 is not shown) in described pin one 10a and the slot 110b is electrical connected; Test carrier 120, its have with described slot 110b in the peripheral pin (Fig. 2 is not shown) of pin correspondence, described test carrier 120 has the inboard pin (Fig. 2 is not shown) that is electrical connected with peripheral pin; Chip functions change-over panel 130, portion is packaged with chip 140 within it, inboard pin (Fig. 2 the is not shown) correspondence of pin of described chip functions change-over panel 130 (Fig. 2 is not shown) and test carrier 120; Wherein said chip functions change-over panel 130 can be installed on the test carrier 120, and the inboard pin of the pin of chip functions change-over panel 130 and test carrier 120 is electrical connected; Described test carrier 120 can be installed in the slot 110b of burn-in board 110, and test carrier 120 is electrical connected with burn-in board 110.
Answer framework to further specify below in conjunction with collapsing induction method to of the present invention collapsing.Fig. 3 is the process flow diagram that collapses induction method of the present invention.With reference to figure 3, of the present inventionly should method comprise step:
S10: chip, burn-in board and test carrier are provided, and described burn-in board has slot, described test carrier have with described slot in the peripheral pin of pin correspondence, described test carrier has the inboard pin that is electrical connected with peripheral pin.
Fig. 4 is a burn-in board structural representation of the present invention.
Concrete with reference to figure 4, wherein burn-in board 110 can be existing a kind of burn-in board, but the number of its pin one 10a must could guarantee that like this interface of chip can apply aging voltage by the pin of burn-in board greater than the interface number of the chip that will test.
Burn-in board can comprise a plurality of slot 110b (for clearer signal, a slot 110b has only drawn in Fig. 4), has pin 110c in slot 110b.Pin 110c in described pin one 10a and the slot 110b is electrical connected by inner lead.
Because the number of the pin one 10c in the slot 110b on burn-in board 110 is many more, the chip kind that it can be suitable for is just many more, and the versatility of burn-in board is also just good more.But the pin one 10c in the slot is many more, the area that slot 110b takies is big more, the slot number that the burn-in board 110 of then same area comprises is also just few more, and the number that burn-in board 110 can simultaneously-measured chip is also just few more like this, and testing efficiency is also just low more.Therefore in order both to guarantee the versatility of testing efficiency and burn-in board, in the present embodiment, number of pins in the described burn-in board slot is greater than 2, even for reaching thousands of, for example be 16,512 or 1024, slot count also reaches hundreds of in the corresponding described burn-in board, for example is 12 to 360.For example slot count can be 150, and the number of pins that comprises in each slot is 100, thereby the external pin number of corresponding test carrier also is 100.
Fig. 5 is the structural representation of test carrier of the present invention.As shown in Figure 5, test carrier 120 have with described slot in the peripheral pin 120a of pin 110c correspondence, described test carrier 120 has the inboard pin 120b that is electrical connected with peripheral pin 120a.
In the present embodiment, the pin 110c quantity in the peripheral pin 120a of described test carrier 120 and the described slot is identical, can connect one to one.Described peripheral pin 120a can be the flat pin of the periphery that is positioned at test carrier 120, the pin 110c in the described slot can for be positioned at slot around flat pin.Described peripheral pin 120a also can be the pad of a side being positioned at test carrier 120, and the pin 110c in the described slot also can be the pad of the bottom that is positioned at slot.That described pad comprises is spherical, column etc.
The inboard pin 120b of test carrier 120 can also can be the pad on the side relative with peripheral pin that is positioned at test carrier 120 for being positioned at the flat pin of test carrier 120.That described pad comprises is spherical, column etc.
S20: chip is encapsulated, chip is encapsulated form the chip functions change-over panel, and make the inboard pin correspondence of pin and test carrier of described chip functions change-over panel.
Fig. 6 is the structural representation of chip functions change-over panel of the present invention.
Concrete, as shown in Figure 6, in the process of packaged chip 140, the interface of chip is encapsulated as the pin of chip functions change-over panel.And need consider in encapsulation between the inner pin 120b of the pin 130a of the chip functions change-over panel 130 after making encapsulation and test carrier 120 and mate that described coupling comprises: the coupling of quantity (the pin 130a number of chip functions change-over panel 130 can not greater than the number of the inner pin 120b of test carrier 120); The unanimity of type for example is all flat or the pad formula; And the signal that the pin that is positioned at correspondence position transmits is identical, for example is all data pin or is all the control pin.
Because chip functions change-over panel 130 need be installed on the test carrier 120, and the pin 130a of chip functions change-over panel 130 needs to be connected on the inner pin 120b of test carrier 120, therefore for the pin 130a that guarantees chip functions change-over panel 130 can be connected on the test carrier, then the pin 130a number of chip functions change-over panel 130 can be less than or equal to the number of the inner pin 120b of test carrier 120.
Because the interface number difference of different chips, therefore the number of pins of the chip functions reformer plate after the encapsulation is also different, if utilize general test carrier 120, then for different packaged chips, the pin of the chip functions change-over panel that has may be less than the inboard pin (just the inside pin of test carrier has the free time) of test carrier, and the pin of the chip functions change-over panel that has may equal the inboard pin of test carrier.
Concrete encapsulation process can realize according to the above description for those skilled in the art, therefore repeats no more.
S30: the chip functions change-over panel is installed on the test carrier, and the pin of chip functions change-over panel and the inboard pin of test carrier are electrical connected.
Fig. 7 is for being installed in the chip functions change-over panel synoptic diagram on the test carrier.
Concrete, with reference to figure 7, chip functions change-over panel 130 is installed on the test carrier 120, and make the pin of chip functions change-over panel 130 and the inboard pin of test carrier 120 be electrical connected, the inboard Pin locations correspondence of pad formula of pad formula pin and test carrier 120 with chip functions change-over panel 130 for example shown in Figure 7 is welded then.
Because the interface number difference of different chips, therefore the number of pins of the chip functions reformer plate after the encapsulation is also different, if utilize general test carrier 120, then for different packaged chips, the pin of the chip functions change-over panel that has may be less than the inboard pin (just the inside pin of test carrier has the free time) of test carrier, and the pin of the chip functions change-over panel that has may equal the inboard pin of test carrier.
S40: test carrier is installed in the slot of burn-in board, and test carrier and burn-in board are electrical connected.
Fig. 8 is for being installed in test carrier the synoptic diagram on the burn-in board.
Concrete, with reference to figure 8,, therefore can utilize method well known to those skilled in the art that test carrier is installed on the burn-in board, and make it be electrical connected because the pin in the external pin of test carrier and the burn-in board slot is corresponding one by one.So just can pass through pin making alive, thereby realize interface making alive chip to burn-in board, should so that chip is collapsed.
With reference to above-mentioned collapse induction method as can be known the present invention also provide a kind of collapsing to answer a kind of collapsing of framework to answer framework, comprising: burn-in board, it has pin and slot, the pin in described pin and the slot is electrical connected; Test carrier, its have with described slot in the peripheral pin of pin correspondence, described test carrier has the inboard pin that is electrical connected with peripheral pin; The chip functions change-over panel, portion is packaged with chip within it, the inboard pin correspondence of the pin of described chip functions change-over panel and test carrier; Wherein said chip functions change-over panel can be installed on the test carrier, and the inboard pin of the pin of chip functions change-over panel and test carrier is electrical connected; Described test carrier can be installed in the slot of burn-in board, and test carrier and burn-in board are electrical connected.
Wherein preferred, the pin of described chip functions change-over panel is a pad; The inboard pin of described test carrier is a pad.That described pad comprises is spherical, column etc.
Wherein preferred, the peripheral pin of described test carrier is a pad, and the pin in the slot of described burn-in board is a pad.That described pad comprises is spherical, column etc.
Wherein preferred, the pin of described chip functions change-over panel is less than or equal to the inboard number of pins of described test carrier.
Wherein preferred, the number of pins in the described burn-in board slot is greater than 2, even for reaching thousands of, for example is 16,512 or 1024, and slot count also reaches hundreds of in the corresponding described burn-in board, for example is 12 to 360.For example slot count can be 150, and the number of pins that comprises in each slot is 100, thereby the external pin number of corresponding test carrier also is 100.。
The present invention has utilized elder generation that Chip Packaging is formed the chip functions change-over panel, make that the pin arrangements of chip functions change-over panel is predefined pattern, just with the pattern of the inboard pin correspondence of general test carrier, even the interface difference of different like this chips, by just having obtained the identical chip functions change-over panel of pin arrangements after encapsulating, so just can use general test carrier, because test carrier is general, that is to say that the employed test carrier pin arrangements of different chips is identical, it is general that thereby burn-in board also can use, so just do not need every kind of chip to manufacture and design a kind of burn-in board separately, therefore greatly reduce and collapse the complexity of answering technology, reduce cost, reduced waste.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (10)
1. one kind collapses and answers framework, it is characterized in that, comprising:
Burn-in board, it has pin and slot, and the pin in described pin and the slot is electrical connected;
Test carrier, its have with described slot in the peripheral pin of pin correspondence, described test carrier has the inboard pin that is electrical connected with peripheral pin correspondence;
The chip functions change-over panel, portion is packaged with chip within it, the inboard pin correspondence of the pin of described chip functions change-over panel and test carrier;
Wherein said chip functions change-over panel can be installed on the test carrier, and the inboard pin of the pin of chip functions change-over panel and test carrier is electrical connected;
Described test carrier can be installed in the slot of burn-in board by peripheral pin, and test carrier and burn-in board are electrical connected.
2. according to claim 1 collapsing answered framework, it is characterized in that, the pin of described chip functions change-over panel is a pad; The inboard pin of described test carrier is a pad.
3. according to claim 1 collapsing answered framework, it is characterized in that, the peripheral pin of described test carrier is a pad, and the pin in the slot of described burn-in board is a pad.
4. according to claim 1 collapsing answered framework, it is characterized in that, the pin of described chip functions change-over panel is less than or equal to the inboard number of pins of described test carrier.
5. according to claim 1 collapsing answered framework, it is characterized in that, the number of pins in the described burn-in board slot is greater than 2.
6. one kind collapses induction method, it is characterized in that, comprises step:
Chip, burn-in board and test carrier are provided, and described burn-in board has slot, described test carrier have with described slot in the peripheral pin of pin correspondence, described test carrier has the inboard pin that is electrical connected with peripheral pin;
Chip is encapsulated, chip is encapsulated form the chip functions change-over panel, and make the inboard pin correspondence of pin and test carrier of described chip functions change-over panel;
The chip functions change-over panel is installed on the test carrier, and the pin of chip functions change-over panel and the inboard pin of test carrier are electrical connected;
Test carrier is installed in the slot of burn-in board, and test carrier and burn-in board are electrical connected.
7. the induction method that collapses according to claim 6 is characterized in that the pin of described chip functions change-over panel is a pad; The inboard pin of described test carrier is a pad.
8. the induction method that collapses according to claim 6 is characterized in that the peripheral pin of described test carrier is a pad, and the pin in the slot of described burn-in board is a pad.
9. the induction method that collapses according to claim 6 is characterized in that the pin of described chip functions change-over panel is less than or equal to the inboard number of pins of described test carrier.
10. according to claim 6 collapsing answered framework, it is characterized in that, the number of pins in the described burn-in board slot is greater than 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910198596XA CN102053220A (en) | 2009-11-10 | 2009-11-10 | Burn-in architecture and burn-in method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910198596XA CN102053220A (en) | 2009-11-10 | 2009-11-10 | Burn-in architecture and burn-in method |
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| CN102053220A true CN102053220A (en) | 2011-05-11 |
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| CN200910198596XA Pending CN102053220A (en) | 2009-11-10 | 2009-11-10 | Burn-in architecture and burn-in method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179031A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Composite tester and use method thereof |
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| JPS5989446A (en) * | 1982-11-15 | 1984-05-23 | Mitsubishi Electric Corp | Coupling device for semiconductor device |
| WO1996002845A1 (en) * | 1994-07-19 | 1996-02-01 | Liang Louis H | Methods and apparatus for test and burn-in of integrated circuit devices |
| US5859538A (en) * | 1996-01-31 | 1999-01-12 | Hewlett-Packard Company | Method and apparatus for connecting a ball grid array device to a test instrument to facilitate the monitoring of individual signals or the interruption of individual signals or both |
| US6071128A (en) * | 1998-04-28 | 2000-06-06 | International Business Machines Corporation | Integrated circuit socket with built in EMC grounding for a heat sink |
| CN101359020A (en) * | 2007-08-03 | 2009-02-04 | 中芯国际集成电路制造(上海)有限公司 | Aging testing substrates |
| CN101545947A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Ageing testing board and ageing testing method general for various products |
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2009
- 2009-11-10 CN CN200910198596XA patent/CN102053220A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5989446A (en) * | 1982-11-15 | 1984-05-23 | Mitsubishi Electric Corp | Coupling device for semiconductor device |
| WO1996002845A1 (en) * | 1994-07-19 | 1996-02-01 | Liang Louis H | Methods and apparatus for test and burn-in of integrated circuit devices |
| US5859538A (en) * | 1996-01-31 | 1999-01-12 | Hewlett-Packard Company | Method and apparatus for connecting a ball grid array device to a test instrument to facilitate the monitoring of individual signals or the interruption of individual signals or both |
| US6071128A (en) * | 1998-04-28 | 2000-06-06 | International Business Machines Corporation | Integrated circuit socket with built in EMC grounding for a heat sink |
| CN101359020A (en) * | 2007-08-03 | 2009-02-04 | 中芯国际集成电路制造(上海)有限公司 | Aging testing substrates |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022179031A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Composite tester and use method thereof |
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Application publication date: 20110511 |