CN102045284B

CN102045284B - Frequency shift keying (FSK) demodulating device

Info

Publication number: CN102045284B
Application number: CN 201010034477
Authority: CN
Inventors: 赵博; 杨华中
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2010-01-21
Filing date: 2010-01-21
Publication date: 2013-06-05
Anticipated expiration: 2030-01-21
Also published as: CN102045284A

Abstract

The invention discloses a frequency shift keying (FSK) demodulating device. The FSK demodulating device comprises a demodulator with an active resistor-capacitor (RC) structure, a low pass filter with the active RC structure, a differentiator with the active RC structure and a hysteresis comparator. The FSK demodulating device performs demodulation by adopting a combined structure of the demodulator with the active RC structure and the low pass filter with the active RC structure, so that the FSK demodulating device has the advantages of simple structure, large dynamic range and low power consumption; and the FSK demodulating device performs data judgment by adopting a combined structure of the differentiator with the active RC structure and the hysteresis comparator, so that the FSK demodulating device can resist frequency shift well and has low power consumption and large dynamic range. Furthermore, time constants of the demodulator, the low pass filter with the active RC structure and the differentiator with the active RC structure are corrected through only one set of time constant correcting circuits, so that the FSK demodulating device has the advantages of process deviation resistance, low power consumption and low cost.

Description

The FSK demodulating equipment

Technical field

The present invention relates to complementary metal oxide semiconductors (CMOS) (Complementary Metal OxideSemiconductor, hereinafter to be referred as COMS) the circuit design technique field, be particularly related to a kind of frequency shift keying (Frequency Shift Keying is hereinafter to be referred as FSK) demodulating equipment.

Background technology

In Modern Communication System, FSK is a kind of widely used modulation system, has to realize the advantages such as simple, low in energy consumption, long transmission distance.

For the FSK demodulation scheme, prior art one adopts phase-locked loop to carry out demodulation, for example, adopts the method for Double feedback phase locking ring to obtain high accuracy and large tuning range.But complex structure, power consumption is large, cost is high.Prior art two adopts the method for two-way mixing to carry out demodulation, but does not provide the bearing calibration of resistance-capacitance (Resistor-Capacitor is hereinafter to be referred as RC) time constant, and the data decision part-structure is complicated, and power consumption is larger.The demodulator that prior art three adopts based on delay lock loop (Delay-Locked Loop is hereinafter to be referred as DLL) has baroque shortcoming equally.Prior art four adopts the method for zero-crossing comparator to carry out demodulation, and follow-up DC drift eliminator is too complicated.Prior art five adopts the demodulation scheme of discrete time, does not need specialized designs direct current offset bucking circuit, but complex time, cost is high, poor reliability.For data decision circuit, prior art six adopts the method for Gm-C differentiators and hysteresis comparator combination to come cancellation of DC offset, but the Gm-C differentiator design is difficult, tuningly is difficult to realization, and cost is high.

Summary of the invention

The technical problem that (one) will solve

The technical problem to be solved in the present invention is to provide a kind of FSK demodulator, and to solve existing fsk demodulator complex structure, power consumption is large, the high in cost of production defective.

(2) technical scheme

For this reason, a kind of FSK demodulating equipment provided by the invention comprises:

The demodulator of Active RC structure, the orthogonal differential input of described demodulator is connected with the orthogonal differential input of described FSK demodulating equipment, and the bias voltage input of described demodulator is connected with the first bias voltage input of FSK demodulating equipment;

The low pass filter of Active RC structure, the differential input end of described low pass filter is connected with the difference output end of described demodulator;

Differentiator, the differential input end of described differentiator is connected with the difference output end of described low pass filter;

Hysteresis comparator, the differential input end of described hysteresis comparator is connected with the difference output end of described differentiator, the bias voltage input of described hysteresis comparator is connected with the second bias voltage input of described FSK demodulating equipment, and the output of described hysteresis comparator is connected with the output of described FSK demodulating equipment.

Wherein,

Described demodulator comprises:

two differential multipliers, the I road in-phase input end of the first differential multiplier, the I road in-phase input end of the Q road in-phase input end of the second differential multiplier and described demodulator is connected, the Q road in-phase input end of described the first differential multiplier, the Q road in-phase input end of the I road inverting input of the second differential multiplier and described demodulator is connected, the I road inverting input of described the first differential multiplier, the I road inverting input of the Q road inverting input of the second differential multiplier and described demodulator is connected, the Q road inverting input of described the first differential multiplier, the Q road inverting input of the I road in-phase input end of the second differential multiplier and described demodulator is connected, the in-phase output end of the in-phase output end of described the first differential multiplier, the second differential multiplier is connected with the in-phase output end of described demodulator, the reversed-phase output of the reversed-phase output of described the first differential multiplier, the second differential multiplier is connected with the reversed-phase output of described demodulator, and the control word input of the control word input of described the first differential multiplier, the second differential multiplier is connected with the control word input of described demodulator,

Load circuit, the in-phase end of the bidirectional port of described load circuit is connected with the in-phase output end of described demodulator, and the end of oppisite phase of the bidirectional port of described load circuit is connected with the reversed-phase output of described demodulator; The bias voltage input of the bias voltage input of the bias voltage input of described load circuit, the first differential multiplier, the second differential multiplier is connected with the bias voltage input of described demodulator.

Described differential multiplier comprises:

eight PMOS pipes, the source electrode of the one PMOS pipe, the source electrode of the 2nd PMOS pipe is connected with power supply, the grid of a described PMOS pipe is connected with the grid of the 3rd PMOS pipe, the grid of described the 2nd PMOS pipe is connected with the grid of the 4th PMOS pipe, the source electrode of described the 3rd PMOS pipe, the source electrode of the 4th PMOS pipe is connected with power supply, the source electrode of the 5th PMOS pipe, the source electrode of the 6th PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the source electrode of the 7th PMOS pipe, the source electrode of the 8th PMOS pipe is connected with the drain electrode of described the 4th PMOS pipe, the grid of described the 5th PMOS pipe, the Q road in-phase input end of the grid of the 8th PMOS pipe and described differential multiplier is connected, the grid of described the 6th PMOS pipe, the I road inverting input of the grid of the 7th PMOS pipe and described differential multiplier is connected, the drain electrode of described the 6th PMOS pipe, the drain electrode of the 8th PMOS pipe is connected with the in-phase output end of described differential multiplier, the drain electrode of described the 5th PMOS pipe, the drain electrode of the 7th PMOS pipe is connected with the reversed-phase output of described differential multiplier,

Two NMOS pipes, the drain electrode of the one NMOS pipe is connected with the drain electrode of a described PMOS pipe, the source ground of a described NMOS pipe, the drain electrode of the 2nd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, the source ground of described the 2nd NMOS pipe, the grid of the grid of a described NMOS pipe, the 2nd NMOS pipe is connected with the bias voltage input of described differential multiplier;

Two numerical control variable capacitance arrays, the first numerical control variable capacitance array connects the I road in-phase input end of described differential multiplier and the drain electrode of a PMOS pipe, the second numerical control variable capacitance array connects the Q road inverting input of described differential multiplier and the drain electrode of the 2nd PMOS pipe, and the control word input of the control word input of described the first numerical control variable capacitance array, the second numerical control variable capacitance array is connected with the control word input of differential multiplier;

Two electric resistance arrays, the first electric resistance array connects the Q road in-phase input end of described differential multiplier and the drain electrode of a PMOS pipe, and the second electric resistance array connects the I road inverting input of described differential multiplier and the drain electrode of the 2nd PMOS pipe;

An operational amplifier, the inverting input of described operational amplifier is connected with the drain electrode of a PMOS pipe, the in-phase input end of described operational amplifier is connected with the drain electrode of the 2nd PMOS pipe, the in-phase output end of described operational amplifier is connected with the grid of a PMOS pipe, and the reversed-phase output of described operational amplifier is connected with the grid of the 2nd PMOS pipe.

Described load circuit comprises:

Four PMOS pipes, the source electrode of the one PMOS pipe is connected with the source electrode of the 2nd PMOS pipe, the drain electrode of the 3rd PMOS pipe is connected to the source electrode of a described PMOS pipe, the source electrode of described the 3rd PMOS pipe connects power supply, the grid of the 4th PMOS pipe is connected to the grid of described the 3rd PMOS pipe, the grid of described the 4th PMOS pipe is connected with the drain electrode of the 4th PMOS pipe, and the source electrode of described the 4th PMOS pipe connects power supply.

seven NMOS pipes, the grid of the one NMOS pipe with the drain electrode be connected after, be connected to the drain electrode of a described PMOS pipe, the grid of the 2nd NMOS pipe with the drain electrode be connected after, be connected to the drain electrode of described the 2nd PMOS pipe, the drain electrode of the 3rd NMOS pipe is connected to the drain electrode of described the 4th PMOS pipe, the drain electrode of the 4th NMOS pipe is with after the drain electrode of the 5th NMOS pipe is connected, be connected to the end of oppisite phase of described load circuit bidirectional port, the drain electrode of the 6th NMOS pipe is with after the drain electrode of the 7th NMOS pipe is connected, be connected to the in-phase end of described load circuit bidirectional port, after the grid of the grid of the 4th NMOS pipe and the 7th NMOS pipe is connected, be connected to the grid of the 2nd NMOS pipe, the grid of the 3rd NMOS pipe, after the grid of the grid of the 5th NMOS pipe and the 6th NMOS pipe is connected, be connected to the bias voltage input of described load circuit, ground connection after the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe is connected,

Four resistance, the first resistance connects grid and the power supply of described the 2nd PMOS pipe, the second resistance connects grid and the ground of described the 2nd PMOS pipe, the end of oppisite phase of the grid of the 3rd described PMOS pipe of resistance connection and the bidirectional port of load circuit, the in-phase end of the grid of the 4th described PMOS pipe of resistance connection and the bidirectional port of load circuit.

Described low pass filter comprises:

Three operational amplifiers and 14 electric resistance arrays, the inverting input of the first operational amplifier is connected by the first electric resistance array with the same input of described low pass filter, and the in-phase input end of described the first operational amplifier is connected by the second electric resistance array with the inverting input of described low pass filter; The inverting input of the second operational amplifier is connected by the 5th electric resistance array with the in-phase output end of described the first operational amplifier, and the in-phase input end of described the second operational amplifier is connected by the 6th electric resistance array with the reversed-phase output of described the first operational amplifier; The inverting input of the 3rd operational amplifier is connected with the same output of described the second operational amplifier by the 9th electric resistance array, the in-phase input end of described the 3rd operational amplifier is connected by the reversed-phase output of the tenth electric resistance array with described the second operational amplifier, the in-phase output end of described the 3rd operational amplifier is connected with the reversed-phase output of described low pass filter, and the reversed-phase output of described the 3rd operational amplifier is connected with the in-phase output end of described low pass filter;

the 3rd electric resistance array connects the inverting input of described the first operational amplifier and the in-phase output end of the first operational amplifier, the 4th electric resistance array connects the in-phase input end of described the first operational amplifier and the reversed-phase output of the first operational amplifier, the 7th electric resistance array connects the inverting input of described the second operational amplifier and the in-phase output end of the second operational amplifier, the 8th electric resistance array connects the in-phase input end of described the second operational amplifier and the reversed-phase output of the second operational amplifier, the 11 electric resistance array connects the inverting input of described the 3rd operational amplifier and the in-phase output end of the 3rd operational amplifier, the 12 electric resistance array connects in-phase input end and the reversed-phase output of described the 3rd operational amplifier, the 13 electric resistance array connects the reversed-phase output of described the 3rd operational amplifier and the inverting input of the second operational amplifier, the 14 electric resistance array connects the in-phase output end of described the 3rd operational amplifier and the in-phase input end of the second operational amplifier,

six numerical control variable capacitance arrays, the first numerical control variable capacitance array connects the inverting input of described the first operational amplifier and the in-phase output end of the first operational amplifier, the second numerical control variable capacitance array connects the in-phase input end of described the first operational amplifier and the reversed-phase output of the first operational amplifier, the 3rd numerical control variable capacitance array connects the inverting input of described the second operational amplifier and the in-phase output end of the second operational amplifier, the 4th numerical control variable capacitance array connects the in-phase input end of described the second operational amplifier and the reversed-phase output of the second operational amplifier, the 5th numerical control variable capacitance array connects the inverting input of described the 3rd operational amplifier and the in-phase output end of the 3rd operational amplifier, the 6th numerical control variable capacitance array connects the in-phase input end of described the 3rd operational amplifier and the reversed-phase output of the 3rd operational amplifier, the control word input of the control word input of the control word input of the control word input of the control word input of the control word input of described the first numerical control variable capacitance array, the second numerical control variable capacitance array, the 3rd numerical control variable capacitance array, the 4th numerical control variable capacitance array, the 5th numerical control variable capacitance array and the 6th numerical control variable capacitance array is connected with the control word input of described low pass filter.

Described differentiator is the Active RC structure, comprising:

Two operational amplifiers and eight electric resistance arrays, the inverting input of the first operational amplifier is connected with the in-phase input end of described differentiator by the first electric resistance array, and the in-phase input end of described the first operational amplifier is connected with the inverting input of described differentiator by the second electric resistance array; The inverting input of the second operational amplifier is connected by the in-phase output end of the 5th electric resistance array with described the first operational amplifier, the in-phase input end of described the second operational amplifier is connected by the reversed-phase output of the 6th electric resistance array with described the first operational amplifier, the reversed-phase output of described the second operational amplifier is connected by the inverting input of the 7th electric resistance array with the first operational amplifier, and the in-phase output end of described the second operational amplifier is connected by the in-phase input end of the 8th electric resistance array with the first operational amplifier;

The 3rd electric resistance array connects the inverting input of described the first operational amplifier and the in-phase output end of the first operational amplifier, and the 4th electric resistance array connects the in-phase input end of described the first operational amplifier and the reversed-phase output of the first operational amplifier;

four numerical control variable capacitance arrays, the first numerical control variable capacitance array connects the inverting input of described the first operational amplifier and the in-phase output end of the first operational amplifier, the second numerical control variable capacitance array connects the in-phase input end of described the first operational amplifier and the reversed-phase output of the first operational amplifier, the 3rd numerical control variable capacitance array connects the inverting input of described the second operational amplifier and the in-phase output end of the second operational amplifier, the 4th numerical control variable capacitance array connects the in-phase input end of described the second operational amplifier and the reversed-phase output of the second operational amplifier, the control word input of four numerical control variable capacitance arrays is connected with the control word input of described differentiator.

In technique scheme, described hysteresis comparator is the voltage follower structure of upset, comprising:

six PMOS pipes, the grid of the one PMOS pipe is connected with the inverting input of described hysteresis comparator, the grid of the 2nd PMOS pipe is connected with the in-phase input end of described hysteresis comparator, the source electrode of a described PMOS pipe is connected with the source electrode of the 2nd PMOS pipe, the grid of the 3rd PMOS pipe and drain electrode, be connected with the grid of the 4th PMOS pipe, the drain electrode of the 5th PMOS pipe is connected with the source electrode of a described PMOS pipe and the source electrode of the 2nd PMOS pipe, the source electrode of the 6th PMOS pipe is connected with the drain electrode of described the 5th PMOS pipe, the drain electrode of described the 6th PMOS pipe is connected with the grid of the 5th PMOS pipe, the source electrode of described the 3rd PMOS pipe, the source electrode of the 4th PMOS pipe, the source electrode of the 5th PMOS pipe is connected with power supply,

seven NMOS pipes, the drain electrode of the grid of a NMOS pipe, the 2nd NMOS pipe is connected with the drain electrode of a described PMOS pipe, and the drain electrode of the grid of the 2nd NMOS pipe, a described NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, the grid of the 3rd NMOS pipe and drain electrode, be connected with the grid of a described NMOS pipe, the grid of the 4th NMOS pipe and drain electrode, be connected with the grid of described the 2nd NMOS pipe, the grid of the 5th NMOS pipe is connected with the drain electrode of described the 3rd NMOS pipe, the drain electrode of the 5th NMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the grid of the 6th NMOS pipe is connected with the drain electrode of described the 4th NMOS pipe, the drain electrode of described the 6th NMOS pipe is connected with the drain electrode of described the 4th PMOS pipe, the grid of the 7th NMOS pipe is connected with the bias voltage input of described hysteresis comparator, the drain electrode of described the 7th NMOS pipe is connected with the drain electrode of the 6th PMOS pipe, the source electrode of a described NMOS pipe, the source electrode of the 2nd NMOS pipe, the source electrode of the 3rd NMOS pipe, the source electrode of the 4th NMOS pipe, the source electrode of the 5th NMOS pipe, the source ground of the source electrode of the 6th NMOS pipe and the 7th NMOS pipe,

Two electric resistance arrays, the first electric resistance array connects the grid of power supply and described the 6th PMOS pipe, and the second electric resistance array connects grid and the ground of described the 6th PMOS pipe;

An inverter, the input of described inverter is connected with the drain electrode of described the 6th NMOS pipe, and the output of described inverter is connected with the output of described hysteresis comparator.

Technique scheme also comprises: the time constant correcting circuit, the Capacity control word output of described time constant correcting circuit is connected with the control word input of the control word input of described demodulator, low pass filter and the control word input of differentiator.

Described time constant correcting circuit comprises:

A bandgap source is used for providing reference voltage to the modules of described time constant correcting circuit;

A digital circuit blocks is used for carrying out figure adjustment;

Four operational amplifiers, the in-phase input end of the in-phase input end of the in-phase input end of the first operational amplifier, the second operational amplifier, the 3rd operational amplifier and the inverting input of four-operational amplifier all are connected with described bandgap source, the inverting input of the output of described the second operational amplifier and the 3rd operational amplifier, and the in-phase input end of four-operational amplifier is connected;

An electric resistance array, connect described the first operational amplifier inverting input and ground;

A numerical control variable capacitance array connects inverting input and the output of described the second operational amplifier, control word input and the digital circuit blocks of described numerical control variable capacitance array, and the output of described time constant correcting circuit is connected;

Two NMOS pipes, the grid of the one NMOS pipe connects the output of described the first operational amplifier, the drain electrode of a described NMOS pipe is connected with the inverting input of the second operational amplifier, the source electrode of a described NMOS pipe is connected with the inverting input of the first operational amplifier, the source electrode of the 2nd NMOS pipe is connected with the inverting input of the second operational amplifier, the drain electrode of described the 2nd NMOS pipe is connected with the output of the second operational amplifier, and the grid of described the 2nd NMOS pipe is connected with digital circuit blocks.

Described numerical control variable capacitance array comprises:

At least four NMOS pipe, the source electrode of the source electrode of a NMOS pipe, the 2nd NMOS pipe is connected with the first end of described numerical control variable capacitance array; The drain electrode of the 3rd NMOS pipe is connected with the drain electrode of the 4th NMOS pipe, the drain electrode of a described NMOS pipe is connected with the source electrode of the 3rd NMOS pipe, the drain electrode of described the 2nd NMOS pipe is connected with the source electrode of the 4th NMOS pipe, the grid of a described NMOS pipe is connected with the primary input of control word, and the grid of described the 2nd NMOS pipe is connected with the deputy input of control word;

At least two inverters, the input of described the first inverter is connected with the grid of a NMOS pipe, and the output of described the first inverter is connected with the grid of the 3rd NMOS pipe; The input of described the second inverter is connected with the grid of the 2nd NMOS pipe, and the output of described the second inverter is connected with the grid of the 4th NMOS pipe;

At least two electric capacity, the first electric capacity connects the drain electrode of a described NMOS pipe and the second end of numerical control variable capacitance array, and the second electric capacity connects the drain electrode of described the 2nd NMOS pipe and the second end of numerical control variable capacitance array;

Two resistance, the first resistance connects drain electrode and the power supply of described the 3rd NMOS pipe, and the second resistance connects drain electrode and the ground of described the 3rd NMOS pipe.

(3) beneficial effect

Technique scheme has following advantage: FSK demodulating equipment of the present invention by adopting the Active RC structure demodulator and the structure of low pass filter combination carry out demodulation, have simple in structurely, dynamic range is large, advantage low in energy consumption; And, carry out data decision by the differentiator of employing Active RC structure and the structure of hysteresis comparator combination, can be good at anti-frequency shift (FS), and low in energy consumption, dynamic range is large; Further, the present invention with the time constant of the differentiator of the low pass filter of a cover time constant correcting circuit correction demodulator, Active RC structure and Active RC structure, makes the FSK demodulating equipment of invention reach anti-process deviation, the beneficial effect that low in energy consumption and cost is low by only.

Description of drawings

Fig. 1 is the electrical block diagram of FSK demodulating equipment embodiment one of the present invention;

Fig. 2 is the electrical block diagram of demodulator in Fig. 1;

Fig. 3 is the electrical block diagram of differential multiplier in Fig. 2;

Fig. 4 is the electrical block diagram of numerical control variable capacitance array in Fig. 3;

Fig. 5 is the electrical block diagram of load circuit in Fig. 2;

Fig. 6 is the electrical block diagram of low pass filter in Fig. 1;

Fig. 7 is the electrical block diagram of differentiator in Fig. 1;

Fig. 8 is the electrical block diagram of hysteresis comparator in Fig. 1;

Fig. 9 is the electrical block diagram of FSK demodulating equipment embodiment two of the present invention;

Figure 10 is the electrical block diagram of time constant correcting circuit in Fig. 9.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for explanation the present invention, but are not used for limiting the scope of the invention.

So as Fig. 1, be the electrical block diagram of FSK demodulating equipment embodiment one of the present invention.The FSK demodulating equipment of the present embodiment comprises: demodulator DEM1, low pass filter LF2, differentiator DIF3 and hysteresis comparator COM4.

Wherein, two-way orthogonal differential input dip, dqp, din and the dqn of DEM1 is connected with sqn with two-way orthogonal differential input sip, sqp, the sin of FSK demodulating equipment respectively, and the bias voltage input dvb of DEM1 is connected with the first bias voltage input vb1 of FSK demodulating equipment.The differential input end ip of LF2 is connected with don with the difference output end dop of DEM1 respectively with in.The differential input end ip of DIF3 is connected with on the difference output end op of LF2 respectively with in.The differential input end ip of COM4 is connected with on the difference output end op of DIF3 respectively with in, the bias voltage input cvb of COM4 is connected with the second bias voltage input vb2 of FSK demodulating equipment, and the output out of COM4 is connected with the output sout of FSK demodulating equipment.

As shown in Figure 2, be the electrical block diagram of demodulator in Fig. 1; The demodulator of the present embodiment comprises: two differential multiplier DM1 and DM2, a load circuit LOAD1.

Wherein the I road in-phase input end ip of DM1 is with after the Q road in-phase input end qp of DM2 is connected, be connected to the I road in-phase input end dip of DEM1, the Q road in-phase input end qp of DM1 is with after the I road inverting input in of DM2 is connected, be connected to the Q road in-phase input end dqp of DEM1, the I road inverting input in of DM1 is with after the Q road inverting input qn of DM2 is connected, be connected to the I road inverting input din of DEM1, the Q road inverting input qn of DM1 is connected to the Q road inverting input dqn of DEM1 with after the I road in-phase input end ip of DM2 is connected.After the in-phase output end op of DM1 and the in-phase output end op of DM2 are connected, be connected to the in-phase output end dop of DEM1, after the reversed-phase output on of DM1 and the reversed-phase output on of DM2 are connected, be connected to the reversed-phase output don of DEM1, the control word input csw of DM1 is connected to the control word input dsw of DEM1 with after the control word input csw of DM2 is connected.The in-phase end iop of the bidirectional port of LOAD1 is connected with the in-phase output end dop of DEM1, and the end of oppisite phase ion of the bidirectional port of LOAD1 is connected with the reversed-phase output don of DEM1.After the bias voltage input vb of bias voltage input vb, the DM1 of LOAD1 and the bias voltage input vb of DM2 are connected, be connected to the bias voltage input dvb of DEM1.

As shown in Figure 3, be the electrical block diagram of differential multiplier in Fig. 2; The differential multiplier DM of the present embodiment is the Active RC structure, comprises eight PMOS pipe, two NMOS pipes, an operational amplifier OTA1, two numerical control capacitor array CA1 and CA2, two electric resistance array RA1 and RA2.

wherein, after the source electrode of PMOS pipe Mp1 and PMOS pipe Mp2 is connected, D is connected with power vd, the grid of PMOS pipe Mp3 is connected with the Mp1 grid of PMOS pipe, the grid of PMOS pipe Mp4 is connected with the grid of PMOS pipe Mp2, after the source electrode that the source electrode of PMOS pipe Mp3 and PMOS manage Mp4 is connected, be connected with power vd D again, after the source electrode that the source electrode of PMOS pipe Mp5 and PMOS manage Mp6 is connected, be connected with the drain electrode of PMOS pipe Mp3, after the source electrode that the source electrode of PMOS pipe Mp7 and PMOS manage Mp8 is connected, be connected to the drain electrode of PMOS pipe Mp4, after the grid that the grid of PMOS pipe Mp5 and PMOS manage Mp8 is connected, be connected to the Q road in-phase input end qp of differential multiplier, after the grid that the grid of PMOS pipe Mp6 and PMOS manage Mp7 is connected, be connected with the I road inverting input in of differential multiplier again, after the drain electrode that the drain electrode of PMOS pipe Mp6 and PMOS manage Mp8 is connected, be connected with the in-phase output end op of differential multiplier again, after the drain electrode that the drain electrode of PMOS pipe Mp5 and PMOS manage Mp7 is connected, be connected with the reversed-phase output on of differential multiplier again.The drain electrode of NMOS pipe Mn1 is connected with the drain electrode of Mp1, the source ground of Mn1, and the drain electrode that NMOS manages Mn2 is connected with the drain electrode of Mp2, and the source ground of Mn2, the grid of Mn1 are connected to the bias voltage input vb of differential multiplier with after the grid of Mn2 is connected.Numerical control variable capacitance array CA1 is connected between the drain electrode of the I road in-phase input end ip of differential multiplier and Mp1, numerical control variable capacitance array CA2 is connected between the drain electrode of the Q road inverting input qn of differential multiplier and Mp2, after the control word input cb of CA1 and the control word input cb of CA2 are connected, be connected to the control word input csw of differential multiplier.RA1 is connected between the drain electrode of the Q road in-phase input end qp of differential multiplier and Mp1, and RA2 is connected between the drain electrode of the I road inverting input in of differential multiplier and Mp2.The inverting input in of OTA1 is connected with the drain electrode of Mp1, and the in-phase input end ip of OTA1 is connected with the drain electrode of Mp2, and the in-phase output end op of OTA1 is connected with the grid of Mp1, and the reversed-phase output on of OTA1 is connected with the grid of Mp2.

The advantages such as the differential multiplier of the present embodiment adopts the structure of Active RC, has dynamic range large, and is low in energy consumption; The electric capacity of numerical control variable capacitance array structure can be proofreaied and correct the RC time constant, can resist process deviation.

As shown in Figure 4, be the electrical block diagram of numerical control variable capacitance array in Fig. 3; The present embodiment numerical control variable capacitance array comprises four NMOS pipe, two inverters, two electric capacity and two resistance at least; The present embodiment describes as an example of eight NMOS manage, four inverters, four electric capacity and two resistance form numerical control variable capacitance array example.

Wherein, the source electrode of NMOS pipe M1, NMOS pipe M2, NMOS pipe M3, NMOS pipe M4 is connected with the first input end cp of numerical control variable capacitance array, and the drain electrode of NMOS pipe M5, NMOS pipe M6, NMOS pipe M7, NMOS pipe M8 is connected; The drain electrode of NMOS pipe M1 is connected with the source electrode of NMOS pipe M5, and the drain electrode of NMOS pipe M2 is connected with the source electrode of NMOS pipe M6, and the drain electrode of NMOS pipe M3 is connected with the source electrode of NMOS pipe M7, and the drain electrode of NMOS pipe M4 is connected with the source electrode of NMOS pipe M8; The grid of NMOS pipe M1 is connected with the primary input cb1 of control word, the grid of NMOS pipe M2 is connected with the deputy input cb2 of control word, the grid of NMOS pipe M3 is connected with the tertiary input cb3 of control word, and the grid of NMOS pipe M4 is connected with the input cb4 of the 4th of control word; The input of inverter INV1 is connected with the grid of NMOS pipe M1, the output of inverter INV1 is connected with the grid of NMOS pipe M5, the input of inverter INV2 is connected with the grid of NMOS pipe M2, the output of inverter INV2 is connected with the grid of NMOS pipe M6, the input of inverter INV3 is connected with the grid of NMOS pipe M3, the output of inverter INV3 is connected with the grid of NMOS pipe M7, the input of inverter INV4 is connected with the grid of NMOS pipe M4, and the output of inverter INV4 is connected with the grid of NMOS pipe M8.Capacitor C 1 is connected between the second input cn of the drain electrode of NMOS pipe M1 and numerical control variable capacitance array, capacitor C 2 is connected between the second input cn of the drain electrode of NMOS pipe M2 and numerical control variable capacitance array, capacitor C 3 is connected between the second input cn of the drain electrode of NMOS pipe M3 and numerical control variable capacitance array, and capacitor C 4 is connected between the second input cn of the drain electrode of NMOS pipe M4 and numerical control variable capacitance array.Resistance R 1 is connected between the drain electrode of power supply and NMOS pipe M5, and resistance R 2 is connected between the drain electrode and ground of NMOS pipe M5.

The operation principle of the numerical control variable capacitance array of the present embodiment is: by the resistance of resistance R 1 and R2 rationally is set, make the drain voltage of NMOS pipe M5, M6, M7 and M8 equal 1/2 of supply power voltage.When numerical control variable capacitance antenna array control word cb1, cb2, cb3 and cb4 equaled the high level of supply power voltage, NMOS managed M1, M2, M3 and M4 conducting, and M5, M6, M7 and M8 close, and at this moment capacitor C 1, C2, C3 and C4 all come into force; When numerical control variable capacitance antenna array control word cb1, cb2, cb3 and cb4 are low level, NMOS manages M5, M6, M7 and M8 conducting, this manages the drain voltage clamper of M1, M2, M3 and M4 at 1/2 of supply power voltage with NMOS, guarantee that M1, M2, M3 and M4 can end fully, at this moment C1, C2, C3 and C4 void in whole.Change by said method the adjusting that numerical control variable capacitance array realized in numerical control variable capacitance antenna array control word.The advantage of numerical control variable capacitance array of the present invention is the voltage clamping by auxiliary switch M5, M6, M7 and M8, makes switch M1, M2, M3 and M4 all can effectively close, and has guaranteed the accuracy of total capacitance value.The accuracy of total capacitance value for the logarithm output of logarithmic amplifier, helps to keep response speed and the ripple characteristics of output signal; For the feedback network of logarithmic amplifier, help cancellation of DC offset, help to keep the stability of feedback control loop.

As shown in Figure 5, be the electrical block diagram of load circuit in Fig. 2; The load circuit of the present embodiment comprises: seven NMOS pipes, four PMOS pipes, four resistance.

Wherein, the source electrode of PMOS pipe Mp1 is connected with the source electrode of PMOS pipe Mp2, the drain electrode of PMOS pipe Mp3 is connected with the source electrode of PMOS pipe Mp1, the source electrode of PMOS pipe Mp3 meets power vd D, the grid of PMOS pipe Mp4 is connected with the grid of PMOS pipe Mp3, the grid of PMOS pipe Mp4 is connected with drain electrode, and the source electrode of PMOS pipe Mp4 meets power vd D.the grid of NMOS pipe Mn1 is with after drain electrode is connected, be connected to the drain electrode of PMOS pipe Mp1, the grid of NMOS pipe Mn2 is with after drain electrode is connected, be connected to the drain electrode of PMOS pipe Mp2, the drain electrode of NMOS pipe Mn3 is connected with the drain electrode of PMOS pipe Mp4, after the drain electrode that the drain electrode of NMOS pipe Mn4 and NMOS manage Mn5 is connected, be connected to the end of oppisite phase ion of load circuit bidirectional port, after the drain electrode that the drain electrode of NMOS pipe Mn6 and NMOS manage Mn7 is connected, be connected to the in-phase end iop of load circuit bidirectional port, after the grid of the grid of NMOS pipe Mn4 and NMOS pipe Mn7 is connected, be connected to the grid of NMOS pipe Mn2, the grid of NMOS pipe Mn3, after the grid of the grid of NMOS pipe Mn5 and NMOS pipe Mn6 is connected, be connected to the bias voltage input vb of load circuit.The source electrode that the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of NMOS pipe Mn1, NMOS pipe Mn2, NMOS pipe Mn3, NMOS pipe Mn4, NMOS pipe Mn5, NMOS pipe Mn6 and NMOS the manage Mn7 rear ground connection that is connected.Resistance R 1 connects grid and the power vd D of Mp2, resistance R 2 connects grid and the ground of Mp2, the end of oppisite phase ion of the grid of resistance R 3 connection PMOS pipe Mp1 and the bidirectional port of load circuit, the in-phase end iop of the grid of resistance R 4 connection PMOS pipe Mp1 and the bidirectional port of load circuit.

As shown in Figure 6, be the electrical block diagram of low pass filter in Fig. 1; The low pass filter of the present embodiment is the Active RC structure, comprising: three operational amplifier OTA, six numerical control capacitor array CA and 14 electric resistance arrays.

Wherein, the in-phase output end op of operational amplifier OTA3 is connected with the reversed-phase output on of low pass filter, and the reversed-phase output on of OTA3 is connected with the in-phase output end op of low pass filter.electric resistance array R1 connects the in-phase input end ip of low pass filter and the inverting input in of OTA1, electric resistance array R2 connects the inverting input in of low pass filter and the in-phase input end ip of operational amplifier OTA1, electric resistance array R3 connects inverting input in and the in-phase output end op of OTA1, electric resistance array R4 connects in-phase input end ip and the reversed-phase output on of OTA1, electric resistance array R5 connects the in-phase output end op of OTA1 and the inverting input in of operational amplifier OTA2, electric resistance array R6 connects the reversed-phase output on of OTA1 and the in-phase input end ip of OTA2, electric resistance array R7 connects inverting input in and the in-phase output end op of OTA2, electric resistance array R8 connects in-phase input end ip and the reversed-phase output on of OTA2, electric resistance array R9 connects the in-phase output end op of OTA2 and the inverting input in of OTA3, electric resistance array R10 connects the reversed-phase output on of OTA2 and the in-phase input end ip of OTA3, electric resistance array R11 connects inverting input in and the in-phase output end op of OTA3, electric resistance array R12 connects in-phase input end ip and the reversed-phase output on of OTA3, electric resistance array R13 connects the reversed-phase output on of OTA3 and the inverting input in of OTA2, electric resistance array R14 connects the in-phase output end op of OTA3 and the in-phase input end ip of OTA2.Numerical control variable capacitance array CA1 connects inverting input in and the in-phase output end op of OTA1, numerical control variable capacitance array CA2 connects in-phase input end ip and the reversed-phase output on of OTA1, numerical control variable capacitance array CA3 connects inverting input in and the in-phase output end op of OTA2, numerical control variable capacitance array CA4 connects in-phase input end ip and the reversed-phase output on of OTA2, numerical control variable capacitance array CA5 connects inverting input in and the in-phase output end op of OTA3, and numerical control variable capacitance array CA6 connects in-phase input end ip and the reversed-phase output on of OTA3.After the control word input cb of control word input cb, the CA5 of control word input cb, the CA4 of control word input cb, the CA3 of control word input cb, the CA2 of CA1 and the control word input cb of CA6 are connected, be connected to the control word input fsw of low pass filter device.

The advantages such as the low pass filter of the present embodiment adopts the Active RC structure, has dynamic range large, and is low in energy consumption; The electric capacity of numerical control variable capacitance array structure can be proofreaied and correct the RC time constant, can resist process deviation.

As shown in Figure 7, be the electrical block diagram of differentiator in Fig. 1; The differentiator of the present embodiment comprises: two operational amplifier OTA, four numerical control variable capacitance array CA and eight variable resistor array RA.

wherein, the in-phase output end op of operational amplifier OTA1 is connected with the reversed-phase output on of differentiator, and the reversed-phase output on of OTA1 is connected with the in-phase output end op of differentiator, numerical control variable capacitance array CA1 connects inverting input in and the in-phase output end op of OTA1, numerical control variable capacitance array CA2 connects in-phase input end ip and the reversed-phase output on of OTA1, inverting input in and the in-phase output end op of numerical control variable capacitance array CA3 concatenation operation amplifier OTA2, numerical control variable capacitance array CA4 connects in-phase input end ip and the reversed-phase output on of OTA2, after the control word input cb of four numerical control variable capacitance arrays is connected, be connected to the control word input dfsw of differentiator, electric resistance array R1 is connected between the inverting input in of the in-phase input end ip of differentiator and OTA1, electric resistance array R2 is connected between the in-phase input end ip of the inverting input in of differentiator and OTA1, electric resistance array R3 is connected between the inverting input in and in-phase output end op of OTA1, electric resistance array R4 is connected between the in-phase input end ip and reversed-phase output on of OTA1, electric resistance array R5 is connected between the inverting input in of the in-phase output end op of OTA1 and OTA2, electric resistance array R6 is connected between the in-phase input end ip of the reversed-phase output on of OTA1 and OTA2, electric resistance array R7 is connected between the inverting input in of the reversed-phase output on of OTA2 and OTA1, electric resistance array R8 is connected between the in-phase input end ip of the in-phase output end op of OTA2 and OTA1.

As shown in Figure 8, be the electrical block diagram of hysteresis comparator in Fig. 1; The hysteresis comparator of the present embodiment comprises: six PMOS pipes, seven NMOS pipes, two electric resistance arrays and an inverter INV1.

wherein, the grid of PMOS pipe Mp1 is connected with the inverting input in of hysteresis comparator, the grid of PMOS pipe Mp2 is connected with the in-phase input end ip of hysteresis comparator, the source electrode of PMOS pipe Mp1 is connected with the source electrode of PMOS pipe Mp2, after the grid of PMOS pipe Mp3 and draining is connected, be connected to the grid of PMOS pipe Mp4, the drain electrode of PMOS pipe Mp5 is connected with the source electrode of PMOS pipe Mp1 and the source electrode of PMOS pipe Mp2, the source electrode of PMOS pipe Mp6 is connected with the drain electrode of PMOS pipe Mp5, the drain electrode of PMOS pipe Mp6 is connected with the grid of PMOS pipe Mp5, the source electrode of PMOS pipe Mp3, the source electrode of Mp4, after the source electrode of Mp5 is connected, be connected to power vd D.after the drain electrode of the grid of NMOS pipe Mn1 and NMOS pipe Mn2 is connected, be connected to the drain electrode of PMOS pipe Mp1, after the drain electrode of the grid of NMOS pipe Mn2 and NMOS pipe Mn1 is connected, be connected to the drain electrode of PMOS pipe Mp2, the grid of NMOS pipe Mn3 is with after drain electrode is connected, be connected to the grid of NMOS pipe Mn1, the grid of NMOS pipe Mn4 is with after drain electrode is connected, be connected to the grid of NMOS pipe Mn2, the grid of NMOS pipe Mn5 is connected with the drain electrode of NMOS pipe Mn3, the drain electrode of NMOS pipe Mn5 is connected with the drain electrode of PMOS pipe Mp3, the grid of NMOS pipe Mn6 is connected with the drain electrode of NMOS pipe Mn4, the drain electrode of NMOS pipe Mn6 is connected with the drain electrode of PMOS pipe Mp4, the grid of NMOS pipe Mn7 is connected with the bias voltage input cvb of hysteresis comparator, the drain electrode of NMOS pipe Mn7 is connected with the drain electrode of PMOS pipe Mp6, the source electrode of NMOS pipe Mn1, the source electrode of Mn2, the source electrode of Mn3, the source electrode of Mn4, the source electrode of Mn5, the source electrode of the Mn6 rear ground connection that is connected with the source electrode of Mn7.Electric resistance array RA1 connects the grid of power vd D and PMOS pipe Mp6, and electric resistance array RA2 connects grid and the ground of PMOS pipe Mp6.The input of inverter INV1 is connected with the drain electrode of NMOS pipe Mn6, and the output of INV1 is connected with the output out of hysteresis comparator.The input difference of the hysteresis comparator of the present embodiment is to Mp1, Mp2, and Mp5, Mp6 and Mn7 adopt the structure of the voltage follower (Fliped VoltageFollower is hereinafter to be referred as FVF) of upset.

The present embodiment adopts the mode of differentiator and hysteresis comparator combination, and can eliminate the error rate that frequency shift (FS) causes increases, and adds two limits can filter away high frequency noise in differentiator, and simple in structure, low in energy consumption, and dynamic range is large; Hysteresis comparator adopts the FVF structure, has advantages of that quiescent dissipation is very little.

As shown in Figure 9, be the electrical block diagram of FSK demodulating equipment embodiment two of the present invention; The present embodiment is from the different of embodiment one: the present embodiment also comprises: time constant correcting circuit 5, the Capacity control word output csw of time constant correcting circuit 5 and the control word input dsw of DEM1, the control word input fsw of LF2, and the control word input dfsw of DIF3 is connected.

As shown in figure 10, be the electrical block diagram of time constant correcting circuit in Fig. 9; The time constant correcting circuit 5 of the present embodiment comprises: bandgap source 51, digital circuit blocks 52, operational amplifier OTA53, operational amplifier OTA54, operational amplifier OTA55, operational amplifier OTA56, electric resistance array RA57, capacitor array CA58 and NMOS pipe M59, NMOS pipe M50.

Wherein, bandgap source 51 is used for providing reference voltage to the modules of time constant correcting circuit 5; Digital circuit blocks 52 is used for carrying out figure adjustment; Operational amplifier OTA53 and operational amplifier OTA54 are as amplifier, and operational amplifier OTA55 and operational amplifier OTA56 are as voltage comparator.The in-phase input end ip of in-phase input end ip, the OTA55 of in-phase input end ip, the OTA54 of operational amplifier OTA53 and the inverting input in of OTA56 are connected with bandgap source 51; Electric resistance array RA57 is connected between the inverting input in and ground of operational amplifier OTA53; Capacitor array CA58 is connected between the inverting input in and output out of operational amplifier OTA54, and the control word input cb of CA58 is connected to the output csw of time constant correcting circuit 5 with after digital circuit blocks 52 is connected; The grid of NMOS pipe M59 is connected with the output out of operational amplifier OTA53; The drain electrode of NMOS pipe M59 is connected with the inverting input in of operational amplifier OTA54, and the source electrode of NMOS pipe M59 is connected with the inverting input in of operational amplifier OTA53; NMOS pipe M50 is as switch, the source electrode of NMOS pipe M50 is connected with the inverting input in of operational amplifier OTA54, the drain electrode of NMOS pipe M50 is connected with the output out of operational amplifier OTA54, and the grid of NMOS pipe M50 is connected with digital circuit blocks 52.

the operation principle of the time constant correcting circuit of the present embodiment is: digital circuit blocks 52 produces clock control NMOS pipe M50, and initial condition is that M50 turn-offs, fixing voltage of inverting input of OTA53 is given by operational amplifier OTA53 in bandgap source 51, and this just produces an electric current in electric resistance array RA57, electric current charges to capacitor array CA58, the result of charging determines the output voltage values of OTA54, this magnitude of voltage with make comparisons as the in-phase input end voltage of the operational amplifier OTA55 of voltage comparator with as the anti-phase input terminal voltage of the operational amplifier OTA56 of voltage comparator, result relatively outputs to digital circuit blocks 52 by OTA55 and OTA56, digital circuit blocks 52 is adjusted the capacitance of capacitor array CA58 according to result relatively, if OTA55 output is low, OTA56 output is high, the output voltage values that OTA54 is described is too high, adjust variable capacitance antenna array control word to change total capacitance value, to reduce the output voltage of the rear OTA54 of charging next time, if it is high that OTA55 exports, OTA56 output is low, illustrates that the output voltage values of OTA54 is too low, adjusts variable capacitance antenna array control word to change total capacitance value, to increase the output voltage of the rear OTA54 of charging next time, if OTA55 output is high, OTA56 output is high, illustrates that the output voltage values of OTA54 is just right, keeps variable capacitance antenna array control word constant to keep total capacitance value, control word csw after also adjusting simultaneously delivers to output.When the resistance in circuit or electric capacity because when technique, temperature generation deviation, the deviation of same percentage occurs in the electric resistance array RA57 in time constant correcting circuit 5 and capacitor array CA58, after charging, the output voltage of OTA54 changes, the Output rusults of OTA55 and OTA56 also changes accordingly, and digital circuit blocks 52 changes the capacitance of CA58 according to the variation of the Output rusults of OTA55 and OTA56.Charge cycle ground carries out, and after each charging finishes, digital circuit blocks 52 is all opened switch M50, makes the CA58 discharge, and then next cycle charges next time again.Charging and so forth, constantly adjust the capacitance of capacitor array CA58, until the output voltage of OTA54 is between the anti-phase input terminal voltage of the in-phase input end voltage of OTA55 and OTA56 the time, correction stops, the control word csw of this moment output is used for controlling simultaneously the capacitor array in the low pass filter of capacitor array in the low pass filter of logarithm output and feedback network, therefore joining day constant correcting circuit can be realized constant correction time in the FSK demodulating equipment, reaches the purpose that improves anti-PVT deviation ability.

As can be seen from the above embodiments, the embodiment of the present invention by adopting the Active RC structure demodulator and the structure of low pass filter combination carry out demodulation, have simple in structurely, dynamic range is large, advantage low in energy consumption; And, carry out data decision by the differentiator of employing Active RC structure and the structure of hysteresis comparator combination, can be good at anti-frequency shift (FS), and low in energy consumption, dynamic range is large; Further, the embodiment of the present invention is by the time constant with the differentiator of the low pass filter of a cover time constant correcting circuit correction demodulator, Active RC structure and Active RC structure, makes the FSK demodulating equipment of the present embodiment reach anti-process deviation, the beneficial effect that low in energy consumption and cost is low.

The above is only the preferred embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and modification, these improve and modification also should be considered as protection scope of the present invention.

Claims

1. a FSK demodulating equipment, is characterized in that, comprising:

Hysteresis comparator, the differential input end of described hysteresis comparator is connected with the difference output end of described differentiator, the bias voltage input of described hysteresis comparator is connected with the second bias voltage input of described FSK demodulating equipment, and the output of described hysteresis comparator is connected with the output of described FSK demodulating equipment;

Also comprise: the time constant correcting circuit, the Capacity control word output of described time constant correcting circuit is connected with the control word input of the control word input of described demodulator, low pass filter and the control word input of differentiator.

2. FSK demodulating equipment as claimed in claim 1, is characterized in that, described demodulator comprises:

3. FSK demodulating equipment as claimed in claim 2, is characterized in that, described differential multiplier comprises:

4. FSK demodulating equipment as claimed in claim 2, is characterized in that, described load circuit comprises:

Four PMOS pipes, the source electrode of the one PMOS pipe is connected with the source electrode of the 2nd PMOS pipe, the drain electrode of the 3rd PMOS pipe is connected to the source electrode of a described PMOS pipe, the source electrode of described the 3rd PMOS pipe connects power supply, the grid of the 4th PMOS pipe is connected to the grid of described the 3rd PMOS pipe, the grid of described the 4th PMOS pipe is connected with the drain electrode of the 4th PMOS pipe, and the source electrode of described the 4th PMOS pipe connects power supply;

5. FSK demodulating equipment as claimed in claim 1, is characterized in that, described low pass filter comprises:

Three operational amplifiers and 14 electric resistance arrays, the inverting input of the first operational amplifier is connected by the first electric resistance array with the in-phase input end of described low pass filter, and the in-phase input end of described the first operational amplifier is connected by the second electric resistance array with the inverting input of described low pass filter; The inverting input of the second operational amplifier is connected by the 5th electric resistance array with the in-phase output end of described the first operational amplifier, and the in-phase input end of described the second operational amplifier is connected by the 6th electric resistance array with the reversed-phase output of described the first operational amplifier; The inverting input of the 3rd operational amplifier is connected by the in-phase output end of the 9th electric resistance array with described the second operational amplifier, the in-phase input end of described the 3rd operational amplifier is connected by the reversed-phase output of the tenth electric resistance array with described the second operational amplifier, the in-phase output end of described the 3rd operational amplifier is connected with the reversed-phase output of described low pass filter, and the reversed-phase output of described the 3rd operational amplifier is connected with the in-phase output end of described low pass filter;

6. FSK demodulating equipment as claimed in claim 1, is characterized in that, described differentiator is the Active RC structure, comprising:

7. FSK demodulating equipment as claimed in claim 1, is characterized in that, described hysteresis comparator is the voltage follower structure of upset, comprising:

8. FSK demodulating equipment as claimed in claim 1, is characterized in that, described time constant correcting circuit comprises:

A digital circuit blocks is used for carrying out figure adjustment;

9. as claim 3,5,6 or 8 described FSK demodulating equipments, it is characterized in that, described numerical control variable capacitance array comprises:

The NMOS pipe of at least four numerical control variable capacitance arrays, the source electrode of the source electrode of a NMOS pipe, the 2nd NMOS pipe is connected with the first end of described numerical control variable capacitance array; The drain electrode of the 3rd NMOS pipe is connected with the drain electrode of the 4th NMOS pipe, the drain electrode of a described NMOS pipe is connected with the source electrode of the 3rd NMOS pipe, the drain electrode of described the 2nd NMOS pipe is connected with the source electrode of the 4th NMOS pipe, the grid of a described NMOS pipe is connected with the primary input of control word, and the grid of described the 2nd NMOS pipe is connected with the deputy input of control word;

At least two inverters, the input of the first inverter is connected with the grid of a NMOS pipe, and the output of described the first inverter is connected with the grid of the 3rd NMOS pipe; The input of the second inverter is connected with the grid of the 2nd NMOS pipe, and the output of described the second inverter is connected with the grid of the 4th NMOS pipe;