CN102045159A - Decryption processing method and device thereof - Google Patents
Decryption processing method and device thereof Download PDFInfo
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- CN102045159A CN102045159A CN 201010614916 CN201010614916A CN102045159A CN 102045159 A CN102045159 A CN 102045159A CN 201010614916 CN201010614916 CN 201010614916 CN 201010614916 A CN201010614916 A CN 201010614916A CN 102045159 A CN102045159 A CN 102045159A
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Abstract
The invention discloses a decryption processing method and a device thereof. Aiming at the encrypted data of a current common public algorithm, a secret key combination to be decrypted is split, and the decryption tasks are assigned to a plurality of computing units and are decrypted. The method and the device disclosed by the invention have the advantages that through realizing the decryption computation on parallelly-operated high-speed hardware devices and processing and occupying all resources in an instruction set mode, the efficiency of the decryption processing is improved.
Description
Technical field
The invention belongs to the decryption processing field, be specifically related to a kind of decipher processing method and decryption processing apparatus thereof that the public encryption algorithm comprises the enciphered data of MD5, SHA, DES, RSA that can be applied to use always.
Background technology
The development for many years of encryption and decryption field, the secret square tube of transmission is crossed the time of strengthening decrypting process, the difficulty that space cost increases deciphering, and the secret side of intercepting also increases secret unlocked probability by the efficient of raising decrypted program and the science of decryption method on network.But most cryptographic algorithm can't be finished deciphering in the short time by individual PC or small server, and this has increased the fail safe of message simultaneously with regard to for the decryption work of current mission critical has caused obstacle encryption one side.
Simultaneously, cryptographic algorithm has been passed through years of development, has been tending towards ripe and stable day by day, and wherein available algorithm leak is also fewer and feweri.Therefore, the pure Brute Force means that all can carry out password cracking without any need for the algorithm leak just become a kind of general deciphering means.And the performance bottleneck of Brute Force depends primarily on the speed of service of computer, and the single computer of the many employings of existing Brute Force carries out serial and cracks, and this has just limited the efficient and the performance of Brute Force greatly.By as can be known to the analysis of password encryption algorithm and permutations of code combination, the password scope is carried out the fractionation of certain rule after, can promote the performance of Brute Force password greatly.
Summary of the invention
What the present invention is directed to cryptographic algorithm commonly used cracks an efficient difficult problem, has proposed a kind of method and system thereof that utilizes hardware device to carry out the task that cracks, and has realized that the high speed of cryptographic algorithm commonly used cracks.This method realizes cracks efficient and can reach 100 times of the strong server catalyst Catalyst speed of current I ntel will.
In a first aspect of the present invention, a kind of decipher processing method of high speed is provided, comprise the following steps:
1) input enciphered data and cryptographic algorithm thereof;
2) cipher key combinations that will be to be cracked splits, and the task of cracking is divided into many parts distributes to a plurality of arithmetic elements respectively;
3) a plurality of arithmetic elements are parallel carries out key and cracks, and stops to crack when one of them arithmetic element cracks successfully;
4) decrypted result is exported.
Above-mentioned steps 1) enciphered data described in is meant that data receiver carries out result after the encryption according to certain algorithm with clear data; Described cryptographic algorithm is meant public encryption algorithm commonly used, for example DES, SHA, MD5, RSA scheduling algorithm.
Above-mentioned steps 2) by the analysis to cryptographic algorithm and permutations of code combination, splitting afterwards according to certain rule the password scope, distribution cracks task.For example, password rule to be cracked is ten pure digi-tal, and can be split as following two kinds of password combination: (1) first bit digital is the combination of 1,2,3,4 or 5 and nine pure digi-tal; (2) first bit digital are combinations of 6,7,8,9 or 0 and nine pure digi-tal.These two kinds of password combination are assigned to respectively on two arithmetic elements crack.
Above-mentioned steps 3) arithmetic element cracks the decipherment algorithm that uses when handling and is determined the decipherment algorithm that different cryptographic algorithm is corresponding different by the cryptographic algorithm of importing.
Above-mentioned steps 4) outgoing position of decrypted result can dispose, and is specified by the user.
In a second aspect of the present invention, a kind of decryption processing apparatus is provided, comprise control unit, arithmetic element, input unit and output unit, wherein: input unit is used to obtain enciphered data and cryptographic algorithm information, and sends these information to control unit; Control unit splits cipher key combinations according to cryptographic algorithm, will crack Task Distribution and give a plurality of arithmetic elements; The corresponding decipherment algorithm of a plurality of arithmetic element utilizations walks abreast and is decrypted processing, and decrypted result is sent to control unit; Output unit is from control unit receiving and deciphering result and output.
Above-mentioned control unit is responsible for control, coordination, the scheduling of whole decryption processing apparatus inside, can be the server of a stable performance, as the Linux server.
Above-mentioned arithmetic element is made up of various decipherment algorithm corresponding hardware processing modules commonly used and key structure module, is responsible for the processing of actual core decryption work.Which hardware processing module is arithmetic element specifically call is determined by algorithm, the hardware processing module that different algorithms is corresponding different.Described decipherment algorithm commonly used is decipherment algorithms such as SHA, MD5, DES, RSA for example.Described arithmetic element can be the server that has high performance computation processor or high-performance association processing hardware accelerator card.
Above-mentioned input unit is responsible for receiving other information of message data, cryptographic algorithm and user's input of encryption, and sends these information to control unit.Described input unit is the unit that a reception cracks task, and the data of reception can be enciphered datas such as the network packet of encrypting, encrypt file.
Above-mentioned output unit is controlled by control unit, is responsible for decrypted result is exported.Described output unit can be memory device or the database that a storage cracks the result, even can be the PC terminal that a demonstration cracks the result.
Preferably communicate between above-mentioned each unit by Transmission Control Protocol.
The invention has the beneficial effects as follows:
Traditional decryption method utilizes software program and PC or small server to finish decryption work, at the enciphered data of current public algorithm commonly used, can not meet consumers' demand far away.The present invention calculates on the hardware device that is implemented in the high-speed parallel operation by deciphering, and handles in the instruction set mode, and takies whole resources, has improved the efficient of decryption processing.Decipher at original DES that carries out on strong 5405 server catalyst Catalysts by intel will, key is that numeral+lowercase amounts to 6 characters, ciphertext length is unfixing, then deciphering time average is 1 day (24 hours), realize in the present invention then foreshortening within 15 minutes under the similarity condition, speed has improved 100 times.
Description of drawings
Fig. 1 is the structure chart of decryption processing apparatus of the present invention.
Fig. 2 is the flow chart of decipher processing method of the present invention.
Embodiment
Be example with the DES deciphering below, the present invention is described in further detail.
Got access to the message data of a plurality of employing public encryption algorithm for encryption in the present embodiment, and the cryptographic algorithm of known each enciphered data correspondence.Decryption processing apparatus comprises a control unit, input unit, a plurality of parallel arithmetic element and an output unit as shown in Figure 1, and the deciphering implementation process specifically comprises the steps: as shown in Figure 2
(1) input unit read the user manually input or text file format des encryption message data and corresponding cryptographic algorithm information " DES ";
(2) control unit sends to arithmetic element with enciphered data and the algorithm information that reads in by Transmission Control Protocol;
(3) arithmetic element is called the DES deciphering module of this inside, unit according to " DES " algorithm of input, and the key structure module of calling this inside, unit is carried out the DES deciphering;
(4) after the arithmetic element deciphering is finished, by Transmission Control Protocol notice control unit; And the key that obtains during with successful decryption and corresponding DES clear data send to control unit, maybe will decipher failure and send to main control computer;
(5) control unit obtains the decrypted result of arithmetic element, sends it to output unit and outputs in terminal screen or the text.
Arrive this, high-speed parallel decryption processing apparatus decrypting process is implemented to finish, what the core processing part of whole process---arithmetic element adopted is the hardware device of high-speed parallel, can data be distributed to according to different algorithms and adopt the pipeline system parallel processing in each simultaneous resource, reach the purpose that significantly improves deciphering speed.
Claims (9)
1. a decipher processing method comprises the following steps:
1) input enciphered data and cryptographic algorithm thereof;
2) cipher key combinations that will be to be cracked splits, and is divided into many parts and distributes to a plurality of arithmetic elements respectively cracking task;
3) a plurality of arithmetic elements are parallel carries out key and cracks, and stops to crack when one of them arithmetic element cracks successfully;
4) decrypted result is exported.
2. decipher processing method as claimed in claim 1 is characterized in that, the described cryptographic algorithm of step 1) is DES, SHA, MD5 or RSA Algorithm.
3. a decryption processing apparatus comprises control unit, arithmetic element, input unit and output unit, and wherein: input unit is used to obtain enciphered data and cryptographic algorithm information, and sends these information to control unit; Control unit splits cipher key combinations according to cryptographic algorithm, the task of cracking is divided into many parts distributes to a plurality of arithmetic elements respectively; The corresponding decipherment algorithm of a plurality of arithmetic element utilizations walks abreast and is decrypted processing, and decrypted result is sent to control unit; Output unit is from control unit receiving and deciphering result and output.
4. decryption processing apparatus as claimed in claim 3 is characterized in that, described control unit is a server.
5. decryption processing apparatus as claimed in claim 3 is characterized in that, form separately by corresponding hardware processing module and key structure module by different decipherment algorithms for described arithmetic element.
6. decryption processing apparatus as claimed in claim 5 is characterized in that, described decipherment algorithm is SHA, MD5, DES or RSA Algorithm.
7. decryption processing apparatus as claimed in claim 3 is characterized in that, described arithmetic element is the server that has high performance computation processor or high-performance association processing hardware accelerator card.
8. decryption processing apparatus as claimed in claim 3 is characterized in that, described output unit is memory device or the database that a storage cracks the result, or demonstration cracks result's PC terminal.
9. decryption processing apparatus as claimed in claim 3 is characterized in that, communicates by Transmission Control Protocol between each unit.
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| CN 201010614916 CN102045159A (en) | 2010-12-30 | 2010-12-30 | Decryption processing method and device thereof |
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| CN 201010614916 CN102045159A (en) | 2010-12-30 | 2010-12-30 | Decryption processing method and device thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102983967A (en) * | 2012-12-06 | 2013-03-20 | 厦门市美亚柏科信息股份有限公司 | Quick traversal algorithm and device for complicated password |
| CN103944713A (en) * | 2014-03-31 | 2014-07-23 | 中国航天时代电子公司 | Binary cipher decoder decoding method based on optimal enumeration algorithm |
| CN104077542A (en) * | 2014-07-10 | 2014-10-01 | 南威软件股份有限公司 | Password cracking system and method |
| CN105262584A (en) * | 2015-09-08 | 2016-01-20 | 厦门市美亚柏科信息股份有限公司 | Distributed password recovery method and system |
| CN106341404A (en) * | 2016-09-09 | 2017-01-18 | 西安工程大学 | IPSec VPN system based on many-core processor and encryption and decryption processing method |
| CN106961323A (en) * | 2017-05-18 | 2017-07-18 | 桀安信息安全技术（上海）有限公司 | A kind of secret key decryption board, device, system and processing method |
| CN111212419A (en) * | 2019-12-17 | 2020-05-29 | 北京威努特技术有限公司 | Wireless password detection method |
| CN116208317A (en) * | 2023-05-05 | 2023-06-02 | 上海芯联芯智能科技有限公司 | Method for resisting side channel attack and encryption and decryption device |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102983967A (en) * | 2012-12-06 | 2013-03-20 | 厦门市美亚柏科信息股份有限公司 | Quick traversal algorithm and device for complicated password |
| CN102983967B (en) * | 2012-12-06 | 2015-09-02 | 厦门市美亚柏科信息股份有限公司 | The complicated quick ergodic algorithm of password and device |
| CN103944713A (en) * | 2014-03-31 | 2014-07-23 | 中国航天时代电子公司 | Binary cipher decoder decoding method based on optimal enumeration algorithm |
| CN103944713B (en) * | 2014-03-31 | 2017-10-13 | 中国航天时代电子公司 | A kind of binary coded decoder coding/decoding method based on optimization enumeration |
| CN104077542A (en) * | 2014-07-10 | 2014-10-01 | 南威软件股份有限公司 | Password cracking system and method |
| CN105262584A (en) * | 2015-09-08 | 2016-01-20 | 厦门市美亚柏科信息股份有限公司 | Distributed password recovery method and system |
| CN105262584B (en) * | 2015-09-08 | 2018-09-07 | 厦门市美亚柏科信息股份有限公司 | Distribution routing algorithm restoration methods and system |
| CN106341404A (en) * | 2016-09-09 | 2017-01-18 | 西安工程大学 | IPSec VPN system based on many-core processor and encryption and decryption processing method |
| CN106961323A (en) * | 2017-05-18 | 2017-07-18 | 桀安信息安全技术（上海）有限公司 | A kind of secret key decryption board, device, system and processing method |
| CN111212419A (en) * | 2019-12-17 | 2020-05-29 | 北京威努特技术有限公司 | Wireless password detection method |
| CN116208317A (en) * | 2023-05-05 | 2023-06-02 | 上海芯联芯智能科技有限公司 | Method for resisting side channel attack and encryption and decryption device |
| CN116208317B (en) * | 2023-05-05 | 2023-07-07 | 上海芯联芯智能科技有限公司 | Method for resisting side channel attack and encryption and decryption device |
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Application publication date: 20110504 |