CN102034807B - Method and device for protecting grid electrode - Google Patents
Method and device for protecting grid electrode Download PDFInfo
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- CN102034807B CN102034807B CN 200910196546 CN200910196546A CN102034807B CN 102034807 B CN102034807 B CN 102034807B CN 200910196546 CN200910196546 CN 200910196546 CN 200910196546 A CN200910196546 A CN 200910196546A CN 102034807 B CN102034807 B CN 102034807B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
The invention discloses a device for protecting a grid electrode, comprising a field effect transistor MOS (Metal Oxide Semiconductor), a first diode, a second diode, first metal wires, a first bonding pad and a second bonding pad, wherein when the device is in an initial state, a grid electrode of the MOS is respectively connected to a first N pole of the first diode and a second P pole of the second diode through the first metal wires; a first P pole of the first diode is grounded; a second N pole of the second diode is grounded; and when the device is in an ending state, the first bonding pad is connected with the grid electrode of the MOS, the second bonding pad is simultaneously connected with the first N pole of the first diode and the second P pole of the second diode, voltage is applied between the first bonding pad and the second bonding pad and the metal wire connected with the MOS and the first diode in the first metal wires is fused. Meanwhile, the invention also discloses a method for protecting the grid electrode. By adopting the method and device, the damage of the antenna effect on the grid electrode can be avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of gate protection method and apparatus.
Background technology
Along with the extensive use of electronic equipment, semi-conductive manufacturing process has obtained development at full speed, in semi-conductive manufacturing process; When to metal level or dielectric layer etching, repeatedly relate to plasma etch process, under normal circumstances; Plasma is electric neutrality, yet, in etching process; Sometimes plasma abnormal discharge can produce free charge, and a large amount of free charge flocks together and will produce electric current.When the dielectric layer of FET (MOS) top or metal level are carried out etching; The electric current that produces owing to plasma abnormal discharge can flow to grid and grid is caused damage along the metal interconnecting wires of grid top; Thereby the reliability of MOS even entire chip and life-span are seriously reduced; Wherein, metal interconnecting wires is the metal connecting path that the metal of filling in the through hole of the metal wire that forms after the metal level etching and dielectric layer is formed.The electric current that we produce plasma abnormal discharge is called antenna effect to the damage phenomenon of grid, is referred to as plasma again and causes grid damage (PID).
For gate protection device of the prior art is clearly explained, at first the principle of gate protection device of the prior art is introduced.
Fig. 1 is the schematic diagram of gate protection device of the prior art; As shown in Figure 1, the N utmost point of first diode 11 links to each other with the grid of MOS 12, and the N utmost point of first diode 11 is connected to first pad 13 simultaneously; The P utmost point ground connection of first diode, the grid of MOS 12 also link to each other with first pad 13.The figure cathetus is a metal interconnecting wires; When the metal level etching being formed metal wire or the dielectric layer etching is formed through hole; Plasma abnormal discharge and the free charge that produces can be directed to the earth along the metal interconnecting wires and first diode 11, so plasma abnormal discharge and the free charge that produces that is to say with regard to not assembling for electric current causes damage to the grid of MOS 12; First diode 11 is equivalent to the protection device of MOS 12; The grid of MOS 12 is connected with first pad 13, and first pad 13 is last formation in this device, is used for to MOS 12 operating voltage being provided through first pad 13.
Fig. 2 is the sectional structure chart of the embodiment of gate protection device of the prior art; As shown in Figure 2, this device comprises: MOS 12, first diode 11, first metal wire 301 and first pad 13, wherein; The grid 105 of MOS 12 is connected to a N utmost point 107 of first diode 11 through first metal wire 301; And a P utmost point 101 ground connection (scheming not shown) of first diode 11, first pad 13 links to each other with the grid 105 of MOS 12, and being used for provides operating voltage to the grid 105 of MOS 12.
Below in conjunction with Fig. 2 the formation method of gate protection device in the prior art is introduced, as shown in Figure 2, the formation method of gate protection device may further comprise the steps in the prior art:
Step 1; One substrate 100 is provided; Adopt depositing operation, etch process and ion implantation technology to form MOS 12; Wherein, MOS 12 comprises: drain electrode 102, source electrode 103, gate oxide 104, grid 105 and side wall layer 106, and we will be positioned at the grid 105 on substrate 100 surfaces and the gate oxide 104 of grid 105 belows is called grid structure usually; Adopt ion implantation technology to form first diode 11, wherein first diode 11 comprises a N utmost point 107 and a P utmost point 101, and makes a P utmost point 101 ground connection (scheming not shown) of the diode of winning.
Step 2; At substrate 100 surface depositions first dielectric layer 201; And adopt etch process on the N utmost point 107 of the grid 105 of MOS12 and first diode 11, to be formed for the follow-up first metal interconnected through hole 202 and second through hole 203 of carrying out respectively; And adopt depositing operation in first through hole 202 and second through hole 203, to fill metal; The metal of being filled can be copper or tungsten, adopts the surface of cmp (CMP) technology with metal grinding to the first dielectric layer 201 in first through hole 202 and second through hole 203 at last.
Step 3; Adopt depositing operation on first dielectric layer 201, to form the first metal layer, and adopt etch process on the first metal layer, to form groove, constitute first metal wire 301 without etched metal; Wherein, There is first metal wire 301 to connect between the MOS 12 and first diode 11, that is to say that the MOS 12 and first diode 11 interconnect at the first metal layer.
Step 4; Adopt depositing operation to form second dielectric layer 401; And adopt second dielectric layer 401 of etch process on the MOS 12 and first diode 11 to form third through-hole 402 and fourth hole 403 respectively; And adopting depositing operation in third through-hole 402 and fourth hole 403, to fill metal, the metal of being filled can be copper or tungsten, adopts the surface of CMP technology with metal grinding to the second dielectric layer 401 in third through-hole 402 and the fourth hole 403 at last.
Step 5; Adopt depositing operation to form second metal level on second dielectric layer, 401 surfaces; And adopt etch process on second metal level, to form groove; Constitute second metal wire 501 without etched metal, wherein, the MOS 12 and first diode 11 second metal wire 501 on second metal level does not interconnect.
Step 6; Adopt depositing operation to form the 3rd dielectric layer 601; And form fifth hole 602 in the 3rd dielectric layer 601 of employing etch process on MOS 12; And adopt depositing operation in fifth hole 602, to fill metal, the metal of being filled can be copper or tungsten, adopt at last CMP technology with in the fifth hole 602 the surface of metal grinding to the three dielectric layers 601.
Step 7; Adopt the surface deposition metallic aluminium of depositing operation, and adopt three dielectric layer 601 surfaces of etch process on MOS 12 to form first pad 13, wherein at the 3rd dielectric layer 601; First pad 13 forms metal interconnected with metal in the fifth hole 602 on fifth hole 602.
Shown in the arrow among Fig. 2, when to the metal level of MOS 12 and first diode, 11 tops or dielectric layer etching, if plasma abnormal discharge produces electric charge, then electric charge can flow to the earth along the direction of dotted line.And first pad 13 is last formation in this device, after first pad 13 forms; Can to MOS 12 operating voltage be provided through first pad 13; With driven MOS 12 operate as normal, because of operating voltage is a positive voltage, so when MOS 12 work; First diode 11 is in cut-off state, and the operate as normal of 11 couples of MOS 12 of first diode has no influence.
Need to prove that present embodiment is to be that example describes with the semiconductor structure that comprises two metal layers, in practical application, the number of the metal level that semiconductor structure comprises is decided as required, but the common metal layer is much larger than two-layer.
So far, this flow process finishes.
It is thus clear that, in the prior art, because the N utmost point of first diode 11 links to each other with the grid 105 of first pad 13 and MOS 12 respectively; The P utmost point ground connection of first diode 11 when plasma abnormal discharge, can produce free positive charge; Also can produce free negative electrical charge, negative electrical charge can be through first diode 11 the earth that leads, yet; Positive charge can't be through first diode, 11 guiding the earth; Like this, a large amount of positive charges flocks together and also can produce electric current and the grid 105 of MOS 12 is caused damage, can't avoid the damage of antenna effect to grid 105.
Summary of the invention
In view of this, the present invention provides a kind of gate protection method and apparatus, can avoid the damage of antenna effect to grid.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of gate protection device, this device comprises: FET MOS, first diode, second diode, first metal wire, first pad and second pad; Wherein,
When initial condition, the grid of MOS is connected to a N utmost point of first diode and the 2nd P utmost point of second diode respectively through first metal wire, and a P utmost point ground connection of first diode, the 2nd N utmost point ground connection of second diode;
When state of termination; First pad links to each other with the grid of MOS; Second pad extremely links to each other with a N utmost point of first diode and the 2nd P of second diode simultaneously, between first pad and second pad, is applied with voltage, connects the metal wire fusing of the MOS and first diode in first metal wire.
When in state of termination, the current density on first metal wire is greater than 10000000 amperes every square centimeter.
The width of the metal wire of the connection MOS and first diode is more than or equal to 0.09 and smaller or equal to 0.2 micron in first metal wire.
A kind of gate protection method, this method comprises:
When initial condition, the grid of MOS is connected to a N utmost point of first diode and the 2nd P utmost point of second diode respectively through first metal wire, and with a P utmost point ground connection of first diode, with the 2nd N utmost point ground connection of second diode;
When state of termination; First pad is linked to each other with the grid of MOS; Second pad is extremely linked to each other with a N utmost point of first diode and the 2nd P of second diode simultaneously; And between first pad and second pad, apply voltage, make the metal wire fusing that connects the MOS and first diode in the metal wire of winning.
When in state of termination, the current density on first metal wire is greater than 10000000 amperes every square centimeter.
The width of the metal wire of the connection MOS and first diode is more than or equal to 0.09 and smaller or equal to 0.2 micron in first metal wire.
Visible by above-mentioned technical scheme; When initial condition; The grid of MOS is connected to a N utmost point of first diode and the 2nd P utmost point of second diode respectively through first metal wire, and with a P utmost point ground connection of first diode, with the 2nd N utmost point ground connection of second diode; When state of termination; First pad is linked to each other with the grid of MOS, second pad is extremely linked to each other with a N utmost point of first diode and the 2nd P of second diode simultaneously, and between first pad and second pad, apply voltage; Make the metal wire fusing that connects the MOS and first diode in the metal wire of winning; Like this, the positive charge that plasma abnormal discharge produces can be directed to the earth from second diode, and the negative electrical charge that plasma abnormal discharge produces can be directed to the earth from first diode; The electric current that can avoid the plasma paradoxical discharge and produce flows to grid along the metal interconnecting wires of the grid top of MOS, thereby avoids the damage of antenna effect to grid.
Description of drawings
Fig. 1 is the schematic diagram of gate protection device of the prior art.
Fig. 2 is the sectional structure chart of the embodiment of gate protection device of the prior art.
Fig. 3 is the schematic diagram of gate protection device provided by the present invention.
Fig. 4 is the sectional structure chart of the embodiment of gate protection device provided by the present invention.
Fig. 5 is the flow chart of the embodiment of gate protection method provided by the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
For gate protection device provided by the present invention is clearly explained, at first the principle of gate protection device provided by the present invention is introduced.
Fig. 3 is the schematic diagram of gate protection device provided by the present invention; As shown in Figure 3; When in initial condition, the P utmost point ground connection of first diode 11, the N utmost point ground connection of second diode 14; The N utmost point of first diode 11 extremely links to each other with the P of second diode 14; The P utmost point of the N utmost point of first diode 11 and second diode 14 links to each other with second pad 16 simultaneously, and the P utmost point that the P utmost point of the N utmost point of first diode 11 and second diode 14 also is connected to the N utmost point and second diode 14 of first pad, 13, the first diodes 11 through fuse 15 simultaneously also is connected to the grid of MOS 12 simultaneously through fuse 15; When in state of termination, between first pad 13 and second pad 16, apply voltage, make fuse 15 fusing.
Said initial condition is meant the formation stage of metal interconnecting wires, and figure is metal interconnecting wires shown in the cathetus, and metal interconnecting wires is the metal connecting path of the metal composition of filling in the through hole of the metal wire that forms after the metal level etching and dielectric layer; After said state of termination is meant that metal interconnecting wires forms, the formation stage of first pad 13 and second pad 16.
Fig. 4 is the sectional structure chart of the embodiment of gate protection device provided by the present invention; As shown in Figure 4; This device comprises: MOS 12, first diode 11, second diode 14, first metal wire 301, first pad 13 and second pad 16; Wherein, when in initial condition, the grid 105 of MOS 12 is connected to a N utmost point 107 of first diode 11 and the 2nd P utmost point 109 of second diode 14 respectively through first metal wire 301; And a P utmost point 101 ground connection of first diode 11, the 2nd N utmost point 110 ground connection of second diode 14; When in state of termination; First pad 13 links to each other with the grid 105 of MOS 12; Second pad 16 links to each other with a N utmost point 107 of first diode 11 and the 2nd P utmost point 109 of second diode 14 simultaneously; Between first pad 13 and second pad 16, be applied with voltage, the metal wire that connects the MOS 12 and first diode 11 in first metal wire 301 is fused.
The normal width c of metal wire is greater than 5 microns; And in the present invention, when in state of termination, in order under the prerequisite of big voltage, the metal wire 301 of winning to be fused; Therefore the width that connects length in the MOS 12 and first diode 11 in first metal wire 301 and be the metal wire of b is set to a; Wherein, b is 10 microns to 20 microns, and the scope of a is more than or equal to 0.09 and smaller or equal to 0.2 micron.Need to prove that the length in first metal wire 301 in the connection MOS 12 and first diode 11 is that the metal wire of b is equivalent to fuse shown in Figure 3 15, the essence of the two is consistent, and in practical application, fuse 15 is thinner metal wire.
In practical application; If the material that first metal wire 301 adopts is different; The resistance of first metal wire 301 is also different, and therefore, the concrete numerical value of the voltage that is applied between first pad 13 and second pad 16 is determined on a case-by-case basis; As long as make current density, J＞10000000 ampere every square centimeter flow through first metal wire 301, the metal wire that connects the MOS 12 and first diode 11 will fuse.
Carry out detailed explanation for formation method, the formation method of gate protection device among the present invention is introduced below in conjunction with Fig. 4 to gate protection device provided by the present invention.
The formation method of gate protection device may further comprise the steps in the prior art:
Step 1; One substrate 100 is provided; Adopt depositing operation, etch process and ion implantation technology to form MOS 12; Wherein, MOS 12 comprises: drain electrode 102, source electrode 103, gate oxide 104, grid 105 and side wall layer 106, and we will be positioned at the grid 105 on substrate 100 surfaces and the gate oxide 104 of grid 105 belows is called grid structure usually; Adopt ion implantation technology to form first diode 11, wherein first diode 11 comprises a N utmost point 107 and a P utmost point 101, and a P utmost point 101 ground connection (scheming not shown) of first diode 11; Adopt ion implantation technology to form second diode 14, wherein, second diode 14 comprises the 2nd P utmost point 109 and the 2nd N utmost point 110, and the 2nd N utmost point 110 ground connection (scheming not shown); Between the MOS 12 and first diode 11, several shallow channel isolation areas 108 are arranged, between first diode 11 and second diode 14, shallow channel isolation area 108 is arranged also.
Step 2; At substrate 100 surface depositions first dielectric layer 201; Adopt etch process on grid 105, a N utmost point 107 and the 2nd P utmost point 109, to be formed for follow-up metal interconnected first through hole 202, second through hole 203 and the 6th through hole 204 of carrying out respectively; And adopt depositing operation in first through hole 202, second through hole 203 and the 6th through hole 204, to fill metal; The metal of being filled can be copper or tungsten, adopts the surface of CMP technology with metal grinding to the first dielectric layer 201 in first through hole 202, second through hole 203 and the 6th through hole 204 at last.
Step 3; Adopt depositing operation on first dielectric layer 201, to form the first metal layer; And adopt etch process on the first metal layer, to form groove; Constitute first metal wire 301 without etched metal, wherein, first metal wire 301 makes MOS 12, first diode 11 and second diode 14 interconnect.
Step 4; Adopt depositing operation to form second dielectric layer 401; Adopt second dielectric layer 401 of etch process on MOS 12, first diode 11 and second diode 14 to form third through-hole 402, fourth hole 403 and the 7th through hole 404 respectively; And adopt depositing operation in third through-hole 402, fourth hole 403 and the 7th through hole 404, to fill metal; The metal of being filled can be copper or tungsten, adopts the surface of CMP technology with metal grinding to the second dielectric layer 401 in third through-hole 402, fourth hole 403 and the 7th through hole 404 at last.
Step 5 adopts depositing operation to form second metal level on second dielectric layer, 401 surfaces, and adopts etch process on second metal level, to form groove; Constitute second metal wire 501 without etched metal; Wherein, second metal wire 501 of MOS 12 tops is not connected with second metal wire 501 with first diode, 11 tops, that is to say; The MOS 12 and first diode 11 do not interconnect at second metal level; First diode 11 has second metal wire 501 to be connected with second diode 14, that is to say, first diode 11 and second diode 14 are at second layer metal interconnection.
Step 6; Adopt depositing operation to form the 3rd dielectric layer 601; Adopt and form fifth hole 602 in the 3rd dielectric layer 601 of etch process on MOS 12; Adopt etch process on second metal wire 501 that is used for first diode 11 and 14 interconnection of second diode, to form the 8th through hole 603; And adopt depositing operation in fifth hole 602 and the 8th through hole 603, to fill metal, the metal of being filled can be copper or tungsten, adopt at last CMP technology with in fifth hole 602 and the 8th through hole 603 the surface of metal grinding to the three dielectric layers 601.
Step 7; Adopt the surface deposition metallic aluminium of depositing operation, and adopt etch process to form first pad 13 and second pad 16, wherein at the 3rd dielectric layer 601; First pad 13 is on fifth hole 602; Can form metal interconnectedly with the metal in the fifth hole 602, second pad 16 can form metal interconnected with the metal in the 8th through hole 603 on the 8th through hole 603.。
When in initial condition; Shown in the arrow among Fig. 2; The positive charge that plasma abnormal discharge produces can be directed to the earth from second diode 14; The negative electrical charge that plasma abnormal discharge produces can be directed to the earth from first diode 11, like this, can avoid the plasma paradoxical discharge and the electric current that produces flows to grid 105 and grid 105 is caused damage along the metal interconnecting wires of grid 105 tops of MOS12; When in state of termination; Between first pad 13 and second pad 16, apply voltage; Because it is thinner to connect the part of the MOS 12 and first diode 11 in first metal wire 301, first metal wire 301 that therefore connects between the MOS 12 and first diode 11 can fuse, and this just makes to win does not have the metal connecting path between the pad 13 and first diode 11; There is not the metal connecting path between first pad 13 and second diode 14 yet; On first pad 13, apply the forward operating voltage of MOS 12 then, to MOS 12 the forward operating voltage to be provided through first pad 13, driven MOS 12 operate as normal.Need to prove; In the present invention, when in state of termination, if first metal wire 301 that connects between the MOS 12 and first diode 11 does not fuse; Then in flow; Be applied to forward operating voltage on first pad 13 and just make 14 conductings of second diode, and operating voltage is added on second diode 14, thus can't driven MOS 12 operate as normal.
In addition, present embodiment is to be that example describes with the semiconductor structure that comprises two metal layers, and in practical application, the number of the metal level that semiconductor structure comprises is decided as required, but the common metal layer is much larger than two-layer.
So far, this flow process finishes.
Based on above-mentioned gate protection method, Fig. 5 is the flow chart of the embodiment of gate protection method provided by the present invention.As shown in Figure 5, this method may further comprise the steps:
When in state of termination, the current density on first metal wire is greater than 10000000 amperes every square centimeter.
The width of the metal wire of the connection MOS and first diode is more than or equal to 0.09 and smaller or equal to 0.2 micron in first metal wire.
The embodiment of a kind of gate protection method provided by the present invention specifies please with reference to the respective description among the device embodiment shown in Figure 4, repeats no more here.
So far, this flow process finishes.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. gate protection device, this device comprises: FET MOS, first diode, second diode, first metal wire, first pad and second pad; Wherein,
During the stage, the grid of MOS is connected to a N utmost point of first diode and the 2nd P utmost point of second diode respectively through first metal wire, and a P utmost point ground connection of first diode, the 2nd N utmost point ground connection of second diode in the formation of metal interconnecting wires;
After metal interconnecting wires forms; The formation of first pad and second pad is during the stage; First pad links to each other with the grid of MOS; Second pad extremely links to each other with a N utmost point of first diode and the 2nd P of second diode simultaneously, between first pad and second pad, is applied with voltage, connects the metal wire fusing of the MOS and first diode in first metal wire.
2. device according to claim 1 is characterized in that, after forming at metal interconnecting wires, the formation of first pad and second pad is during the stage, and the current density on first metal wire is greater than 10000000 amperes every square centimeter.
3. device according to claim 2 is characterized in that, the width of the metal wire of the connection MOS and first diode is more than or equal to 0.09 and smaller or equal to 0.2 micron in first metal wire.
4. gate protection method, this method comprises:
In the formation of metal interconnecting wires during the stage, the grid of MOS is connected to a N utmost point of first diode and the 2nd P utmost point of second diode respectively through first metal wire, and with a P utmost point ground connection of first diode, with the 2nd N utmost point ground connection of second diode;
After metal interconnecting wires forms; The formation of first pad and second pad is during the stage; First pad is linked to each other with the grid of MOS; Second pad is extremely linked to each other with a N utmost point of first diode and the 2nd P of second diode simultaneously, and between first pad and second pad, apply voltage, make the metal wire fusing that connects the MOS and first diode in the metal wire of winning.
5. method according to claim 4 is characterized in that, after forming at metal interconnecting wires, the formation of first pad and second pad is during the stage, and the current density on first metal wire is greater than 10000000 amperes every square centimeter.
6. method according to claim 5 is characterized in that, the width of the metal wire of the connection MOS and first diode is more than or equal to 0.09 and smaller or equal to 0.2 micron in first metal wire.
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| CN 200910196546 CN102034807B (en) | 2009-09-27 | 2009-09-27 | Method and device for protecting grid electrode |
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| CN 200910196546 CN102034807B (en) | 2009-09-27 | 2009-09-27 | Method and device for protecting grid electrode |
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| CN102034807B true CN102034807B (en) | 2012-05-30 |
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| US20140159157A1 (en) * | 2012-12-07 | 2014-06-12 | Altera Corporation | Antenna diode circuitry and method of manufacture |
| CN105932021B (en) * | 2016-05-13 | 2019-02-01 | 上海华力微电子有限公司 | Method for preventing the antenna effect of semiconductor chip domain |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691234A (en) * | 1995-08-03 | 1997-11-25 | United Microelectronics Corporation | Buried contact method to release plasma-induced charging damage on device |
| CN1845331A (en) * | 2005-04-07 | 2006-10-11 | 冲电气工业株式会社 | Semiconductor device |
| CN101083264A (en) * | 2006-06-02 | 2007-12-05 | 中芯国际集成电路制造(上海)有限公司 | Proctive circuit of metal-oxide-semiconductor transistor and its producing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691234A (en) * | 1995-08-03 | 1997-11-25 | United Microelectronics Corporation | Buried contact method to release plasma-induced charging damage on device |
| CN1845331A (en) * | 2005-04-07 | 2006-10-11 | 冲电气工业株式会社 | Semiconductor device |
| CN101083264A (en) * | 2006-06-02 | 2007-12-05 | 中芯国际集成电路制造(上海)有限公司 | Proctive circuit of metal-oxide-semiconductor transistor and its producing method |
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