CN102033767B - A kind of method of veneer and veneer online upgrading - Google Patents
A kind of method of veneer and veneer online upgrading Download PDFInfo
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- CN102033767B CN102033767B CN201010578746.2A CN201010578746A CN102033767B CN 102033767 B CN102033767 B CN 102033767B CN 201010578746 A CN201010578746 A CN 201010578746A CN 102033767 B CN102033767 B CN 102033767B
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Abstract
The invention provides a kind of veneer, described veneer comprises main control unit, FPGA unit, the first storage unit and the second storage unit, wherein, described main control unit, for loading minimum steering logic from described FPGA unit, load successfully from second storage unit read FPGA official release and store, FPGA unit is reloaded; Described FPGA unit, for automatically loading minimum steering logic from the first storage unit; Described first storage unit, for storing minimum steering logic; Described second storage unit, for storing the official release of FPGA; Present invention also offers a kind of method of veneer online upgrading; Apply the method for veneer of the present invention and veneer online upgrading, not only save veneer cost, but also achieve the online upgrading of veneer FPGA unit.
Description
Technical field
The present invention relates to data communication field, specifically, relate to a kind of method of veneer and veneer online upgrading.
Background technology
At communication technical field, FPGA (Field Programmable Gate Array, field programmable gate array) to have density more and more higher, speed goes is fast, capacity is increasing, the plurality of advantages such as can to redistribute, but its power down volatibility determines its range of application there are some to limit to.
The downloading mode of FPGA mainly contains two kinds, and one is that FPGA initiatively loads, and namely FPGA initiatively reads logic from nonvolatile memory (being generally ROM); Another kind is passive loading, and namely FPGA waits for that master devices downloads logic to it.
The another kind of logical device corresponding with FPGA is CPLD (Complex Programmable LogicDevice, CPLD), although the speed of CPLD is slow, capacity is little, but has the feature that power down is not volatile.
Therefore the framework of most of hardware system veneer is usually by CPU+CPLD+FPGA+ nonvolatile memory, be illustrated in figure 1 the configuration diagram of existing veneer, existing veneer is made up of CPU, CPLD, FPGA and Flash, wherein CPU is main control unit, CPLD is used for basic control function, and FPGA is used for realizing business function, and Flash is for storing FPGA version, the high speed of its feature utilizing the power down of CPLD not volatile and FPGA, Large Copacity feature realizes concrete function.
Its workflow is substantially as follows:
First, Board Power up, the steering logic in CPLD is not volatile owing to having power down, so work at first, utilizes I/O interface to control the original state of whole veneer, and completes required control and logic working when CPU starts;
Then, CPU starts to load, and loads successfully, reads the FPGA version in Flash, and the load bus of utilization and FPGA loads FPGA.
The FPGA version be stored in nonvolatile memory can be upgraded by external interface.
Although said method is flexible, due to FPGA, to have power down volatile, therefore must increase a CPLD and realize the most initial logic control function.Therefore this scheme cost is higher, and design is complicated, and CPLD is generally downloaded by JTAG (Joint Test Action Group, joint test behavior tissue) interface, therefore can not realize online upgrading, be unfavorable for remote maintenance and upgrade logic.
Summary of the invention
The technical matters that the present invention solves there is provided a kind of method of veneer and veneer online upgrading, achieves the automatic on-line upgrading of veneer.
In order to solve the problem, the invention provides a kind of veneer, described veneer comprises main control unit, FPGA unit, the first storage unit and the second storage unit, wherein,
Described main control unit, for loading minimum steering logic from described FPGA unit, load successfully from second storage unit read FPGA official release and store, FPGA unit is reloaded;
Described FPGA unit, for automatically loading minimum steering logic from the first storage unit;
Described first storage unit, for storing minimum steering logic;
Described second storage unit, for storing the official release of FPGA.
Further, described veneer also comprises load-on module selection unit, and described load-on module selection unit is defaulted as bootstrap loading pattern;
Described FPGA unit is used for automatically loading minimum steering logic from the first storage unit by described load-on module selection unit;
Described minimum steering logic comprise main control unit start needed for control and logic.
Above-mentioned veneer, wherein, described main control unit is used for sending control command to change the state of load-on module selection unit to described loading mode selection unit;
Described bootstrap loading Mode change, for after receiving described control command, is passive loading by described load-on module selection unit.
Further, described veneer also comprises supervisory circuit unit,
Described main control unit and described FPGA unit are loading successfully, send load success message to supervisory circuit;
Described supervisory circuit unit, during for can not receive the loading success message of main control unit and FPGA unit in the schedule time, triggers the reset function of veneer, removes the content of FPGA unit and triggers FPGA unit and automatically load.
Above-mentioned veneer, wherein, FPGA version also for being carried out the upgrading of FPGA version by external interface, and is saved to the second storage unit, to carry out the version updating of FPGA unit by described main control unit.
Present invention also offers a kind of method of veneer online upgrading, the method comprises:
FPGA unit loads minimum steering logic from the first storage unit automatically;
Main control unit loads described minimum steering logic from described FPGA unit, loads successfully, reads the official release of FPGA and store from the second storage unit;
Described main control unit reloads FPGA unit, loading successfully, completes online upgrading.
Above-mentioned method, wherein, described FPGA unit automatically loads minimum steering logic from the first storage unit and is specially:
Described FPGA unit loads minimum steering logic automatically by load-on module selection unit from the first storage unit, and described load-on module selection unit is defaulted as bootstrap loading pattern;
Described minimum steering logic comprise main control unit start needed for control and logic.
Above-mentioned method, wherein, after FPGA unit loads automatically, before main control unit reloads, described method also comprises:
Described main control unit sends control command to load-on module selection unit, and the pattern changing described load-on module selection unit is passive loading, and removes the minimum steering logic of described FPGA unit;
Above-mentioned method, described method comprises further,
Described main control unit and described FPGA unit are loading successfully, send load success message to supervisory circuit;
If described supervisory circuit unit is when the schedule time can not receive the loading success message of main control unit and FPGA unit, trigger the reset function of veneer, remove the content of FPGA unit and trigger FPGA unit and automatically load.
Above-mentioned method, described method comprises further,
Described main control unit carries out the upgrading of FPGA version by external interface, and FPGA version is saved to the second storage unit, to carry out the version updating of FPGA unit.
Application technique scheme, introduces the first storage unit, achieves the automatic value-added tax function of FPGA unit, and namely achieving after power down still can the function of retention logic, thus eliminates the CPLD in existing scheme, saves veneer cost.After utilizing main control unit to load, read the formal FPGA version of the second storage unit and store, and by the downloading mode changing FPGA unit, FPGA unit being downloaded again, realizing the online upgrading to FPGA unit.In addition, the second storage unit can store multiple FPGA version simultaneously, downloads other versions in the second storage unit by external interface, realizes online upgrading by the version changing FPGA.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms a part of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the configuration diagram of existing veneer;
Fig. 2 is a kind of single plate structure figure provided by the invention;
Fig. 3 is a kind of veneer specific embodiment structural drawing provided by the invention;
Fig. 4 is the method flow diagram of a kind of veneer online upgrading provided by the invention;
Fig. 5 is the method specific embodiment process flow diagram of a kind of veneer online upgrading provided by the invention.
Embodiment
In order to make technical matters to be solved by this invention, technical scheme and beneficial effect clearly, understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As described in Figure 2, provide a kind of veneer, this veneer comprises main control unit, FPGA unit, the first storage unit and the second storage unit, wherein,
Described main control unit, for loading minimum steering logic from described FPGA unit, load successfully from second storage unit read FPGA official release and store, FPGA unit is reloaded;
Described FPGA unit, for automatically loading minimum steering logic from the first storage unit, this minimum steering logic comprise main control unit start needed for control and logic;
Described first storage unit, for storing minimum steering logic;
Described second storage unit, for storing the official release of FPGA.
In this veneer, main control unit is CPU or other processors, and the first storage unit and the second storage unit are nonvolatile memory cell, and the first storage unit can be ROM, and the second storage unit can be Flash.
As shown in Figure 3, provide a kind of specific embodiment of veneer, this veneer comprises CPU element 101, FPGA unit 102, supervisory circuit unit 103, load-on module selection unit 104, and nonvolatile memory cell, is ROM105 and Flash106 respectively, wherein,
CPU element 101, has general I/O interface and external interface, for loading described minimum steering logic by load-on module selection unit 104, load successfully, notice supervisory circuit unit 103, reads the official release of FPGA, exists in the internal memory of CPU element 101 after reading from Flash106; The state sending control command change load-on module selection unit 104 is passive loading, and remove the minimum steering logic of FPGA unit 102, then FPGA unit 102 is reloaded, after loading, whether load successful according to the operation judges of FPGA unit 102 some function inner, if success, veneer can carry out follow-up business, otherwise the version again reading Flash06 loads FPGA unit.
In addition, CPU element from maintenance centre or backstage by external interface (as network interface etc.), is carried out the upgrading of FPGA version, and version is saved in Flash, utilize CPU element to carry out the version updating of FPGA unit, i.e. online upgrading.
FPGA unit 102, for automatically loading minimum steering logic from nonvolatile memory 105 by load-on module selection unit 104, this minimum steering logic include but not limited to CPU start needed for control and logic, its effect just realizes CPU and starts and guarantee normally to access FLASH, loads notice supervisory circuit unit 103 successfully;
Supervisory circuit unit 103, jointly realized by FPGA and reset circuit, FPGA unit and the CPU element backward reset circuit that normally works fixes output clock pulse, during as can not receive the fixed clock pulse of CPU element 101 and FPGA unit 102 in the given time, trigger the reset function of veneer, remove the content of FPGA unit and trigger FPGA unit and again automatically load;
Load-on module selection unit 104, loading mode for controlling FPGA unit 102 selects pin, and the loading mode of FPGA unit 102 is controlled according to the control signal state of CPU element, decision is bootstrap loading pattern or passive loading mode, is defaulted as bootstrap loading pattern.
Non-volatile memory cells, comprises ROM105, and it stores minimum steering logic, ensures that CPU element normally starts; And Flash106, it stores the official release of FPGA unit, can store multiple version, and namely CPU element realizes online upgrading by reading different editions automatic switchover.
Present invention also offers a kind of method of veneer online upgrading, as shown in Figure 4, be applied in the veneer shown in Fig. 2, comprise the steps:
S401, FPGA unit loads minimum steering logic from the first storage unit automatically, this minimum steering logic comprise main control unit start needed for control and logic;
S402, main control unit loads described minimum steering logic from described FPGA unit, loads successfully, reads the official release of FPGA and store from the second storage unit;
S403, described main control unit reloads FPGA unit, loading successfully, completes online upgrading.
As shown in Figure 5, provide a kind of specific embodiment of method of veneer online upgrading, be applied in the veneer shown in Fig. 3, comprise the steps:
S501, Board Power up loads, and now whole system is all reset, without any version, simultaneously in FPGA unit 102 also without logic, the default conditions of load-on module selection unit 104 be automatic loading;
S502, FPGA unit 102 loads minimum steering logic automatically by load-on module selection unit 104 from ROM105, this minimum steering logic include but not limited to CPU start needed for control and logic, also referred to as Systematical control version, its effect just realizes CPU and starts and guarantee normally to access Flash, load notice supervisory circuit unit 103 successfully, if supervisory circuit unit 103 does not receive loading success notification in the schedule time, then automatically can trigger reset;
S503, FPGA unit 102 loads successfully automatically, CPU element 101 loads described minimum steering logic by load-on module selection unit 104, load successfully, notice supervisory circuit unit 103, if supervisory circuit unit 103 does not receive loading success notification in the schedule time, then automatically can trigger reset;
S504, CPU element 101 loads successfully, reads the official release of FPGA from Flash106, exists in the internal memory of CPU element 101 after reading;
S505, CPU element sends control command to load-on module selection unit 104, and the state changing load-on module selection unit 104 is passive loading, and removes the minimum steering logic of FPGA unit 102;
S506, CPU element 101 pairs of FPGA unit 102 are reloaded, after loading, whether successfully load according to the operation judges of FPGA unit 102 some function inner, if success, veneer can carry out follow-up business, completes online upgrading, otherwise the version again reading Flash06 loads FPGA unit.
In addition, CPU can pass through external interface (as network interface etc.) from maintenance centre or backstage, carries out the upgrading of FPGA version, and version is saved in Flash, utilize CPU to carry out the version updating of FPGA.
Application technique scheme, introduces the first storage unit (ROM), achieves the automatic value-added tax function of FPGA unit, and namely achieving after power down still can the function of retention logic, thus saves the CPLD in existing scheme.What store in the first storage unit is generic logic, and its effect realizes main control unit start and guarantee normally to access Flash, and therefore it there is no online upgrading demand.After utilizing main control unit to load, read the formal FPGA version of the second storage unit and store, and by the downloading mode changing FPGA unit, FPGA unit being downloaded again, realizing the online upgrading to FPGA unit.In addition, the second storage unit can store multiple FPGA version simultaneously, downloads other versions in the second storage unit by external interface, realizes online upgrading by the version changing FPGA.
Above-mentioned explanation illustrate and describes a preferred embodiment of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the present invention, then all should in the protection domain of claim appended by the present invention.
Claims (10)
1. a veneer, is characterized in that, described veneer comprises main control unit, FPGA unit, the first storage unit and the second storage unit, wherein,
Described main control unit, for loading minimum steering logic from described FPGA unit, load successfully from second storage unit read FPGA official release and store, FPGA unit is reloaded;
Described FPGA unit, for automatically loading minimum steering logic from the first storage unit;
Described first storage unit, for storing minimum steering logic;
Described second storage unit, for storing the official release of FPGA.
2. veneer according to claim 1, is characterized in that, described veneer also comprises load-on module selection unit, and described load-on module selection unit is defaulted as bootstrap loading pattern;
Described FPGA unit is used for automatically loading minimum steering logic from the first storage unit by described load-on module selection unit;
Described minimum steering logic comprise main control unit start needed for control and logic.
3. veneer according to claim 2, is characterized in that, described main control unit is used for sending control command to change the pattern of load-on module selection unit to described loading mode selection unit;
Described bootstrap loading Mode change, for after receiving described control command, is passive loading by described load-on module selection unit.
4., according to the arbitrary described veneer of claims 1 to 3, it is characterized in that, described veneer also comprises supervisory circuit unit,
Described main control unit and described FPGA unit are loading successfully, send load success message to supervisory circuit;
Described supervisory circuit unit, during for can not receive the loading success message of main control unit and FPGA unit in the schedule time, triggers the reset function of veneer, removes the content of FPGA unit and triggers FPGA unit and automatically load.
5., according to the arbitrary described veneer of claims 1 to 3, it is characterized in that, FPGA version also for being carried out the upgrading of FPGA version by external interface, and is saved to the second storage unit, to carry out the version updating of FPGA unit by described main control unit.
6. a method for veneer online upgrading, is characterized in that, described method comprises:
FPGA unit loads minimum steering logic from the first storage unit automatically;
Main control unit loads described minimum steering logic from described FPGA unit, loads successfully, reads the official release of FPGA and store from the second storage unit;
Described main control unit reloads FPGA unit, loading successfully, completes online upgrading.
7. method according to claim 6, is characterized in that, described FPGA unit automatically loads minimum steering logic from the first storage unit and is specially:
Described FPGA unit loads minimum steering logic automatically by load-on module selection unit from the first storage unit, and described load-on module selection unit is defaulted as bootstrap loading pattern;
Described minimum steering logic comprise main control unit start needed for control and logic.
8. method according to claim 7, is characterized in that, after FPGA unit loads automatically, before main control unit reloads, described method also comprises:
Described main control unit sends control command to load-on module selection unit, and the pattern changing described load-on module selection unit is passive loading, and removes the minimum steering logic of described FPGA unit.
9., according to the arbitrary described method of claim 6 to 8, it is characterized in that, described method comprises further,
Described main control unit and described FPGA unit are loading successfully, send load success message to supervisory circuit;
If described supervisory circuit unit is when the schedule time can not receive the loading success message of main control unit and FPGA unit, trigger the reset function of veneer, remove the content of FPGA unit and trigger FPGA unit and automatically load.
10., according to the arbitrary described method of claim 6 to 8, it is characterized in that, described method comprises further,
Described main control unit carries out the upgrading of FPGA version by external interface, and FPGA version is saved to the second storage unit, to carry out the version updating of FPGA unit.
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| CN103513994B (en) * | 2012-06-19 | 2017-10-20 | 记忆科技(深圳)有限公司 | A kind of method and system that FPGA online upgradings are carried out by PCIE |
| CN103927210A (en) * | 2014-04-22 | 2014-07-16 | 唐山轨道客车有限责任公司 | FPGA loading system based on CPLD |
| CN105511897B (en) * | 2014-09-26 | 2018-11-09 | 新华三技术有限公司 | Method and apparatus for initializing programming device |
| CN105653299A (en) * | 2014-11-12 | 2016-06-08 | 杭州华三通信技术有限公司 | Firmware upgrade method device |
| WO2019084916A1 (en) * | 2017-11-03 | 2019-05-09 | 华为技术有限公司 | Method and system for recovering logic in fpga chip, and fpga apparatus |
| CN110704365A (en) * | 2019-08-20 | 2020-01-17 | 浙江大华技术股份有限公司 | Reconstruction device based on FPGA |
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