CN102023566A

CN102023566A - Method for controlling and producing AC code of IRIG-B as time synchronization standard by FPGA (field programmable gata array)

Info

Publication number: CN102023566A
Application number: CN 201010505485
Authority: CN
Inventors: 丁晨; 张柄瑶; 叶磊
Original assignee: Shanghai Airui Science & Technology Development Co Ltd
Current assignee: Shanghai Rui Qiang Mdt InfoTech Ltd
Priority date: 2010-10-13
Filing date: 2010-10-13
Publication date: 2011-04-20
Anticipated expiration: 2030-10-13
Also published as: CN102023566B

Abstract

The invention relates to a method for controlling and producing an AC code of an IRIG-B as a time synchronization standard by a FPGA (field programmable gata array), which comprises the following steps: a DC code stream of the IRIG-B passes through the FPGA, then an AC code number sequence for amplitude modulation of a sine wave (1KHz) is produced; the AC code number sequence passes through a DAC, then an AC code stream of the IRIG-B is produced; and the FPGA carries out level discrimination on the DC code stream of the IRIG-B, wherein 'H' means that the high level part synchronously triggers a phase accumulator 1, the sample data of a sine wave of which the peak value of a voltage peak is 10V is stored in a ROM 1, the output value of the phase accumulator 1 triggers the data output in the ROM 1; 'L' refers to the operation of the low level, and the operation principle of the low level is same as that of the high level. The method in the invention has the advantages that compared with the methods implemented based on MCU or DSP and DLC (digital logic circuit), the method in the invention can greatly reduce the system design difficulty, lower the cost, and improve the accuracy of a B code and the system flexibility.

Description

A kind ofly produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control

[technical field]

The present invention relates to the technical field of IRIG-B, FPGA, specifically produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA (field programmable gate array) control.

[background technology]

Target range measurement, Industry Control, power system measuring with protection, calculating, communicate by letter, timing code (being called for short the B sign indicating number) that testing apparatus such as meteorology is all adopted international standards the IRIG-B form is as the time synchronized standard, also is a kind of remote measurement time standard that China carries out.The B sign indicating number is a kind of time format of serial, is divided into two kinds of direct current sign indicating number (DC sign indicating number) and alternating current code (AC sign indicating number).

Existing alternating current code (AC sign indicating number) is based on MCU or DSP and DLC (digital logic circuit) realization, and this method also exists many weak points: the design difficulty of system is very big, cost height, shortcomings such as the accuracy of B sign indicating number and system flexibility difference.

[summary of the invention]

Purpose of the present invention is exactly will solve above-mentioned deficiency and provide a kind of and produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control.

Design for achieving the above object and a kind ofly produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control, it is characterized in that: at first, utilize the DC code stream of IRIG-B, carry out the AC yardage word sequence of amplitude modulation(PAM) earlier by the sine wave of FPGA generation 1KHz, again through producing the AC code stream of IRIG-B after the DAC, described FPGA carries out the differentiation of level to the DC sign indicating number of IRIG-B: " H ", the part meeting synchronous triggering phase accumulator 1 of high level, storing the sampled data that the voltage peak-to-peak value is the sine wave of 10V among the ROM 1, described phase accumulator 1 output valve triggers the data output among the ROM 1; " L ", low level is in like manner being stored the sampled data that the voltage peak-to-peak value is the sine wave of 2V among the ROM 2, and drawing modulation ratio is 1/5, and secondly the output data among ROM1, the ROM 2 realizes stack output AC yardage word sequence by the output data controller.

Described FPGA adopts directly synthetic technology mode of numeral, and the direct synthetic technology mode of described numeral sees through generation time variable signal under digital form, carries out the digital-to-analogue conversion action then.

Described DAC partly adopts D/A converting circuit, low-pass filter circuit to produce the AC code stream of simulation.

Described D/A converting circuit adopts DAC0832.

Beneficial effect of the present invention: with compare with the method that DLC (digital logic circuit) realizes based on MCU or DSP, this method can reduce the design difficulty of system greatly, reduces cost, and improves the accuracy and the system flexibility of B sign indicating number, is worthy of popularization.

[description of drawings]

Fig. 1 is the AC sign indicating number design frame chart of realization IRIG-B of the present invention;

Fig. 2 is the DC code stream format chart of IRIG-B;

Fig. 3 is the AC code stream format chart of IRIG-B;

Fig. 4 produces AC yardage word sequence implementation method figure for FPGA;

Fig. 5 produces the AC code stream circuit theory diagrams of simulation for DAC;

Among the figure: 41 is that DC code stream, 42 is that electrical level discrimination, 43 is that phase accumulator 1,44 is that

phase accumulator

2,45 is that sampled data ROM1,46 is that sampled data ROM2,47 is that output data controller, 48 is that AC yardage word sequence, 51 is that AC yardage word sequence, 52 is that D/A converting circuit, 53 is that low pass filter, 54 is the AC code stream.

[embodiment]

Below in conjunction with drawings and Examples structural representation of the present invention is further specified.

The present invention is exactly by the research to the IRIG-B sign indicating number, adopts the method for designing of FPGA.Utilize the DC code stream of IRIG-B, carry out the AC yardage word sequence of amplitude modulation(PAM) earlier by the sine wave of FPGA generation 1KHz, through producing the AC code stream of IRIG-B after the DAC, promptly on the basis of DC sign indicating number, realize ac modulation, again to obtain the AC sign indicating number.

The DC code stream form of IRIG-B as shown in Figure 2, it is the time string sign indicating number of per second one frame, each symbol width is 10ms, a time frame cycle comprises 100 code elements, is pulsewidth coding.Pulsewidth 0.2ms represents Binary Zero, and pulsewidth 0.5ms represents binary one, and pulsewidth 0.8ms represents location identifier or reference symbols sn.

The AC code stream form of IRIG-B as shown in Figure 3, the carrier wave of alternating current code is the 1KHz sinusoidal signal, changes in amplitude peak one peak value scope is 0.5～10V.Modulation ratio is U1/U0=1/6～1/2, be that index marker is the 1KHz sinusoidal signal that 8 amplitudes are U1, logical one is the 1KHz sinusoidal signal that 5 amplitudes are U1, and logical zero is the 1KHz sinusoidal signal that 2 amplitudes are U1, and other times are that amplitude is the 1KHz sinusoidal signal of U0.

In the FPGA part, adopted digital direct synthetic technology (DDS): a kind of method that produces analog waveform--normally sinusoidal wave, mode is to see through generation time variable signal under digital form, carries out the action of digital-to-analogue conversion then.Because operation mainly is digital in DDS, it can provide between the output frequency switches fast, trickle frequency resolution, and in the broad spectrum scope, operate.

The principle of the DC sign indicating number commentaries on classics AC yardage word sequence of FPGA realization IRIG-B as shown in Figure 4.At first, FPGA carries out the differentiation of level to the DC sign indicating number of IRIG-B: " H ", the part meeting synchronous triggering phase accumulator 1 of high level is being stored the sampled data that the voltage peak-to-peak value is the sine wave of 10V among the ROM 1, phase accumulator 1 output valve triggers the data output among the ROM 1 like this; " L ", low level in like manner but is being stored the sampled data that the voltage peak-to-peak value is the sine wave of 2V among the ROM 2, be 1/5 thereby draw modulation ratio.Secondly, the output data controller is to realize stack output AC yardage word sequence.

In the DAC part, adopt digital-to-analog conversion to add the AC code stream that low-pass filter circuit produces simulation, as shown in Figure 5.AC code stream by FPGA output is directly connected to DAC0832; Because the output of DAC0832 belongs to current mode, so must carrying out current/voltage, its output transforms, use the LM324 operational amplifier to get final product.At last, carry out filtering, the noise filtering in the waveform by electric capacity.

Claims

1. one kind produces the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control, it is characterized in that: at first, utilize the DC code stream of IRIG-B, carry out the AC yardage word sequence of amplitude modulation(PAM) earlier by the sine wave of FPGA generation 1KHz, described AC yardage word sequence is again through producing the AC code stream of IRIG-B after the DAC, described FPGA carries out the differentiation of level to the DC sign indicating number of IRIG-B: " H ", the part meeting synchronous triggering phase accumulator 1 of high level, storing the sampled data that the voltage peak-to-peak value is the sine wave of 10V among the ROM 1, described phase accumulator 1 output valve triggers the data output among the ROM 1; " L ", low level is in like manner being stored the sampled data that the voltage peak-to-peak value is the sine wave of 2V among the ROM 2, and drawing modulation ratio is 1/5, and secondly the output data among ROM 1, the ROM 2 realizes stack output AC yardage word sequence by the output data controller.

2. as claimed in claim 1ly produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control, it is characterized in that: described FPGA adopts directly synthetic technology mode of numeral, the direct synthetic technology mode of described numeral sees through generation time variable signal under digital form, carries out the digital-to-analogue conversion action then.

3. as claimed in claim 1 or 2ly produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control, it is characterized in that: described DAC partly adopts D/A converting circuit, low-pass filter circuit to produce the AC code stream of simulation.

4. as claimed in claim 3ly produce the method for the AC sign indicating number of IRIG-B as the time synchronized standard by FPGA control, it is characterized in that: described D/A converting circuit adopts DAC0832.