CN102012877B - Flushbonading stored program control exchange for expanding embedded processor GPIO by using CPLD - Google Patents
Flushbonading stored program control exchange for expanding embedded processor GPIO by using CPLD Download PDFInfo
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- CN102012877B CN102012877B CN2010105607991A CN201010560799A CN102012877B CN 102012877 B CN102012877 B CN 102012877B CN 2010105607991 A CN2010105607991 A CN 2010105607991A CN 201010560799 A CN201010560799 A CN 201010560799A CN 102012877 B CN102012877 B CN 102012877B
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Abstract
The invention discloses a method for expanding an embedded processor general purpose input/output (GPIO) by using a complex programmable logic device (CPLD), wherein expands the embedded processor GPIO by using the CPLD to control multi-path voice modules and technology. The method effectively and organically combines the low-cost CPLD and the high-end embedded processor together so that a user conveniently finishes rich additional functions by using the same embedded processor. The method can expand GPIO wires in a number of subtracting 4 from the actual GPIO number of the CPLD at most by using 4 GPIOs (using a bus interface of software simulation serial peripheral interfaces (SPI)) of the embedded processor, or 1 hardware SPI interface and 1 GPIO so as to greatly enrich the application range of the embedded processor.
Description
Technical field
The present invention relates to a kind of method of expanding flush bonding processor GPIO, be specifically related to a kind of communication technology of utilizing the CPLD device to expand flush bonding processor GPIO that relates to.
Background technology
Raising along with science and technology development and chip technology technology; Increasing flush bonding processor (especially digital signal processor) provides increasingly high single-chip performance, the single-chip size that reduces more and more and more lower power consumption for the user; Thereby let user's design become more and more lighter, quick and low-cost; But also can let certain customers in actual design, run into the for example not enough situation of GPIO simultaneously, the user has to add more logical device in order to expand GPIO quantity sometimes; Perhaps have to change flush bonding processor with more GPIO; The former will increase the size of printed circuit board and the workload of wiring largely, and the latter possibly introduce more hardware cost and design difficulty owing to use a plurality of chips.
Summary of the invention
Technical matters to be solved by this invention provides a kind of embedded design technology that addresses the aforementioned drawbacks; Be specially a kind of CPLD of utilization and expand the method for flush bonding processor GPIO, utilize CPLD (PLD) device to expand flush bonding processor GPIO (general input and output pin) and reach control multi-path voice module and technology.
Technical matters proposed by the invention is to solve like this: construct the method that a kind of CPLD of utilization expands flush bonding processor GPIO; It is characterized in that: the flush bonding processor that comprises a band hardware SPI interface; CPLD device with a band software simulation SPI interface; Wherein, the CPLD device is data of explaining the flush bonding processor spi bus, goes out corresponding GPIO interface according to corresponding instruction transformation in the data; The present invention also comprises the spi bus process software of flush bonding processor end and the interpretive routine part in the CPLD device; Wherein the spi bus process software is responsible for the hardware SPI interface of initialization flush bonding processor, passes through spi bus simultaneously to CPLD device input of control commands; The CPLD interpretive routine mainly is responsible for analyzing the spi bus data, controls inner IO according to corresponding order, lets it assist to accomplish the expanded function of flush bonding processor.
A kind of embedded programme-controlled exchange that utilizes the GPIO of CPLD expansion flush bonding processor is characterized in that: comprise an embedded dsp, a CPLD device, 4 telephone line interfaces and 4 dual-colored LED lamps, wherein,
Embedded dsp connects the CPLD device through spi bus, through the interpretive routine in the CPLD device, exports the chip selection signal that 4 telephone line interfaces need; The spi bus of connection processing device is to telephone line interface simultaneously; When embedded dsp need be operated telephone line interface, at first can see chip selection signal off to activate telephone line interface to the telephone line interface of appointment, write the state that instructs or read telephone line interface to this telephone line interface through spi bus then; To reach the judgement line status; Receive calls the purpose of hanging up the telephone
Telephone line interface directly docks through pcm bus with embedded dsp, utilizes time-multiplexed rule to come mutual voice data,
Each dual-colored LED lamp all directly is connected with 2 GPIO of CPLD device, and the interpretive routine in the CPLD device is when receiving the order of embedded dsp driving LED lamp, and the output state of 2 GPIO of control promptly can reach the purpose of control LED lamp,
The CPLD device is when article one GPIO is effective, and the data of control command and a byte that receive a byte from the spi bus interface are to buffer zone; The CPLD device judges that according to the control command that receives this control command is the order of control LED lamp; Still control the sheet choosing order of telephone line interface; If the order of control LED lamp; The data parsing of a byte is gone out the status data of 4 LED lamps of control, and CPLD devices use GPIO controls the state of 4 LED lamps respectively;
If the sheet choosing order of control telephone line interface, the sheet that then data parsing of a byte is gone out 4 telephone line interfaces of control selects status data; Select status data to deliver to telephone line interface the sheet of correspondence from the GPIO of CPLD device; Can receive the signal of indication second GPIO effective status simultaneously, continue to read the data of control telephone line interface register this moment, with the function of complete operation telephone line interface from spi bus.
Beneficial effect of the present invention is: the present invention effectively organically combines cheap CPLD device and high-end flush bonding processor, makes things convenient for the user to utilize same flush bonding processor to accomplish abundant additional function.The present invention takies 4 GPIO of flush bonding processor (utilizing software simulation spi bus interface), or 1 hardware SPI interface and 1 GPIO; Can expand the actual GPIO quantity of CPLD at most and deduct 4 GPIO line, enrich the range of application of flush bonding processor greatly.
This techniques make use is the CPLD chip cheaply, for high-end flush bonding processor (especially digital signal processor) provides abundant input and output pin, thereby the performance of maximum possible the function of flush bonding processor.
Description of drawings
Fig. 1 is a hardware structure synoptic diagram of the present invention.
The software flow synoptic diagram of a byte of Fig. 2.
Fig. 3 is the structural representation of embedded programme-controlled exchange of the present invention.
Fig. 4 is the schematic flow sheet of the described switch of Fig. 3.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further explanation:
Invention effectively organically combines cheap CPLD device and high-end flush bonding processor, makes things convenient for the user to utilize same flush bonding processor to accomplish abundant additional function.The present invention takies 4 GPIO of flush bonding processor (utilizing software simulation spi bus interface), or 1 hardware SPI interface and 1 GPIO; Can expand the actual GPIO quantity of CPLD at most and deduct 4 GPIO line, enrich the range of application of flush bonding processor greatly.
Hardware structure of the present invention is as shown in Figure 1, comprises a flush bonding processor (band hardware SPI interface) and a CPLD device.
Wherein, the CPLD device is core of the present invention, explains the data of flush bonding processor spi bus, goes out corresponding GPIO interface according to corresponding instruction transformation in the data.Software of the present invention comprises the interpretive routine in flush bonding processor end spi bus process software and the CPLD device; The spi bus process software mainly is responsible for the hardware SPI interface of initialization flush bonding processor, passes through spi bus simultaneously to CPLD device input of control commands; The CPLD interpretive routine, main being responsible for analyzed the spi bus data, controls inner IO according to corresponding order, lets it assist to accomplish the expanded function of flush bonding processor.
The present invention provides a kind of embedded programme-controlled exchange of using said method at this, and this system comprises a digital signal processor, CPLD chip and 4 telephone line interfaces and 4 dual-colored LED lamps, its concrete structure such as Fig. 3.
4 dual-colored LED lamps and 4 FXO modules need 12 GPIO altogether in this system; Generally DSP chip is removed outside the GPIO of system self needs; Be difficult to the GPIO that provides so many, the digital signal processor spi bus comprises a SPI interface and 2 GPIO (GPIO1, GPIO2).Pcm bus and the present invention have nothing to do in this system, just introduce for the complete description systemic-function.Digital signal processor connects CPLD through spi bus, and through the interpretive routine of CPLD, chip selection signal and the SPI data bus of export 4 telephone line interfaces (FXO) needs are to the FXO module; When digital signal processor need be operated the FXO module; At first can see chip selection signal off with active module, write instruction or read module state through the SPI data bus to module then, to reach such as judging line status to the module of appointment; Receive calls function such as hang up the telephone; The pcm bus of digital signal processor and the pcm bus of module directly dock, and utilize time-multiplexed rule to come mutual voice data.A dual-colored LED lamp directly is connected with 2 GPIO of CPLD simultaneously, and interpretive routine is when receiving the order of digital signal processor driving LED, and the output state of controlling its GPIO can reach the purpose of control LED lamp.
The workflow that Fig. 4 has provided this system is following:
The CPLD device when GPIO1 is effective, from the SPI interface receive a control command add data totally 2 byte datas to buffer zone;
CPLD judges it is control LED signal according to the control command that receives, and still is as the chip selection signal of FXO module;
If control LED orders, the data parsing of a byte is gone out the state of 4 LED of control;
If the chip selection signal of control FXO module, the sheet that the data parsing of a byte is gone out 4 FXO of control selects state; Can receive the effective state of GPIO2 simultaneously, continue to read the data of control FXO module register this moment, with the function of complete operation FXO module from the SPI interface.
Claims (1)
1. embedded programme-controlled exchange that utilizes the GPIO of CPLD expansion flush bonding processor is characterized in that: comprise an embedded dsp, a CPLD device, 4 telephone line interfaces and 4 dual-colored LED lamps, wherein,
Embedded dsp connects the CPLD device through spi bus, through the interpretive routine in the CPLD device, exports the chip selection signal that 4 telephone line interfaces need; The spi bus of connection processing device is to telephone line interface simultaneously; When embedded dsp need be operated telephone line interface, at first can see chip selection signal off to activate telephone line interface to the telephone line interface of appointment, write the state that instructs or read telephone line interface to this telephone line interface through spi bus then; To reach the judgement line status; Receive calls the purpose of hanging up the telephone
Telephone line interface directly docks through pcm bus with embedded dsp, utilizes time-multiplexed rule to come mutual voice data,
Each dual-colored LED lamp all directly is connected with 2 GPIO of CPLD device, and the interpretive routine in the CPLD device is when receiving the order of embedded dsp driving LED lamp, and the output state of 2 GPIO of control promptly can reach the purpose of control LED lamp,
The CPLD device is when article one GPIO is effective, and the data of control command and a byte that receive a byte from the spi bus interface are to buffer zone; The CPLD device judges that according to the control command that receives this control command is the order of control LED lamp; Still control the sheet choosing order of telephone line interface; If the order of control LED lamp; The data parsing of a byte is gone out the status data of 4 LED lamps of control, and CPLD devices use GPIO controls the state of 4 LED lamps respectively;
If the sheet choosing order of control telephone line interface, the sheet that then data parsing of a byte is gone out 4 telephone line interfaces of control selects status data; Select status data to deliver to telephone line interface the sheet of correspondence from the GPIO of CPLD device; Can receive the signal of indication second GPIO effective status simultaneously, continue to read the data of control telephone line interface register this moment, with the function of complete operation telephone line interface from spi bus.
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CN102436432A (en) * | 2011-09-15 | 2012-05-02 | 中兴通讯股份有限公司 | Read-write method and system for embedded type microprocessor |
CN103297163B (en) * | 2012-02-22 | 2016-10-05 | 安凯(广州)微电子技术有限公司 | A kind of method and device being intended PCM communication by GPIO mouth die |
CN103488601B (en) * | 2012-06-12 | 2016-04-20 | 京信通信技术(广州)有限公司 | A kind of clock delay, data access method, system and equipment |
CN103914414A (en) * | 2012-12-30 | 2014-07-09 | 航天信息股份有限公司 | I/O port based SPI simulation method and device |
CN105404594A (en) * | 2015-10-30 | 2016-03-16 | 山东超越数控电子有限公司 | Control method and device of blade server |
CN105426336A (en) * | 2015-11-09 | 2016-03-23 | 上海斐讯数据通信技术有限公司 | Data processing system and data reading output method |
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CN1459734A (en) * | 2002-05-21 | 2003-12-03 | 联想(北京)有限公司 | Installation for realizing extension ceasing using CPLD |
CN101303680A (en) * | 2008-06-17 | 2008-11-12 | 深圳市宏电技术股份有限公司 | Method and apparatus for expanding multiple serial ports of terminal |
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CN1459734A (en) * | 2002-05-21 | 2003-12-03 | 联想(北京)有限公司 | Installation for realizing extension ceasing using CPLD |
CN101303680A (en) * | 2008-06-17 | 2008-11-12 | 深圳市宏电技术股份有限公司 | Method and apparatus for expanding multiple serial ports of terminal |
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Address after: 610041 building 11, hi tech incubator Park, 1480 North Tianfu Road, Chengdu hi tech Zone, Sichuan Patentee after: Chengdu branch communications technology Limited by Share Ltd Address before: 610041 building 11, hi tech incubator Park, 1480 North Tianfu Road, Chengdu hi tech Zone, Sichuan Patentee before: ZYCOO Co., Ltd. |