CN102005960A - Inverter with three bridge arms and nine switches for dual-alternating-current motor drive and control method thereof - Google Patents

Abstract

The invention relates to an inverter with three bridge arms and nine switches for dual-alternating-current motor drive and a control method thereof. The inverter comprises a main loop, a first coder, a second coder, a current detection circuit, a digital signal processor and drive circuits, wherein the main loop comprises a direct-current power source, a filter capacitor, nine switch elements, a first current transformer and a second current transformer. In the inverter with three bridge arms and nine switches for dual-alternating-current motor drive and the control method thereof provided by the invention, one inverter can be used for independently controlling two three-phase alternating-current motors simultaneously; because the number of the switch elements in the inverter is nine and is reduced by three as compared with the prior art, the volume of the controller and the number of the drive circuits can be reduced; and one digital signal processor can be used for realizing the output of pulse-width modulation signals, so that the cost can be effectively lowered. In addition, the inverter also has the advantages of reasonable structural design, high control accuracy, strong practicability and the like.

Description

Be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and control method thereof

Technical field

The present invention relates to a kind of inverter and control method thereof, particularly relate to and a kind ofly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and control method thereof.

Background technology

A lot of industrial applications such as the motor vehicle that drives such as wheel hub motor, industrial robot, mine, electric locomotive all need to realize the independent control of two or four alternating current machines.

Alternating current machine is normally driven by the DC-AC inverter of an AC power supply.The DC busbar voltage is supplied with inverter and is converted AC voltage to, is used to drive each phase of alternating current machine.Alternating current machine generally adopts three-phase structure.Microcontroller or digital signal processor are the typical elements that is used for control inverter, come to apply predetermined driving voltage as the switch element gate signal of power device in their control inverters to alternating current machine, general pulse-width modulation (PWM) signal that adopts, the switch element of employing is generally IGBT or MOSFET.When needs are controlled two alternating current machines separately, method commonly used at present has two kinds: a kind of is to dispose an inverter separately for every alternating current machine, promptly use two inverters, wherein every inverter all is three brachium pontis, comprise two switch elements in each brachium pontis, need 12 switch elements altogether.Because the volume of controller is bigger when adopting two inverters, and the number of inverse parallel diode, drive circuit is more, so cost is higher.Another method is to adopt an inverter to control two alternating current machines simultaneously, this moment, inverter was six brachium pontis, comprise two switch elements in each brachium pontis, six brachium pontis are divided into two groups, control an alternating current machine separately for every group, though be merged into the quantity and a cost that can reduce parts such as inverter casing, radiator because of inverter by two when adopting this method, and the volume of controller reduces to some extent, but because the number of switch element does not change, and the number of inverse parallel diode, drive circuit also reduces, so cost is still higher.

Summary of the invention

In order to address the above problem, the object of the present invention is to provide a kind of double cross that is used for that can effectively reduce cost to flow motor-driven three brachium pontis, nine switching inverters.

In order to achieve the above object, provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and comprise: major loop, the 1st encoder, the 2nd encoder, current detection circuit, digital signal processor and drive circuit; Wherein, three-phase brachium pontis and the 1st, the 2nd current transformer that major loop is formed by DC power supply, filtering capacitor, by 9 switch elements are formed, and it has two three phase power output ports, is connected with the 2nd three phase electric machine with the 1st three phase electric machine respectively; 1st, the 2nd current transformer is installed in respectively on above-mentioned two three phase power output ports, and two output port is connected with two input ports of current detection circuit respectively, is used for detecting respectively the running current value of the 1st three phase electric machine and the 2nd three phase electric machine; The 1st encoder and the 2nd encoder are installed in respectively on the main shaft of the 1st three phase electric machine and the 2nd three phase electric machine, and two output port is connected with two input ports of digital signal processor respectively; Current detection circuit is the input interface circuit of the 1st, the 2 current transformer, and two input port links to each other with the 1st, the 2 current transformer respectively, and two output ports join with two input ports of digital signal processor respectively; Digital signal processor is the master controller of inverter, and its output port directly is connected with drive circuit; Drive circuit is the required gate drive circuit of switch element, is connected between digital signal processor and the major loop.

Described major loop comprises: DC power supply, filter capacitor, 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH and the 1st, the 2nd current transformer; Wherein filter capacitor is the power-type filtering capacitor, and it is pressed for dc bus provides galvanic current after the DC power supply parallel connection; 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH form the three-phase bridge arm jointly, wherein switch element UL, UM, UH are composed in series U phase brachium pontis, switch element VL, VM, VH are composed in series V phase brachium pontis, switch element WL, WM, WH are composed in series W phase brachium pontis, and U, V, W three-phase brachium pontis all are directly parallel on the dc bus; Three phase windings of the 1st three phase electric machine are connected between switch element UH and UM, VH and VM, WH and the WM; Three phase windings of the 2nd three phase electric machine are connected between switch element UL and UM, VL and VM, WL and the WM; 1st, the 2nd current transformer is installed in respectively on the major loop on the connecting line of two three phase power output ports and the 1st three phase electric machine and the 2nd three phase electric machine.

Described switch element UL, VL, WL, UM, VM, WM, UH, VH, WH are IGBT or MOSFET device.

The model of described digital signal processor 7 is TMS320F28335.

Described the 1st encoder and the 2nd encoder are the photoelectric type pulse coder.

Provided by the inventionly be used for double cross and flow the control method of motor-driven three brachium pontis, nine switching inverters and comprise the following step that carries out in order:

1) at S1 in the stage, at first the counter of digital signal processor is set to increase and decrease continuously count mode, produces triangular signal, and skew for according to axisymmetric signal of time as carrier signal, enter the S2 stage afterwards;

2) at S2 in the stage, whether judge earlier the carrier signal value greater than zero, when the carrier signal value enters the S3 stage when zero, otherwise enter the S5 stage;

3) at S3 in the stage, try to achieve the currency of the 1st reference signal according to the 1st reference signal curve equation, enter the S4 stage then;

4) at S4 in the stage, at first the currency of above-mentioned the 1st reference signal and the currency of carrier signal are compared, when the currency of the 1st reference signal during greater than the currency of carrier signal, the drive signal of switch element UH, VH, WH is effective, otherwise be invalid, enter the S7 stage afterwards;

5) at S5 in the stage, try to achieve the currency of the 2nd reference signal according to the 2nd reference signal curve equation, enter the S6 stage then;

6) at S6 in the stage, at first the currency of above-mentioned the 2nd reference signal and the currency of carrier signal are compared, when the currency of the 2nd reference signal during less than the currency of carrier signal, the drive signal of switch element UL, VL, WL is effective, otherwise be invalid, enter the S7 stage afterwards;

7) at S7 in the stage, earlier the drive signal of the drive signal of switch element UH, VH, WH and switch element UL, VL, WL is negated respectively, signal after then two being negated carries out the logical "or" computing, and resulting result is the drive signal of switch element UM, VM, WM.

Provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and control method thereof and can simultaneously two three phase alternating current motors be controlled separately by enough inverters, because the number of switch element is 9 in the inverter, 3 have been reduced than prior art, so can reduce the volume of controller and the number of drive circuit, and can realize the output of pulse-width signal by a slice digital signal processor, so can effectively reduce cost.In addition, this inverter also has reasonable in design, control precision height, advantage such as practical.

Description of drawings

Fig. 1 is used for double cross and flows motor-driven three brachium pontis, nine switching inverter major loop primary structure schematic diagrames for provided by the invention.

Fig. 2 flows motor-driven three brachium pontis, nine switching inverter major loop operational mode schematic diagrames for the double cross that is used for shown in Fig. 1.

Fig. 3 is INV1 shown in Fig. 2 and INV2 gate pole pulse-width signal generating principle sequential chart.

Carrier signal and the reference waveform signal schematic diagram of Fig. 4 when the 1st carrier signal among Fig. 3 and the 2nd carrier signal being merged into a complete triangular signal.

Fig. 5 is the composition structural representation that motor-driven three brachium pontis, nine switching inverters are flowed in double cross that is used for provided by the invention.

Fig. 6 is used for double cross and flows the corresponding control method flow chart that motor-driven three brachium pontis, nine switching inverters are adopted for provided by the invention.

Embodiment

In order to make purpose of the present invention, technical scheme clearer, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only is used to explain the present invention, and be not used in qualification the present invention.

Fig. 1 is used for double cross and flows motor-driven three brachium pontis, nine switching inverter major loop primary structure schematic diagrames for provided by the invention.As shown in Figure 1, provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverter major loops and mainly comprise: DC power supply E, filter capacitor C and 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH; Wherein filter capacitor C is the power-type filtering capacitor, and it is pressed for dc bus AR provides galvanic current after DC power supply E parallel connection; 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH are IGBT or MOSFET device, the common three-phase bridge arm of forming, wherein switch element UL, UM, UH are composed in series U phase brachium pontis, switch element VL, VM, VH are composed in series V phase brachium pontis, switch element WL, WM, WH are composed in series W phase brachium pontis, and U, V, W three-phase brachium pontis all are directly parallel on the dc bus AB; Three phase windings of the 1st three phase electric machine 2 are connected between switch element UH and UM, VH and VM, WH and the WM; Three phase windings of the 2nd three phase electric machine 3 are connected between switch element UL and UM, VL and VM, WL and the WM.

Owing to adopted above-mentioned three brachium pontis, nine switch topology, each brachium pontis all contains three switch elements and two-way output on dc bus AB.Yet, be implemented in and drive two motors on the dc bus simultaneously independently, just must adopt the operational mode of timesharing control, promptly realize the timesharing control of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3 by the reasonable cooperation of 9 switch element switch motions.The relative theory and the control method of two motor timesharing controls are described below by Fig. 2 and Fig. 3.

Fig. 2 flows motor-driven three brachium pontis, nine switching inverter major loop operational mode schematic diagrames for the double cross that is used for shown in Fig. 1.As shown in Figure 2, the figure middle and upper part is divided into the pattern 1 that is used to drive the 1st three phase electric machine 2, and the top of brachium pontis is called INV1 in the pattern 1, the figure lower middle portion be used to drive the 2nd three phase electric machine 3 pattern 2, the lower part of brachium pontis is called INV2 in the pattern 2.INV1 comprises switch element UM, VM, WM, UH, VH, WH, and INV2 comprises switch element UM, VM, WM, UL, VL, WL.

Fig. 3 is INV1 shown in Fig. 2 and INV2 gate pole pulse-width signal generating principle sequential chart.As shown in Figure 3, the carrier signal that is used for pulse-width modulation has adopted unique waveform, be characterized in: when the 1st three phase electric machine 2 is carried out the calculating of pulse-width signal, the 2nd reference signal that is used to control the 2nd three phase electric machine 3 always is lower than the 2nd carrier signal that is used for 3 controls of the 2nd three phase electric machine, when the 2nd three phase electric machine 3 was carried out the calculating of pulse-width signal, the 1st reference signal that is used to control the 1st three phase electric machine 2 always was higher than the 1st carrier signal that is used for 2 controls of the 1st three phase electric machine.Therefore, when inverter drove the 1st three phase electric machine 2, switch element UL, VL, WL were in " opening " state, and when inverter drove the 2nd three phase electric machine 3, switch element UH, VH, WH were in " opening " state.In addition, the 1st carrier signal among Fig. 3 and the 2nd carrier signal can merge when producing gate electrode drive signals, and the carrier signal after the merging is a complete triangular signal.

Carrier signal and the reference waveform signal schematic diagram of Fig. 4 when the 1st carrier signal among Fig. 3 and the 2nd carrier signal being merged into a complete triangular signal.As shown in Figure 4, when the first half that is in triangular wave (be ordinate greater than zero part), calculate the pulse-width signal of INV1, when the latter half that is in triangular wave (being the minus part of ordinate), calculate the pulse-width signal of INV2.Make the U phase reference voltage level of INV1 be

The U phase reference voltage level of INV2 is

And

$V_{u1}^{\mathrm{ref}}=A_1\sin (2\mathrm{\π}{f}_{1}t+{\mathrm{\θ}}_1)$

$V_{u2}^{\mathrm{ref}}=A_2\sin (2\mathrm{\π}{f}_{2}t+{\mathrm{\θ}}_2)$

Wherein: A ₁, A ₂Be amplitude, f ₁, f ₂Be frequency, θ ₁, θ ₂Be phase place.

Unified modulation rate m is:

$m=\frac{V_{\mathrm{ref}}}{E/2}$

Wherein: E is a d-c bus voltage value.

When calculating pulse-width signal, the 1st shifted signal E/4 is added on the 1st reference signal, the 2nd shifted signal-E/4 is added on the 2nd reference signal, thereby the modulation rate of the 1st reference signal and the 2nd reference signal is respectively:

$m_{1u}=\frac{V_{u1}^{\mathrm{ref}}+E/4}{E/2}=\frac{V_{u1}^{\mathrm{ref}}}{E/2}+\frac{1}{2}$

$m_{2u}=\frac{V_{u2}^{\mathrm{ref}}-E/4}{E/2}=\frac{V_{u2}^{\mathrm{ref}}}{E/2}-\frac{1}{2}$

Can reach a conclusion thus: the reference voltage range of INV1 and INV2 is respectively:

$-E/4\≤V_{u1}^{\mathrm{ref}}\≤E/4$

$-E/4\≤V_{u2}^{\mathrm{ref}}\≤E/4$

Fig. 5 is the composition structural representation that motor-driven three brachium pontis, nine switching inverters are flowed in double cross that is used for provided by the invention.As shown in Figure 5, provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and comprise: major loop the 1, the 1st encoder the 4, the 2nd encoder 5, current detection circuit 6, digital signal processor (DSP) 7 and drive circuit 8; Wherein, major loop 1 has adopted the topological structure that motor-driven three brachium pontis, nine switching inverter major loops are flowed in double cross that is used for shown in Figure 1, three-phase brachium pontis and the 1st, the 2nd current transformer CT1 that it is formed by DC power supply E, filtering capacitor C, by 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH, CT2 forms, it has two three phase power output ports, is connected with the 2nd three phase electric machine 3 with the 1st three phase electric machine 2 respectively; 1st, the 2nd current transformer CT1, CT2 is installed in respectively on above-mentioned two three phase power output ports, two output port is connected with two input ports of current detection circuit 6 respectively, is used for detecting respectively the running current value of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3; The 1st encoder 4 and the 2nd encoder 5 are installed in respectively on the main shaft of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3, and two output port is connected with two input ports of digital signal processor 7 respectively; Current detection circuit 6 is the 1st, the input interface circuit of the 2nd current transformer CT1 and CT2, two input ports link to each other with CT2 with the 1st, the 2 current transformer CT1 respectively on it, and two output ports join with two input ports of digital signal processor 7 respectively; Digital signal processor 7 is the master controller of inverter, usually adopt high speed digital signal processor, because its inner integrated pulse-width signal generation unit, therefore can under the control of software, generate pulse-width signal by calculating, the pulse-width signal that is generated can directly promote switch element work in the major loop 1 by drive circuit 8, simultaneously, as master controller, digital signal processor 7 also is responsible for finishing the control and the computing of whole inverter; Drive circuit 8 is switch element UL, VL, WL, UM, VM, WM, UH, VH, the required gate drive circuit of WH, is connected between digital signal processor 7 and the major loop 1.

The model of described digital signal processor 7 is TMS320F28335.

Described the 1st encoder 4 and the 2nd encoder 5 are the photoelectric type pulse coder.

Now be used for double cross and flow motor-driven three brachium pontis, the nine switching inverter courses of work and describe provided by the invention: described digital signal processor 7 is by the 1st encoder 4, the 2nd encoder 5 obtains the speed/positional signal of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3, obtain the running current information of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3 simultaneously by current detection circuit 6, generate through conversion and computing then and be used to drive all switch element UL on the major loop 1, VL, WL, UM, VM, WM, UH, VH, the pulse-width signal of WH, and promote major loop 1 by drive circuit 8 and carry out work, come the 1st three phase electric machine 2 and the 2nd three phase electric machine 3 are carried out independent electric current and speed closed loop control with this.

More than introduce principle of compositionality and the physical circuit composition that motor-driven three brachium pontis nine its cores of switching inverter are flowed in double cross that be used for provided by the invention, further specified the concrete control method that motor-driven three brachium pontis, nine switching inverters are flowed in double cross that is used for provided by the invention below.

Fig. 6 is used for double cross and flows the corresponding control method flow chart that motor-driven three brachium pontis, nine switching inverters are adopted for provided by the invention, promptly generates the program flow diagram of the related algorithm of corresponding pulse-width signal according to the principle of Fig. 3 and Fig. 2.

Flowcharting shown in Figure 6 in each computing cycle, with regular time section be increment, according to the correlation of carrier wave (triangular wave) signal, the 1st reference signal and the 2nd reference signal, obtain this computational process of relevant pulse width modulation signals value (being the corresponding state of switch element UL, VL, WL, UM, VM, WM, UH, VH, WH) constantly.As shown in Figure 6, provided by the inventionly be used for double cross and flow the control method of motor-driven three brachium pontis, nine switching inverters and comprise the following step that carries out in order:

1) at S1 in the stage, at first the counter of digital signal processor 7 is set to increase and decrease continuously count mode, produces triangular signal, and skew for according to axisymmetric signal of time as carrier signal, enter the S2 stage afterwards;

2) at S2 in the stage, whether judge earlier the carrier signal value greater than zero, when the carrier signal value enters the S3 stage when zero, otherwise enter the S5 stage;

3) at S3 in the stage, try to achieve the currency of the 1st reference signal according to the 1st reference signal curve equation, enter the S4 stage then;

4) at S4 in the stage, at first the currency of above-mentioned the 1st reference signal and the currency of carrier signal are compared, when the currency of the 1st reference signal during greater than the currency of carrier signal, the drive signal of switch element UH, VH, WH is effective, otherwise be invalid, enter the S7 stage afterwards;

5) at S5 in the stage, try to achieve the currency of the 2nd reference signal according to the 2nd reference signal curve equation, enter the S6 stage then;

6) at S6 in the stage, at first the currency of above-mentioned the 2nd reference signal and the currency of carrier signal are compared, when the currency of the 2nd reference signal during less than the currency of carrier signal, the drive signal of switch element UL, VL, WL is effective, otherwise be invalid, enter the S7 stage afterwards;

7) at S7 in the stage, earlier the drive signal of the drive signal of switch element UH, VH, WH and switch element UL, VL, WL is negated respectively, signal after then two being negated carries out the logical "or" computing, and resulting result is the drive signal of switch element UM, VM, WM.

Claims (6)

1. one kind is used for double cross and flows motor-driven three brachium pontis, nine switching inverters, it is characterized in that: describedly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and comprise: major loop (1), the 1st encoder (4), the 2nd encoder (5), current detection circuit (6), digital signal processor (7) and drive circuit (8); Wherein, three-phase brachium pontis and the 1st, the 2nd current transformer (CT1 that major loop (1) is formed by DC power supply (E), filtering capacitor (C), by 9 switch elements (UL, VL, WL, UM, VM, WM, UH, VH, WH), CT2) form, it has two three phase power output ports, is connected with the 2nd three phase electric machine (3) with the 1st three phase electric machine (2) respectively; 1st, the 2nd current transformer (CT1, CT2) be installed in respectively on above-mentioned two three phase power output ports, two output port is connected with two input ports of current detection circuit (6) respectively, is used for detecting respectively the running current value of the 1st three phase electric machine (2) and the 2nd three phase electric machine (3); The 1st encoder (4) and the 2nd encoder (5) are installed in respectively on the main shaft of the 1st three phase electric machine (2) and the 2nd three phase electric machine (3), and two output port is connected with two input ports of digital signal processor (7) respectively; Current detection circuit (6) is the 1st, the 2 current transformer (CT1, input interface circuit CT2), two input ports are respectively with the 1st on it, (CT1's the 2nd current transformer CT2) links to each other, and two output ports join with two input ports of digital signal processor (7) respectively; Digital signal processor (7) is the master controller of inverter, and its output port directly is connected with drive circuit (8); Drive circuit (8) is the required gate drive circuit of switch element (UL, VL, W L, UM, VM, WM, UH, VH, WH), is connected between digital signal processor (7) and the major loop (1).

2. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described major loop (1) comprising: and DC power supply (E), filter capacitor (C), 9 switch elements (UL, VL, WL, UM, VM, WM, UH, VH, WH) and the 1st, the 2nd current transformer (CT1, CT2); Wherein filter capacitor (C) is the power-type filtering capacitor, and it is pressed for dc bus (AB) provides galvanic current after DC power supply (E) parallel connection; 9 switch elements (UL, VL, WL, UM, VM, WM, UH, VH, WH) are formed the three-phase bridge arm jointly, wherein switch element (UL, UM, UH) is composed in series U phase brachium pontis, switch element (VL, VM, VH) is composed in series V phase brachium pontis, switch element (WL, WM, WH) is composed in series W phase brachium pontis, and U, V, W three-phase brachium pontis all are directly parallel on the dc bus (AB); Three phase windings of the 1st three phase electric machine (2) be connected to switch element (UH) and (UM), (VH) and (VM), (WH) and (WM) between; Three phase windings of the 2nd three phase electric machine (3) be connected to switch element (UL) and (UM), (VL) and (VM), (WL) and (WM) between; 1st, the 2nd current transformer (CT1) and (CT2) being installed in respectively on the connecting line of last two the three phase power output ports of major loop (1) and the 1st three phase electric machine (2) and the 2nd three phase electric machine (3).

3. according to claim 2ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described switch element (UL, VL, WL, UM, VM, WM, UH, VH, WH) is IGBT or MOSFET device.

4. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: the model of described digital signal processor (7) is TMS320F28335.

5. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described the 1st encoder (4) and the 2nd encoder (5) are the photoelectric type pulse coder.

6. one kind as claimed in claim 1ly is used for the control method that motor-driven three brachium pontis, nine switching inverters are flowed in double cross, and it is characterized in that: described control method comprises the following step that carries out in order:

1) at S1 in the stage, at first the counter of digital signal processor (7) is set to increase and decrease continuously count mode, produces triangular signal, and skew for according to axisymmetric signal of time as carrier signal, enter the S2 stage afterwards;

2) at S2 in the stage, whether judge earlier the carrier signal value greater than zero, when the carrier signal value enters the S3 stage when zero, otherwise enter the S5 stage;

3) at S3 in the stage, try to achieve the currency of the 1st reference signal according to the 1st reference signal curve equation, enter the S4 stage then;

4) at S4 in the stage, at first the currency of above-mentioned the 1st reference signal and the currency of carrier signal are compared, when the currency of the 1st reference signal during greater than the currency of carrier signal, the drive signal of switch element UH, VH, WH is effective, otherwise be invalid, enter the S7 stage afterwards;

5) at S5 in the stage, try to achieve the currency of the 2nd reference signal according to the 2nd reference signal curve equation, enter the S6 stage then;

6) at S6 in the stage, at first the currency of above-mentioned the 2nd reference signal and the currency of carrier signal are compared, when the currency of the 2nd reference signal during less than the currency of carrier signal, the drive signal of switch element UL, VL, WL is effective, otherwise be invalid, enter the S7 stage afterwards;

7) at S7 in the stage, earlier the drive signal of the drive signal of switch element UH, VH, WH and switch element UL, VL, WL is negated respectively, signal after then two being negated carries out the logical "or" computing, and resulting result is the drive signal of switch element UM, VM, WM.

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