CN102004668A - Providing state storage in a processor for system management mode - Google Patents

Providing state storage in a processor for system management mode Download PDF

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Publication number
CN102004668A
CN102004668A CN2010102774051A CN201010277405A CN102004668A CN 102004668 A CN102004668 A CN 102004668A CN 2010102774051 A CN2010102774051 A CN 2010102774051A CN 201010277405 A CN201010277405 A CN 201010277405A CN 102004668 A CN102004668 A CN 102004668A
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smm
processor
state
smi
storage
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CN102004668B (en
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M·S·纳图
T·兰加拉詹
G·B·多希
S·M·达塔
B·加尼桑
M·J·库马尔
R·S·帕塔萨拉蒂
F·宾斯
R·N·默西
R·C·斯旺森
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Multimedia (AREA)
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Abstract

The invention is named as providing state storage in a processor for system management mode. In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Description

In processor, be provided for the status storage of System Management Mode
Technical field
The present invention relates in processor, be provided for the status storage of System Management Mode.
Background technology
The support of most computers system processor is called the special manipulation mode of System Management Mode (SMM).SMM provides for the transparent different operating environment of operating system (OS) software.This pattern usually is used to carry out the special duty of for example system management, device, power supply and heat management by original equipment manufacturer (OEM).Reliability, availability and serviceability (RAS) function that server is relevant usually uses SMM to realize.Usually by entering SMM to processor transmitting system management interrupt (SMI) message.When confirming SMI, processor is saved in the part of distributing to SMM in the system storage specially with current processor context (being also referred to as the processor preservation state), be called system management random access memory (SMRAM), and carry out SMI handling procedure (handler) code that comprises among the SMRAM.When the SMI handling procedure was finished its operation, it was carried out special (only effective in SMM) and recovers instruction, and this instruction makes processor reload the processor context of being preserved and recover the task that execution is interrupted from SMRAM.
In multicomputer system, generally the SMI information broadcast is arrived all processors.The SMI handling procedure selects a processor (being called SMM master control (monarch)) to come processing events.This processor waits for up to every other processor and joins (rendezvous) in SMM, afterwards treatment S MI incident.Non-main control processor is retained among the SMM, finishes event handling up to master control.When having handled the SMM incident, master control will be withdrawed from SMM with other processors of signalisation.Realize thisly synchronous entering and withdraw from behavior to stop any resource contention between two parallel environments (OS and SMM).That is, if some processors are movable in the OS environment, and remaining processor is movable in the SMM environment simultaneously, and then possible is: they may revise resources shared, and disturb operation each other thus, thereby cause system crash.In addition, some SMM incident can only be handled by certain logic processor or one group of logic processor.Broadcasting has guaranteed that this condition always is satisfied, because all logic processors all will enter SMI.
Therefore, SMI in the multicomputer system handles to be complicated and can to consume all system resources, stops the processing of other useful work, because when processor is among the SMM, it just is not useable for operating system.
Summary of the invention
The invention provides a kind of equipment, comprise: processor core, execution command also enters System Management Mode (SMM), wherein when entering described SMM, described processor core will be stored the active state that exists in the status storage of described processor core in the storage unit of described processor core, and will set up the SMM execution environment in described status storage by inserting the value related with described SMM.
The present invention also provides a kind of method, comprising: responding system management interrupt (SMI) incident, determine whether all threads of carrying out on the processor have entered System Management Mode (SMM) rendezvous mode; And if not, determine that then all the other threads are whether just at executive chairman's flow operation or be in the state that SMI forbids, and if, then use the master control thread to handle described SMI incident, otherwise waited for that before handling described SMI incident all the other threads enter described SMM rendezvous mode at the described long flow operation of all the other thread execution or when being in the state that described SMI forbids.
The present invention also provides a kind of system, comprise: first processor, comprise execution command and enter first nuclear of System Management Mode (SMM), whether the thread of indicating described first nuclear to go up execution is in first designator in the long flow operation, indicate described thread whether to be in second designator and storage unit in the state that system management interrupt (SMI) forbids, wherein when entering described SMM, described first nuclear will be stored the active state that exists in the status storage of described first nuclear also will store the SMM executing state in described status storage in described storage unit, described storage unit is exclusively used in the described active state of storage during described SMM; Second processor, comprise execution command and enter second of described SMM and examine, whether second thread of indicating described second nuclear to go up execution is in first designator in the long flow operation, indicate described second thread whether to be in second designator and second storage unit in the state that described SMI forbids, wherein when entering described SMM, described second nuclear will be stored the active state that exists in the status storage of described second nuclear also will store the SMM executing state in described status storage in described second storage unit, described second storage unit is exclusively used in the described active state of storage during described SMM; And dynamic RAM (DRAM), being coupled to described first and second processors, the part of wherein said DRAM is the system management random access memory (SMRAM) that is used for described system.
Description of drawings
Fig. 1 is the block diagram of processor according to an embodiment of the invention.
Fig. 2 is the block diagram of multicomputer system according to an embodiment of the invention.
Fig. 3 is the process flow diagram of method according to an embodiment of the invention.
Fig. 4 is the process flow diagram of method according to another embodiment of the invention.
Embodiment
In various embodiments, can use memory storage on the tube core (on-die storage) alternative to store the preservation state of each thread that relevant SMM enters/withdraw from as what use the external physical storer.By contrast, for entering and withdraw from SMM, present system depends on the external physical storer.This SMM causes flexible (scaling), the restriction that Performance And Reliability is relevant in the mission critical applications to the dependence of the RAM of system, and can use one embodiment of the invention to avoid.Notice that when using in this article, term " thread " can refer to comprise the hardware thread that is used for the memory storage (for example, register file (register file) and related configuration and status register) of the processor of the architecture states of process context.When using in this article, term " hardware thread " uses with term " logic processor " synonym.Each processor core can comprise a plurality of logic processors, and each logic processor has special-purpose architecture states memory storage, but it shares other nuclear resources (for example front end unit, performance element etc.).
In different realizations, be provided for during SMM that memory storage can be with static RAM (SRAM) (SRAM) on register file in the processor of the little private memory that acts on the preservation state memory storage itself or the tube core on the tube core of preservation state of any active threads of storage.Some processors can comprise SRAM on the tube core of particular task that is used for the picture power management, for example, for example according to low power supply (low power) state (for example, C6 state or other power management operations) of the OS of ACPI (ACPI) state management.In this type of processor, can be reserved in the part among this SRAM of subregion on every thread basis for the SRAM preservation state of each thread.As an example, each logic processor can use the SRAM memory storage of 1 kilobyte (KB) to be used for the SMM preservation state.If given processor can not be exclusively used in the SRAM of this amount the SMM preservation state, can realize that then an embodiment makes it can be utilized as the SRAM that C6 stream (flow) is reserved.In this case, the C6/C7 of SMM inside transformation can be downgraded to lower low power supply status (for example, C3) to guarantee that mutual exclusion ground is used for the SMM state with the SRAM space of sharing and preserves.Some processors are not that the C6 state is preserved and realize special-purpose SRAM, but a part of utilizing last level cache (LLC) on the contrary is to be used for storage of processor state between C6 state storage life.In these processors, the SMM preservation state can be stored among the LLC.
In case preserve, then can be in different modes this inner SMM preservation state of access.For example, can use specific register (MSR) addressing or the backward compatibility mechanism of model on every thread basis to come this internal state of access.Under the usual manner, processor can be at certain system memory addresses access SMM preservation state.Backward compatibility mechanism comprises that seizure (trap) logic processor leaves over the access of storage address and it is redirected to logic in the processor of suitable SRAM position these.If the absolute backwards compatibility of requirement and existing basic input/output (BIOS) software can realize that then this type of is redirected.These MSR can only read or write and follow the constraint related with the SMM preservation state in the SMM pattern.If logic processor need be to the access of the preservation state of another processor, then this can finish through software protocol.
In certain embodiments, MSR (register that model the is specific) potential energy of application specific processor identifier leaf (leaf) (for example, CPUID leaf) or its field or feature enabler is used to enable the use of internal SRAM.With reference now to Fig. 1,, what illustrate is the block diagram of processor according to an embodiment of the invention.As shown in fig. 1, processor 100 can be multistage pipeline system (multi-stage pipelined) out-of order processor.Processor 100 shows so that the various features that the related SMM technology of describing is herein used to be shown with the view of relative simplification.As can be seen, processor 100 can be to comprise a plurality of processor cores 105 and its polycaryon processor that can form on single semiconductor element.Though illustrate with four these nucleoids in the embodiment in figure 1, it should be understood that scope of the present invention is unrestricted in this respect.As also being seen among Fig. 1, can there be additional assembly in the processor 100.For example, can there be integrated Memory Controller (IMC) 108 and static RAM (SRAM) 106.As discussed above, in some implementations, according to one embodiment of the invention, this storer can be used for storing context state, itself otherwise will be stored among the SRAM.Still also have plenty of, processor 100 can comprise last level cache (LLC) 109, and it can be the shared cache of sharing between all processor cores.
As shown in fig. 1, processor 100 comprises front end unit 110, and it can be used for getting the macro instruction that will carry out and the use after a while that its preparation is used for examining.For example, front end unit 110 can comprise that instruction prefetch device, instruction decoder, trace cache (trace cache) are together with microcode store device and micro-order (μ op) memory storage.The instruction prefetch device can be got macro instruction and it is fed to instruction decoder and be carried out by processor being used for to be decoded into primitive (being μ op) from storer.Trace cache can obtain the μ op of decoding and the sequence that its assembling (assemble) one-tenth program is sorted.Certainly, can in front end unit 110, realize additional assembly and feature.
Being coupling between front end unit 110 and the performance element 120 is out of order (OOO) engine 115, and it can be used for receiving micro-order and its preparation is used for carrying out.More properly, OOO engine 115 can comprise that multiple impact damper is to be renamed into logic register on the interior memory location of multiple register file (for example register file 130a) for carrying out required multiple resource and providing micro instruction flow rearrangement and distribution.Register file 130 can comprise the independent register file that is used for integer and floating-point operation.Can there be a plurality of register file 130a-n in attention, and each register file is used for different logic processors.Can also there be additional register, i.e. state and configuration register 135.As can be seen, every group of register 135a-n can be used for different logic processors.These multiple registers can be used for disposing nuclear to be used for different operator schemes and to provide about the thread of execution and the status information of different instruction.
In the example depicted in fig. 1, this type of register can comprise SMM preservation state register 136.In multiple realization, can there be a plurality of these type of registers, each register is related with the given thread that nuclear is gone up operation.As discussed above, but this type of register storage indicator (for example, enable position) is to make the state of thread for example can be stored in the nuclear itself when entering SMM.If this designator is not activated, when then entering SMM, the context of thread will then store SMRAM into.In certain embodiments, this MSR can comprise other positions that can control other processor features.In certain embodiments, can make this register file 135 that comprises designator only is modifiable in SMM, protects it to avoid being carried out the malice change by the outer malice assembly of SMM thus, thereby increases the security and the robustness of system.
As also seen, register file 135 can also comprise one or more SMM status indicator registers 138.This type of indicator register can adopt the form of bitmap or bit vector, and wherein each logic processor has when this logic processor of indication is prohibited from entering SMM or whether this logic processor is in the executory position of long stream.In one embodiment, can there be independent register for each this type of indication.Alternative is can have single register, and can use the existence of the designator of logical combination for these states of each logic processor indication thus.The relevant further details of using these registers is hereinafter described.
Still, can there be multiple resource in the performance element 120, except that other special hardware, comprises for example integer, floating-point and a plurality of data of single instruction (SIMD) logical block with reference to figure 1.The result can be provided to retirement unit (retirement unit) 140, it can be operated to determine whether the performed instruction of can retiring from office effectively, and whether result data can be submitted to the architecture states of processor, or the correct resignation of one or more unusual prevention instructions does not take place.
As shown in fig. 1, retirement unit 140 is coupled to cache memory 150, and in one embodiment, cache memory 150 can be lower level of cache (for example, the L1 high-speed cache), but scope of the present invention is unrestricted in this regard.Equally, performance element 120 can be directly coupled to high-speed cache 150 (not shown in figure 1)s.From cache memory 150, can carry out data communication with upper-level cache, system storage etc.Though with this senior illustrating, it should be understood that in the embodiment in figure 1 scope of the present invention is unrestricted in this regard.For example, can realize other embodiment in the processor in order.
By storing the SMM preservation state into processor, can improve the reliability and the robustness of system in inside.That is, normally the physical storage of resident one group of external dynamic random access memory (DRAM) device thereon of SMRAM meets with memory error easily.Under the situation of no one embodiment of the invention, this outside storer is used up in the SMM operation, and therefore can not rely in erroneous condition.The opposite one embodiment of the invention of using by carry out the SMI handling procedure from non-volatile space when handling mistake, can be improved the reliability of SMRAM storer.For example, in its address memory errors, the SMM handling procedure can move from the more healthy and stronger memory storage as BIOS flash memory or external SRAM.Equally, when the SMM preservation state was inside for processor, the architecture states of this memory storage can only be exposed to outside software by MSR.The micro-architecture state that restores the required processor of machine executing state after the SMM code is carried out " Resume (RSM) " instruction need not to be exposed to external software, because it does not have legal use for this internal machine state.This means that also malicious software code haves no right the micro-architecture state (if the data storage of preserving is arranged in SMRAM, then it will so be done) of access sensitivity, thereby makes machine safer and healthy and strong.
Embodiment can also improve performance and stand-by period.The consistent memory architectures of many server application/operating system right and wrong (NUMA) are optimized and BIOS becomes to make whole SMRAM (it is the contiguous memory scope) be mapped to single slot (socket) with memory configurations usually.Therefore, all SMM preservation states/reset condition operation will look as remote write/long-range reading for all logic CPU, be in the slot of this locality unless these operations are included in SMRAM to it.For the performance evaluation indication that has four slots and respectively have the server configures of 12 nuclears, SMM preservation state write operation can be subjected to interconnecting and the restriction of bandwidth of memory and spending up to 5 microseconds.NUMA optimizes along with application becomes, and processor may be that teleaction service distributes few more impact damper.When that takes place, the operation of SMRAM preservation state write and read will spend even the longer time.Operating system has usually for CPU can be in restriction how long among the SMM, so that keep acceptable real-time performance and avoid overtime on the express network link.Surpass this limitations affect OS responsiveness, applications wait time and even may cause operation system function to lose efficacy.Therefore, use and to have reduced the stand-by period, and therefore make and to serve SMM incident (effective work of SMM) for the other time of SMM handling procedure distribution according to SMM preservation state on the tube core of one embodiment of the invention.
In addition, embodiment can improve scalability.In multicomputer system, when SMI took place, each thread in the system must be stored in its preservation state in preservation state district of its own special use in the external system memory, as being defined and reserved by system bios during system bootstrap.The total amount of reserving as the physical storage in the desired SMRAM of all preservation states space of all threads in the capture systems increases linearly along with the quantity of thread in the system.For having many slots of multinuclear system that symmetrical multithreading is supported, the amount in space is big (and in one embodiment, can be about general 256KB) quite.By for the SMM preservation state provides memory storage on the tube core, can avoid demand, thereby be beneficial to flexible for the SMRAM district of the continuous expansion of holding all nuclears and thread thereof.This also eliminates the necessity of searching and distributing unique and nonoverlapping district for each thread in SMRAM for BIOS.Still also have plenty of, this also preserves the storage protection district and avoids realizing in silicon.In the hot plug situation, the SMM preservation state zone of the architecture definition among the SMRAM is below 1MB.Under the situation of no one embodiment of the invention, when adding new processor, BIOS sets up the storage protection scope, and attacks and/or interference to avoid OS moving out of data.Embodiment eliminates the needs of so doing, because the state of preserving no longer is stored in the visible storer of OS.
With reference now to Fig. 2,, what illustrate is the block diagram of multicomputer system according to an embodiment of the invention.As shown in Figure 2, multicomputer system 200 comprises a plurality of processors 210 1-210 n(being referred to as processor 210).Though in the embodiment of Fig. 2, illustrate, it should be understood that scope of the present invention is unrestricted in this regard with four these type of processors.In the realization shown in Fig. 2, there is non-consistent memory architecture (NUMA) system, make system storage 220 1With 220 3Via interconnection 217 1With 217 3This locality is attached to processor 210 1With 210 3Therefore, processor 210 2With 210 nAccess to storer requires by one of a plurality of point-to-points (PTP) interconnection 215 and processor 210 1With 210 3One of communication.Seen in the realization of Fig. 2, can be the storer 220 of DRAM 1Comprise SMRAM 225.In this NUMA framework, SMRAM 225 is the system management storages that are used for total system.Therefore, under the situation of no one embodiment of the invention, each processor that relevant SMM enters or withdraws from needs preservation/recovery context to this SMRAM 225.This so cause PTP interconnection 215 and interconnection 217 1On a large amount of uses of bandwidth, and increase and be used to stand-by period of entering SMM and withdrawing from from SMM.
Therefore, in various embodiments, except one or more nuclears 212 and integrated Memory Controller 214, each processor 210 also can comprise SRAM 216.In various embodiments, SRAM 216 can be exclusively used in storage SMM preservation state.That is, when the generation systems management interrupt, the context state this locality that is used for a plurality of logic processors of each processor 210 can be stored into its SRAM 216, thereby avoid the needs of communicating by letter for the status information of SMRAM 225.In other embodiments, do not adopt memory storage on the special-purpose tube core, but this context state can be stored on the chip of register file for example in the register or for example in other positions of cache memory.Though illustrate with this specific implementation in the embodiment of Fig. 2, scope of the present invention is unrestricted in this regard.For example, embodiment can also use together with consistent memory cabinet construction system.
With reference now to Fig. 3,, what illustrate is the process flow diagram of method according to an embodiment of the invention.As shown in Figure 3, can manner of execution 300 enter SMM and need not access SMRAM for preservation state information with processing.Note, in order to be easy to discuss, suppose only to have single hardware thread, but in many realizations, a plurality of threads can enter SMM together.As seen in Figure 3, method 300 can begin (frame 310) by the receiving system management interrupt.When receiving this interruption, current active state (for example, the active state of given hardware thread) can be saved in memory storage on the tube core (frame 320).As discussed above, memory storage can be a cache memory etc. on special-purpose SRAM, the SRAM that is used for another purpose (for example, power management states), register storage, the tube core on this tube core.
Still, for example defined according to the processor standard with reference to figure 3, processor state is revised as coupling SMM get the hang of (frame 330).This state comprises value that is used for various control and configuration register and the initial value that is used for register file.This sets up thus by being loaded into the SMM execution environment of preparing to be suitable for the SMM handling procedure in the status storage with the SMM related predetermined value that gets the hang of.When setting up the SMM state, control is delivered to frame 340, and wherein SMM can use from code and the data of SMRAM and carry out (frame 340).Therefore, SMM operation that can carry out desired.Certain scope of the present invention is unrestricted in this regard, and the example of SMM operation comprises power management operations, fault processing operation etc.
Can determine then whether the SMM operation finishes (diamond 350).If no, then the execution among the SMM can continue.If finish, then processor is carried out and is recovered instruction (frame 360).As the result of this instruction, previous state memory storage from tube core can be loaded back the register of processor (frame 370).Then, processor can recover and the execution (frame 380) of restoring the pairing thread of this original state of getting back to active state.Though illustrate with this specific implementation in the embodiments of figure 3, it should be understood that scope of the present invention is unrestricted in this regard.For example, in some implementations, be not to carry out SMM operation from SMRAM (particularly when SMM is used to handle as DRAM mistake wrong), some embodiment can be on the contrary from Nonvolatile memory devices acquisition SMM status information, SMM code and the data of for example flash memory.
As mentioned above, the storage of the silicon of active state can reduce the SMM stand-by period.Embodiment can be by making that can enter SMM more quickly in some cases further reduces the stand-by period, as will now be discussed.
The SMM stand-by period is defined as the every single SMI of processor it is in duration in the SMM environment.There are two mainly to facilitate factor (contributor) for total SMM stand-by period: processor expense and OEM bios code.These times for the treatment of must be remained under the control to avoid spinoff, for example overtime and clock drift the OS environment.Other demand also will require to reduce these and treat the time, and this becomes difficult to achieve.At present, the regulation SMI stand-by period is under about 190 microseconds.Come the more predictable stand-by period of self-application as the expectation that newly uses a model of the Internet-portals data center and effectiveness calculating.As a result, OS supplier is pushing for the further minimizing of SMM in the stand-by period.On the other hand, other technologies have the potential possibility that increases the SMI stand-by period in the past along with the time.For example, the industry of polycaryon processor is advanced mean the SMI handling procedure ever-increasing processor core of quantity of must joining.The new ability based on SMM also places SMM on the stand-by period additional pressure.For example, high-end RAS ability relies on SMM.In addition, some OEM utilize SMM to pay unique power management capabilities to distinguish their product.Known many OEM generate the SMI per second up to 8 times.
Some instruction set architecture (ISA) for example comprise write back (write back) and make illegal command (for example, instruction wbinvd), it makes all cache lines (cache line) invalid and they are write back to storer.These operations can spend to be finished for a long time, for example, and about 10 3To 10 7The individual processor cycle is particularly in the processor of supporting big cache memory sizes.In addition, there is some processor state (for example, C3 and C6 low processor state) that wherein can postpone the SMI response.Generally speaking, these instructions and processor state are called " long flow (longflow) " state, and it is defined as the cycle that expression can spend unusual long number amount and finishes (for example, about 10 3Individual clock) and its can postpone to enter instruction or the process of SMM.In one embodiment, any stream that delay SMM is entered greater than 5 microseconds can be called long stream.With regard to SMM, if one or more logic processor is in the long stream, then it postpones SMM and enters.
As explained above, the SMM master control waits for that the logic processor up to all expectations has all entered SMM.When entering SMM, each processor is provided with its position to indicate it to enter SMM in SMRAM.Master control waits for that the processor up to all expectations all has been provided with their position.When one or more logic processors were in the long stream and enter SMM after a while, it maintained (hold up) SMM master control, and therefore increased the SMM stand-by period.In addition, there is some architecture states of wherein forbidding the SMI incident, for example waits for starting and interrupt (WFS) and TXT dormant state between processor.If the state that OS/BIOS places SMI to forbid one or more logic processors, then it will not enter SMM and take it out of this state up to the OS/BIOS explicitly.Because the SMI incident places SMM with every other processor, so OS can not appear (unmask) SMI.In the case, the SMM master control must rely on the long overtime existence of determining the processor that SMI forbids.These time out delay SMM can merge increases the time quantum that total SMM stand-by period or minimizing can be used for the SMM event handling.
In various embodiments, even under some logic processors are in situation in the long stream, still can avoid the needs overtime to SMM inside.Eliminate this type of and overtimely the average SMM stand-by period can be improved 10-20%, and under worst case, improved several at least milliseconds the SMM stand-by period.
Embodiment relies on the following fact: be in the long stream or state that SMI forbids in the unlikely access shared resource of processor.In addition, this type of processor has unlikely caused SMI, and therefore it participates in handling optional for SMI.Therefore, the SMM master control can be proceeded the SMM processing before this type of processor has entered SMM.
But before continuing, which processor the SMM master control must detect reliably is in the state that length flows and/or SMI forbids.Busy or be in processor in the state that SMI forbids in order to detect in the long stream, embodiment can for example be provided for the designator of these states by bitmap.In one embodiment, this type of indication can provide by the overall visible configuration register that is called LONG_FLOW_INDICATION and SMI_INHIBITED_INDICATION.In this embodiment, can distribute a position to each logic processor in the slot.As an example, these registers can be represented by the register 138 of Fig. 1.The processor microcode relates to and enters state that long stream and SMI forbid and from the realization that it withdraws from, microcode/hardware can be filled these register-bit therein.Some long streams can cause the time of being longer than 5 microseconds, and therefore do not wait for that the ability that is in the processor in these states can provide SMM remarkable saving in the stand-by period.Processor in the future may spend and be used for the SMM microcode more than 5 microseconds and enter stream, and itself can be considered as long stream.The SMM master control can wait for up to all processors and being taken into account, that is, they or add SMM or be in the long stream by report or be in the state that SMI forbids.In order to help this type of to determine, can use the one or more tables (for example bitmap) that are stored among the SMRAM, as described below.
In one embodiment, before the inspection of carrying out indicator register, main control processor is preserved its state and is moved the leading code of SMM (preamble code).These steps can spend easily more than 0.5 microsecond.This duration is much larger than the travel-time that is used for any aloft interruption (in-flightinterrupt), thereby guaranteeing that SMI is delivered to nuclear and reads does not exist race condition between its indicator register.If postpone lessly under some configuration, then main control processor can insert little delay and circulates and remedy (make up).
With reference now to Fig. 4,, what illustrate is the process flow diagram of method according to another embodiment of the invention.Definitely, Fig. 4 illustrates and is used for need not to understand the process flow diagram that fashionable processing enters SMM and withdraws from from SMM at the SMM state at all logic processors.In this way, can avoid with carry out SMM operation before wait for the stand-by period that all logic processors are associated.As seen in Figure 4, method 400 can begin (frame 410) by generating the SMI incident.This SMI incident can propagate into all threads.Notice that in order to be easy to discuss, the thread of supposing Fig. 4 is at single processor slot, but realizing can be used in strides a plurality of slot junction SMM.
Next, can in the SMM indicator chart, designator (frame 420) be set for each thread that enters the SMM rendezvous mode.Be appreciated that thread can at first carry out the warming-up exercise of the multiple SMM of entering, for example, state is preserved, and for example above describes with reference to figure 3.Each thread that enters the SMM rendezvous mode can be provided with designator in the SMM indicator chart that can be stored among the SMRAM.In one embodiment, this figure can be the related bitmap in position of wherein each logic processor and figure, and wherein the logic processor of each slot can be assigned in different sections of figure.Thus, when given thread entered SMM, the position of its correspondence can be set up in the bitmap.Then, can select one of the thread of SMM inside as master control or execution thread (frame 430).In various embodiments, which thread will be definite variableization of execution thread.For example, can select master control (for example, the logic processor 0 on the slot 0) or can dynamically select master control in advance via election contest mechanism.
Still with reference to figure 4, each thread can determine then whether it is selected as master control (diamond 435).If not selected, then this thread can enter dormant state, and wherein its wait master control thread is finished (frame 470) with signalisation.
Therefore, be controlled to be the master control thread and be delivered to frame 440.Here, can determine the ACCOUNTED state for all threads.In one embodiment, except also can being present in the thread existence figure among the SMRAM, this state can also be based on various configurations register, SMM indicator chart.There is figure in this can be the bitmap similar to the SMM indicator chart, and its thread that exists in can being provided with indication mechanism during the SMM initialization.In one embodiment, determining of frame 440 places is the exclusive disjunction of following step-by-step: OR (LONG_FLOW_INDICATION, SMI_INHIBITED_INDICATION, IN_SMM_INDICATION), wherein LONG_FLOW_INDICATION is that status register from the bank bit vector obtains, whether the corresponding thread of its each indication is in the long flow operation, SMI_INHIBITED_INDICATION obtains from the status register of bank bit vector, whether its each corresponding thread of indication is in the state that SMI forbids, and IN_SMM_INDICATION is the SMM indicator chart.Step-by-step or result, ACCOUNTED can be stored in the bitmap (for example, in SMRAM).After this analyzed, control was delivered to diamond 450, wherein can determine the thread for all existence, and whether the ACCOUNTED state is movable (diamond 450).This can and exist relatively coming between the figure to determine based on the result of ACCOUNTED computing.If not, then frame 440 is transmitted back in control.Otherwise control is delivered to frame 455, wherein can treatment S MI incident.Therefore, the SMM code that the master control thread can carry out desired.When the SMM of master control thread execution finished, control was delivered to frame 460.At frame 460, can be with ACCOUNTED state and SMM designator replacement (reset) (frame 460).That is, the master control thread can all be reset the value in these two bitmaps.Then, the master control thread can be signaled other logic processors: they can recover (frame 465) from SMI.In this way, other threads from they etc. release to be recycled.Therefore, at frame 475, all threads can recover from SMM.Though illustrate with this specific implementation in the embodiment of Fig. 4, scope of the present invention is unrestricted in this regard.
Therefore, embodiment makes and realizes the execution of SMM handling procedure and do not have the storer dependence, thereby improves reliability.This mechanism also solves performance related with SMM and scalability issues, makes SMI handle the bottleneck that can avoid becoming in multinuclear/many slots system.Therefore, embodiment avoids having the execution of the dependent SMM code of DRAM, makes the high availability that realizes wherein SMM code diagnosis and correction memory error use a model.
Embodiment also makes and can enter SMM with the stand-by period that reduces when existing logic processor to be in the state that length flows or SMI forbids.By contrast, do not have reliable mechanism to be used for determining that one or more processors are to add SMM after a while or to be in the state that SMM forbids at present, and therefore be provided with than longer overtime of the longest stream mode by the SMM code.This solution except unreliable and be difficult to realize, also increase the SMM stand-by period and reduce the OS real-time response, and use one embodiment of the invention can overcome these shortcomings.
Embodiment can realize in code, and can store on the medium that stores instruction thereon, and described instruction can be used for programing system to carry out these instructions.Medium can include but not limited to: the dish of any kind comprises that floppy disk, CD, CD, solid state drive (SSD), compact-disc ROM (read-only memory) (CD-ROM), compact-disc can rewrite (CD-RW) and magneto-optic disk; Semiconductor device, for example ROM (read-only memory) (ROM), random-access memory (ram) (for example dynamic RAM (DRAM), static RAM (SRAM)), Erasable Programmable Read Only Memory EPROM (EPROM), flash memory, Electrically Erasable Read Only Memory (EEPROM), magnetic or optical card; The medium that perhaps are suitable for any other type of store electrons instruction.
Though the present invention embodiment of relatively limited quantity describes, those skilled in the art will figure out many modifications and variations from it.Claims are intended to contain all these type of modifications and variations that drop in true spirit of the present invention and the scope.

Claims (24)

1. equipment comprises:
Processor core, execution command also enters System Management Mode (SMM), wherein when entering described SMM, described processor core will be stored the active state that exists in the status storage of described processor core in the storage unit of described processor core, and will set up the SMM execution environment in described status storage by inserting the value related with described SMM.
2. equipment as claimed in claim 1, wherein said processor core will expose in the described storage unit canned data with as only specific to the accessible machine of SMM code register (MSR).
3. equipment as claimed in claim 1, also comprise first status register, described first status register storage indication is enabled described processor core and described active state is stored in the described storage unit but not is stored in designator in the system management random access memory (SMRAM).
4. equipment as claimed in claim 3, wherein said first status register can only be upgraded by the agency who carries out among the described SMM.
5. equipment as claimed in claim 3, wherein said processor core is stored in SMM code among the described SMRAM with execution.
6. equipment as claimed in claim 5, wherein as described SMM during with the resolving memory mistake, described processor core will obtain to recover the SMM code and do not obtain described SMM code from described SMRAM from nonvolatile memory.
7. equipment as claimed in claim 3 also comprises second status register, and the logic processor of the described processor core of described second status register storage indication is in the designator in the long flow operation.
8. equipment as claimed in claim 7 also comprises third state register, and described third state register-stored indicates the logic processor of described processor core to be in designator in the state that system management interrupt (SMI) forbids.
9. equipment as claimed in claim 8 also comprises the SMM indicator chart, and described SMM indicator chart is stored the indication of each logic processor of the processor core that has entered described SMM.
10. equipment as claimed in claim 8, wherein said first, second can not be write in described SMM outside with third state register.
11. equipment as claimed in claim 1 also comprises main control processor, described main control processor is carried out described SMM and all junctions among the described SMM of executed of all logic processors of need not described processor core.
12. equipment as claimed in claim 11, the logic processor that wherein said main control processor indicates the logic processor of described processor core to be in first status register in the long flow operation, the described processor core of indication access is in the SMM indicator chart of each logic processor of the processor core that second status register in the state that SMI forbids and indication entered described SMM, and determines whether SMM operation of the request of will carrying out and need not the described junction of all logic processor executeds based on this.
13. equipment as claimed in claim 12, if wherein each logic processor of described processor core has entered described SMM, be in the long flow operation or be in the state that SMI forbids, then described main control processor will be carried out the SMM operation of described request and need not the described junction of all logic processor executeds.
14. a method comprises:
Responding system management interrupt (SMI) incident determines whether all threads of carrying out on the processor have entered System Management Mode (SMM) rendezvous mode; And
If not, determine that then all the other threads are whether just at executive chairman's flow operation or be in the state that SMI forbids, and if, then use the master control thread to handle described SMI incident, otherwise waited for that before handling described SMI incident all the other threads enter described SMM rendezvous mode at the described long flow operation of all the other thread execution or when being in the state that described SMI forbids.
15. method as claimed in claim 14 also is included in the SMM indicator chart and for each thread that enters described SMM rendezvous mode designator is set.
16. method as claimed in claim 15 also comprises:
The designator that first status register of described processor is set is in the long flow operation with the indication thread; And
The designator that second status register of described processor is set is in the state that SMI forbids with the indication thread.
17. method as claimed in claim 16, the wherein said step-by-step exclusive disjunction of determining to comprise between execution described SMM indicator chart, described first status register and described second status register.
18. method as claimed in claim 14, wherein when entering described SMM, described master control thread will be stored the active state that exists in the status storage of described processor also will store the SMM state in described status storage in the storage unit of described processor.
19. a system comprises:
First processor, comprise execution command and enter first nuclear of System Management Mode (SMM), whether the thread of indicating described first nuclear to go up execution is in first designator in the long flow operation, indicate described thread whether to be in second designator and storage unit in the state that system management interrupt (SMI) forbids, wherein when entering described SMM, described first nuclear will be stored the active state that exists in the status storage of described first nuclear also will store the SMM executing state in described status storage in described storage unit, described storage unit is exclusively used in the described active state of storage during described SMM;
Second processor, comprise execution command and enter second of described SMM and examine, whether second thread of indicating described second nuclear to go up execution is in first designator in the long flow operation, indicate described second thread whether to be in second designator and second storage unit in the state that described SMI forbids, wherein when entering described SMM, described second nuclear will be stored the active state that exists in the status storage of described second nuclear also will store the SMM executing state in described status storage in described second storage unit, described second storage unit is exclusively used in the described active state of storage during described SMM; And
Dynamic RAM (DRAM) is coupled to described first and second processors, and the part of wherein said DRAM is the system management random access memory (SMRAM) that is used for described system.
20. system as claimed in claim 19, wherein said DRAM are coupling in wherein said second processor will be by in described first processor and the non-consistent memory architecture (NUMA) that described DRAM communicates by letter.
21. system as claimed in claim 19, whether wherein said second processor will or not store described active state into that described SMRAM responds smi signal but then described active state will be stored in described second storage unit.
22. system as claimed in claim 19, wherein said first processor comprises main control processor, and at least one logic processor of described therein first and second processors of described main control processor does not enter the described SMM rendezvous mode of SMM rendezvous mode and carries out the SMM operation afterwards.
23. the system as claimed in claim 22 is in the state that wherein said at least one logic processor is in the long flow operation or SMI forbids.
24. the system as claimed in claim 22, whether any logic processor that wherein said main control processor indicates any logic processor of described first processor whether to be in first bitmap in the long flow operation, the described first processor of indication access is in the 3rd bitmap of each logic processor of the described first processor that second bitmap in the state that SMI forbids and indication entered described SMM rendezvous mode, and determines whether to carry out described SMM operation when described at least one logic processor does not enter described SMM rendezvous mode based on this.
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CN108351781B (en) * 2015-12-24 2024-01-23 英特尔公司 Method and apparatus for thread synchronization
CN113826072A (en) * 2019-05-16 2021-12-21 微软技术许可有限责任公司 Code update in system management mode
CN113826072B (en) * 2019-05-16 2024-04-26 微软技术许可有限责任公司 Code update in system management mode
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