CN101996115B - Memorizer control method - Google Patents
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- CN101996115B CN101996115B CN 200910171040 CN200910171040A CN101996115B CN 101996115 B CN101996115 B CN 101996115B CN 200910171040 CN200910171040 CN 200910171040 CN 200910171040 A CN200910171040 A CN 200910171040A CN 101996115 B CN101996115 B CN 101996115B
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Abstract
The invention provides a memorizer control method, which is suitable for driving the memorizer of a computer system and used for driving and testing the memorizer by using a basic input output system (BIOS) while starting the computer system, and the memorizer control method aims at testing a plurality of control signals of the memorizer. The memorizer control method comprises the following steps: detecting the effective area of each control signal of the memorizer, judging whether the effective area is more than the predetermined area, regulating the parameters of the control signal in case of one of the effective areas is less than the predetermined area, testing the phase position limitation between two control signals when the effective area is more than the predetermined region, regulating the phase position of effective area of the control signal in case of the control signal is failed in the phase position limitation test and driving the memorizer according to the control signal which is regulated.
Description
Technical field
The present invention is about a kind of memory control methods, and particularly relevant a kind of test procedure for utilizing BIOS carries out the control method of setting parameter to storer.
Background technology
With the element supplier's of PC fast development now, on the market public offering and for the customized various memory module kinds of client a lot, different from the release time with its manufacturer, memory chip, each different storer specification is slightly different.Storer separately is when dispatching from the factory, memory vendor or system assembles factory all will determine the environmental baseline that storer can stable operation one by one, and its environmental baseline can comprise the operating voltage of storer and set (working voltage configuration), drives the various conditions such as intensity (driving strength), time delay parameter (delay time reference), valid interval (active window).Storer need to be under the setting of the best, and the side completes read-write and the store operation of various information with the highest degree of stability.The demand that the initial setting that dispatches from the factory of memory vendor may not meet the internal standard of system assembles factory or use, usually need the business tester of system or research and development slip-stick artist to carry out surveying and finely tuning with manpower and permanent practical experience, can learn the best setting separately of different storeies.
Take PC as example, usually there is Basic Input or Output System (BIOS) (Basic Input/OutputSystem, BIOS) to be responsible for initializes memory module and start selftest etc. on its mainboard.Usually store the various environmental baselines settings that huge look-up table (lookup table) is used for contrasting the different required employings of storer in BIOS.
yet, various semiconductor technologies are constantly weeded out the old and bring forth the new, common storer is also from synchronous dynamic access memory (Synchronous dynamic random access memory, SDRAM) proceed to third generation double data rate Synchronous Dynamic Random Access Memory (Double-Data-Rate Three Synchronous Dynamic RandomAccess Memory, DDR3SDRAM), develop various specification, the time-histories that each new product is released is more and more short, if each new storer is released, electronic product will can make through the flow process that once resets the stable running of storer, manufacturer bears huge design and manufacturing cost with needs, and the inconvenience that also will cause the user to use.
In order to address the above problem, the present invention proposes a kind of memory control methods, to address the above problem.
Summary of the invention
A purpose of the present invention is to provide a kind of memory control methods, is applicable to drive the storer in computer system, and storer is driven by a plurality of control signals.When computer system boot-strap, memory control methods drives and tests these control signals by BIOS.
According to a specific embodiment, memory control methods comprises the following step: this valid interval that (a) detects each control signal; (b) judge that whether these valid intervals are greater than a predetermined interval; (c) if one of them valid interval less than this predetermined interval, carries out a parameter adjustment to these control signals; (d) if these valid intervals greater than this predetermined interval, wherein carry out a phase place limit test between two control signals according to these valid intervals to these control signals; (e) if these control signals wherein two control signals by this phase place limit test, to this wherein these valid intervals of two control signals carry out a phase place adjustment; And (f) these control signals after adjusting according to step (c) or (e) drive this storer.
That is to say, memory control methods of the present invention, can be carried out by the software or the firmware that are stored in BIOS, after computer system boot-strap, storer is tested and adjusted (for example valid interval size and signal phase) according to control signal, automatically control signal is carried out parameter adjustment or phase place adjustment.Computer system can be in the process of start by this, can automatically adjust parameter according to the present storer of using, to guarantee that the memory module that the user is used can stablize running, avoid occuring to drive the situation of storer, and can save the time cost that manufacturer carries out system research and development.
Can be further understood by the following detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Figure 1 shows that the process flow diagram according to memory control methods in a specific embodiment of the present invention.
Figure 2 shows that the details implementing procedure figure according to memory control methods in a specific embodiment of the present invention.
Figure 3 shows that the signal mode schematic diagram according to two control signals in a specific embodiment of the present invention.
Figure 4 shows that the signal mode schematic diagram when carrying out the phase place limit test between two control signals in a specific embodiment of the present invention.
Embodiment
See also Fig. 1 and Fig. 2.Figure 1 shows that the process flow diagram according to memory control methods in a specific embodiment of the present invention.Figure 2 shows that the details implementing procedure figure according to memory control methods in a specific embodiment of the present invention.
Memory control methods of the present invention is applicable to the storer in computer system, when computer system boot-strap, respectively storer is driven and tests by the driver in BIOS and test procedure, and the parameter of storer is adjusted.The parameter of storer is driven by a plurality of control signals usually, in practical application, these control signals can comprise command-control signal (Command, CMD), clock control signal (Clock, CLK), read control signal (Read DQ), read clock control signal (Read DQS), the one at least in a group that write control signal (Write DQ) and write clock control signal (Write DQS) form.These control signals defined storer minimum clock unit, execute the task at present, read and the various states such as write operation, required control signal when operating for storer.
Each control signal has respectively one section valid interval (active window).See also Fig. 3, Figure 3 shows that the signal mode schematic diagram according to two control signals in a specific embodiment of the present invention.As the example in Fig. 3, two control signals can be respectively the first control signal (for example clock control signal Clock) and the second control signal (for example command-control signal Command).The first control signal has a valid interval window1, and the second control signal has a valid interval window2.In practical application, the valid interval of each control signal should have certain size at least, to guarantee the storer normal operation.
It is the main process step of memory control methods of the present invention shown in Fig. 1.As shown in Figure 1, the present invention is execution in step S100 at first, is written into one group of preset value to drive this storer, and the step S100 that wherein is written into preset value herein can be completed by further details step.See also Fig. 2, in an embodiment, step S100 can comprise step S100a, step S100b and step S100c.Execution in step S100a is written into an original frequency to this storer.The sign frequency (labeled frequency) that provides of manufacturer for example.Execution in step S100b is written into an initialization voltage and is set to this storer, for example in practical application, the storer of corresponding DDR3 framework can adopt the memory bus operating voltage (memory bus voltage) of 1.5V and the Memory Controller operating voltage (memory controller voltage) that the corresponding P55 of Intel platform can adopt 1.1V.Execution in step S100c makes the control signal (such as CMD, CLK, Write DQ, Write DQS, Read DQ, ReadDQS, CTRL etc.) of storer be written into an initialize signal phase place to this storer.Wherein, be written in step S100 preset value take the practice that drives this storer only as starting simply the basic function of storer, facilitate follow-up test and adjustment, be in stable mode of operation but the method that there is no guarantees storer.
The practice that is written into preset value in step S100 is known by the people of known technology, can utilize look-up table or static firmware set and reach, and does not separately give unnecessary details at this.
Then, the memory control methods execution in step S102 in the present invention detects the size of the valid interval (as the window1 in Fig. 3, window2) of each control signal.The valid interval of control signal refers to herein, when control signal was set at particular job voltage level (for example representing the high level of positive logic or the low level of negative logic) and use control or drive corresponding circuit module, the signal that this section control signal is maintained on this level continued interval.For example in Fig. 3, control signal (CMD, CLK) is promoted to high level at specific time point respectively, and enters valid interval (window1, window2) to control or to drive its corresponding circuit.
In actual applications, in order to pursue higher calculation process speed, circuit adopts high signal switching frequency mostly, make the valid interval of control signal that more and more short trend be arranged, yet many circuit components (such as buffer, operational amplifier etc.) itself still have nonideal time delay, and for example line delay (wiring delay) or logic gate postpone (gate delay).If the valid interval of control signal is too of short duration, when several layers of logical circuit of control signal process, just might postpone or the asynchronous problems such as distorted signals or signal omission that occur of system clock because of element.
Then, execution in step S104 judges that whether the valid interval of these control signals is greater than a predetermined interval.In this embodiment, this predetermined interval can be by the deviser according in reality test experience or special algorithm, and storer can keep stable necessary interval magnitude numerical value to decide.If the valid interval of control signal all greater than this predetermined interval, represents that storer can operate under steady state (SS).
Otherwise if the valid interval that has arbitrary control signal less than this predetermined interval, represents that this moment, storer still played pendulum, at this moment, but memory control methods execution in step S106 of the present invention carries out parameter adjustment to these control signals.
See also Fig. 2, parameter adjustment of the present invention (step S106) can further be completed by several steps, and for example signal driver intensity, operating voltage are set and the adjustment of time parameter.
In embodiment as Fig. 2, central step S104 judges the valid interval of these control signals less than predetermined interval, and when entering the parameter adjustment of step S106.But memory control methods execution in step S106b of the present invention, adjust the signal driver intensity (driving strength) of one of them control signal, control signal CMD herein, CLK, Write DQ, Write DQS, Read DQ, the signal driver intensity such as Read DQS, CTRL all can attempt adjusting, can again pass through step S102 and S104 after each the adjustment, then detect and judge that whether these valid intervals are greater than this predetermined interval after adjusting.
That is to say, the signal driver intensity of the different control signals of memory control methods of the present invention repeated attempt adjustment always is until each valid interval has all been attempted adjusting greater than the signal driver intensity of this predetermined interval or each control signal all.
What need special instruction is that before execution in step S106b, memory control methods of the present invention can further comprise step S106a, prejudges the driving intensity that whether still has control signal and not yet attempts adjusting.If the driving intensity of all control signals has attempted adjusting all, but still the valid interval that can't make the control signal after adjustment is greater than this predetermined interval, memory control methods of the present invention just can automatically switch other parameters are adjusted, the efficient of adjusting to accelerate judgement.
In embodiment as Fig. 2, if step S106a judgement has been completed trial all to the adjustment of signal driver intensity, but still the valid interval that has a control signal is less than predetermined interval.But the present invention follows execution in step S106d, attempts adjusting the operating voltage setting of storer itself.In practical application, the operating voltage of storer is set the one at least comprise in the group that memory bus operating voltage (memory bus voltage) parameter and Memory Controller operating voltage (memorycontroller voltage) parameter form.These parameters have certain specification limit, may damage storer or make the storer abnormal if exceed this scope.For example the specification limit of memory bus operating voltage parameter can be 1.5V between 2.0V, and Memory Controller operating voltage parameter can be between 1.1V～1.5V.Step S106d sets corresponding to adjusting operating voltage in specification limit.
Can again pass through step S102 and S104 after each the adjustment, then detect and judge that whether these valid intervals are greater than this predetermined interval after adjusting.That is to say, memory control methods of the present invention repeated attempt is always adjusted different operating voltage settings, until each valid interval has all been attempted complete greater than the setting of the operating voltage in this predetermined interval or specification limit all.
In addition, as shown in Figure 2, before execution in step S106d, memory control methods of the present invention also can further comprise step S 106c, prejudges the operating voltage that whether still has in specification limit and sets not yet trial adjustment.If all attempted adjusting, but still can't make valid interval greater than this predetermined interval, just memory control methods of the present invention can automatically switch other parameters are adjusted.
As shown in Figure 2, if trial has been completed in the adjustment that step S106c judgement is set operating voltage all, but still the valid interval that has a control signal is less than predetermined interval.But the present invention follows execution in step S106f, attempts adjusting one of them time parameter of storer itself.in practical application, the time parameter of storer can comprise a plurality of memory latency parameters, these memory latency parameters comprise the clock period (TCL), row is with reference to arriving row with reference to delay parameter (timing of RAS to CAS Delay, TRCD), row is with reference to pre-charge delay parameter (timing of RASPrecharge, TRP) and valid till pre-charge delay parameter (active to RAS precharge delay, TRAS) one at least in a group that forms, in practical application, these memory latency parameters represent respectively the required time of each mode of operation of storer.When step S106f is performed, the time parameter of storer is adjusted one by one.
Can again pass through step S102 and S104 after each the adjustment, detect and judge that whether these valid intervals are greater than this predetermined interval after adjusting.That is to say, but memory control methods repeated attempt of the present invention is adjusted different time parameters, until each valid interval has all been attempted adjusting complete greater than this predetermined interval or each time parameter all.
Whether in addition, as shown in Figure 2, before execution in step S106f, memory control methods of the present invention also can further comprise step S106e, prejudge to still have time parameter not yet to attempt adjusting.If all attempted adjusting, but still can't make valid interval greater than this predetermined interval, in this embodiment, entered other follow-up test adjustment programme.But memory control methods of the present invention is not adjusted (signal driver intensity, operating voltage setting, time parameter) with above-mentioned three kinds of tests and is limited, and also can comprise adjustment and test to more other parameters in other embodiment.In addition, the decision logic order of these three kinds test adjustment also is not limited with this embodiment, and in other embodiment, its sequencing is interchangeable or independent separately.
In addition, in another embodiment, when the time parameter also attempts adjusting complete, but still can't make valid interval greater than this predetermined interval the time, memory control methods passback error messages of the present invention, or prompting deviser or user redefines to judge the reference value of the predetermined interval of valid interval, and re-executes subsequently steps flow chart (S102-S106).
On the other hand, when the valid interval of control signal during all greater than predetermined interval, memory control methods of the present invention is execution in step S108, according to valid interval to wherein carrying out phase place limit test (phase range test) between two control signals.See also Fig. 2 and Fig. 4, Figure 4 shows that the signal mode schematic diagram when carrying out the phase place limit test between two control signals in a specific embodiment of the present invention.In this embodiment, phase test herein can utilize step S108a that two control signals are tested.For instance, two control signals herein can be the first control signal (for example CMD) and the second control signal (for example CLK), this first control signal has positive edge PE1 and negative edge NE1, this second control signal has positive edge PE2, wherein valid interval indication of the present invention is the positive edge of control signal and the interval between negative edge, as the valid interval window1 of the first control signal in Fig. 4.
In the embodiment of Fig. 4, step S108a obtains the left phase place limit rL of the valid interval window1 of relative the first control signal of the second control signal according to the time interval of the positive edge PE1 of the positive edge PE2 of this second control signal and the first control signal.Meanwhile, according to the time interval of the negative edge NE1 of the positive edge PE2 of the second control signal and the first control signal, obtain the right phase place limit rR of the valid interval window1 of relative the first control signal of the second control signal.Then, if this left phase place limit rL equals this right phase place limit rR, produce the test result of passing through the phase place limit test.Otherwise, if left phase place limit rL is not equal to the right phase place limit of rL rR, produce the test result of not passing through the phase place limit test.
Then as shown in Figure 1, memory control methods of the present invention is execution in step S110, judges whether by limit test.In concrete instance, be the step S110a in Fig. 2, whether equaling this right phase place limit rR according to left phase place limit rL judges, if left phase place limit rL equals right phase place limit rR, but execution in step S114 is written into the control signal driving storer of adjusting in above-mentioned steps later, to guarantee the degree of stability of storer.
If left phase place limit rL is not equal to right phase place limit rR, need execution in step S112 to carry out the phase place adjustment to these two control signals.Phase place is herein adjusted the details step and is also seen also Fig. 2.At first but execution in step S112a judges the magnitude relationship between left phase place limit rL and right phase place limit rR, as rL＜rR in Fig. 4, at this moment, but execution in step S112b shifts to an earlier date a unit with the phase place of the first control signal, and relative the second control signal that refers in advance herein shifts to an earlier date the phase place of the first control signal.Otherwise, if rL＞rR, but execution in step S112c, relative the second control signal is with the phase delay of the first control signal.
When the phase place of first and second control signal in step S112 after adjusting, get back to step S108, again the first control signal and the second control signal are carried out the phase place limit test, judge whether the first control signal and the second control signal are by this phase place limit test (whether left phase place limit rL equals right phase place limit rR), repeated execution of steps S108 is to step S112, until should the group control signal pass through the phase place limit test.
By this, but two control signals of associated are arranged on assurance function, wherein the positive edge PE2 triggered time point of the second control signal is sitting at the central authorities of the valid interval window1 of the first control signal.By this, can guarantee that relevant control signal has been completed switching when positive edge triggers, avoid occuring that time that two control signals switch too approaches and the swinging of signal stable condition brought.The example of above-mentioned phase place limit test and adjustment in addition, to be applied between CMD and CLK control signal as example, in practical application, also can between Write DQ and Write DQS, between ReadDQ and Read DQS, between CLK and Write DQS and between CLK and Read DQS or have the signal combination of association to test and adjust on various function, not be limited for example with of the present invention.
In above-mentioned giving an example, the situation that triggers for positive edge describes, but the present invention is not as limit.In another embodiment, memory control methods of the present invention also can correspondingly be born the situation that edge triggers.Maximum difference is, it can according to the time interval of the positive edge of the negative edge of the second control signal and the first control signal, obtain the left phase place limit; And obtain the right phase place limit according to the time interval of the negative edge of the negative edge of the second control signal and the first control signal.Other details practice and previous embodiment are roughly the same, separately do not give unnecessary details at this.
In sum, memory control methods of the present invention can be carried out by the software or the firmware that are stored in BIOS, after computer system boot-strap, according to the control signal characteristic (for example valid interval size and signal phase) of storer, automatically control signal is carried out parameter adjustment or phase place adjustment.Computer system can be adjusted to stable setting value according to the storer that uses automatically in the process of start by this, can stablize running to guarantee the memory module that the user is used, and can save the time cost that manufacturer carries out system research and development.
By the above detailed description of preferred embodiments, hope can be known description feature of the present invention and spirit more, and with above-mentioned disclosed preferred embodiment, category of the present invention is limited.On the contrary, its objective is that hope can contain in the category that is arranged in claim of the present invention of various changes and tool equality.
Claims (10)
1. a memory control methods, be applicable to drive storer, and described storer is driven by a plurality of control signals, and each control signal has respectively valid interval, it is characterized in that described memory control methods comprises the following step:
Detect the valid interval of each control signal of described storer;
Judge that whether described these valid intervals are all greater than predetermined interval;
If wherein any valid interval is less than described predetermined interval, described these control signals are carried out parameter adjustment, with the valid interval of adjusting described these control signals all greater than described predetermined interval;
If described these valid intervals are all greater than described predetermined interval, described these control signals comprise the first control signal and the second control signal, to carrying out the phase place limit test between described the first control signal and described the second control signal;
If described the first control signal and described the second control signal not by described phase place limit test, are carried out the phase place adjustment to described the first control signal and described the second control signal; And
Drive described storer according to described these control signals after adjusting.
2. memory control methods according to claim 1 is characterized in that wherein said parameter adjustment comprises the following step:
Adjust the signal driver intensity of one of them control signal;
After test is adjusted, whether described these valid intervals are all greater than described predetermined interval; And
If wherein any valid interval is less than described predetermined interval, repeat the signal driver intensity of described these one of them control signals of control signal is adjusted and tested.
3. memory control methods according to claim 1, is characterized in that wherein said storer has operating voltage and sets, and described operating voltage is set and met specification limit, and wherein said parameter adjustment comprises the following step:
Adjusting described operating voltage in described specification limit sets;
After test is adjusted, whether described these valid intervals are all greater than described predetermined interval; And
If wherein any valid interval is less than described predetermined interval, repeats described operating voltage is set in described specification limit and adjust and test.
4. memory control methods according to claim 3 is characterized in that wherein said operating voltage sets the one at least that comprises in the group that memory bus operating voltage parameter and Memory Controller operating voltage parameter form.
5. memory control methods according to claim 1, is characterized in that wherein said storer has a plurality of time parameters, and wherein said parameter adjustment comprises the following step:
Adjust one of them described these time parameter of described storer;
After test is adjusted, whether described these valid intervals are all greater than described predetermined interval; And
If wherein any valid interval is less than described predetermined interval, repeat one of them described these time parameter of described storer are adjusted and tested.
6. memory control methods according to claim 5, it is characterized in that wherein said these time parameters comprise a plurality of memory latency parameters, described these memory latency parameters comprise clock period, row reference to being listed as with reference to delay parameter, row with reference to pre-charge delay parameter and the one at least in the group that the pre-charge delay parameter forms.
7. memory control methods according to claim 1, it is characterized in that described the first control signal has the first positive edge and negative edge, described the second control signal has the second positive edge, the described valid interval of described the first control signal is between the described first positive edge and described negative edge, and wherein said phase place limit test comprises the following step:
According to the time interval of the described first positive edge of the described second positive edge of described the second control signal and described the first control signal, obtain the left phase place limit of the described valid interval of relatively described the first control signal of described the second control signal;
According to the time interval of the described negative edge of the described second positive edge of described the second control signal and described the first control signal, obtain the right phase place limit of the described valid interval of relatively described the first control signal of described the second control signal;
If judge that the described left phase place limit equals the described right phase place limit, the described valid interval that produces relatively described the first control signal of described the second control signal has passed through the test result of phase place limit test; And
If judge that the described left phase place limit is not equal to the described right phase place limit, the described valid interval that produces relatively described the first control signal of described the second control signal does not pass through the test result of phase place limit test.
8. memory control methods according to claim 1, it is characterized in that wherein said the first control signal has positive edge and the first negative edge, described the second control signal has the second negative edge, the described valid interval of described the first control signal is between described positive edge and the described first negative edge, and wherein said phase place limit test comprises the following step:
According to the time interval of the described positive edge of the described second negative edge of described the second control signal and described the first control signal, obtain the left phase place limit of the described valid interval of relatively described the first control signal of described the second control signal;
According to the time interval of the described first negative edge of the described second negative edge of described the second control signal and described the first control signal, obtain the right phase place limit of the described valid interval of relatively described the first control signal of described the second control signal;
If judge that the described left phase place limit equals the described right phase place limit, the described valid interval that produces relatively described the first control signal of described the second control signal has passed through the test result of phase place limit test; And
If judge that the described left phase place limit is not equal to the described right phase place limit, the described valid interval that produces relatively described the first control signal of described the second control signal does not pass through the test result of phase place limit test.
9. memory control methods according to claim 1 is characterized in that when described the first control signal and described the second control signal wherein said phase place adjustment comprises the following step during not by described phase place limit test:
Relatively described the second control signal postpones or shifts to an earlier date described the first control signal;
Described the first control signal and described the second control signal are carried out described phase place limit test; And
Judge that whether described the first control signal and described the second control signal are by described phase place limit test, if not by described phase place limit test, repeat relatively described the second control signal and postpone or shift to an earlier date described the first control signal and carry out described phase place limit test.
10. memory control methods according to claim 1, the one at least in the group that it is characterized in that wherein said these control signals comprise command-control signal, clock control signal, read control signal, read clock control signal, write control signal and write clock control signal forms.
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| CN1368684A (en) * | 2001-01-31 | 2002-09-11 | 伟格科技股份有限公司 | Frequency multiplying method and system for CPU |
| US6574739B1 (en) * | 2000-04-14 | 2003-06-03 | Compal Electronics, Inc. | Dynamic power saving by monitoring CPU utilization |
| CN1776568A (en) * | 2005-11-28 | 2006-05-24 | 北京中星微电子有限公司 | Task-based dynamic CPU working frequency regulating method and system |
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| US6078518A (en) * | 1998-02-25 | 2000-06-20 | Micron Technology, Inc. | Apparatus and method for reading state of multistate non-volatile memory cells |
| US6574739B1 (en) * | 2000-04-14 | 2003-06-03 | Compal Electronics, Inc. | Dynamic power saving by monitoring CPU utilization |
| CN1368684A (en) * | 2001-01-31 | 2002-09-11 | 伟格科技股份有限公司 | Frequency multiplying method and system for CPU |
| CN1776568A (en) * | 2005-11-28 | 2006-05-24 | 北京中星微电子有限公司 | Task-based dynamic CPU working frequency regulating method and system |
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| C06 | Publication | ||
| PB01 | Publication | ||
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