CN101963936B

CN101963936B - Method for storing working parameter state by DSP (Digital Signal Processor) equipment through CF (Compact Flash) memory card

Info

Publication number: CN101963936B
Application number: CN2010102767378A
Authority: CN
Inventors: 鲁剑锋
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2010-09-09
Filing date: 2010-09-09
Publication date: 2012-09-19
Anticipated expiration: 2030-09-09
Also published as: CN101963936A

Abstract

The invention relates to a method for storing a working parameter state by DSP (Digital Signal Processor) equipment through a CF (Compact Flash) memory card, belonging to the technical field of electronics. The method comprises the following steps of: connecting a data bus of the DSP with an FPGA (Field Programmable Gate Array); sending working parameter state data transmitted by the DSP to the CF memory card through the FPGA; and storing the received data in real time by the CF memory card, wherein the CF memory card works in a Memory mode. The invention has the advantages that even if the DSP equipment is suddenly subjected to the interruption of power supply, the data stored in the CF storage card cannot be influenced; and when the DSP has a fault, analysis can be carried out according to the data in the CF storage card to position the position of the fault.

Description

DSP equipment is through the method for Compact Flash store operational parameters state

Technical field

The invention belongs to art of electronics, relate to a kind of memory interface technology, relate in particular to the method for a kind of DSP equipment through Compact Flash store operational parameters state.

Background technology

Current in fields such as signal Processing, Digital Image Processing; The applied more and more of DSP (digital signal processor), the complicacy of task is also increasingly high, and this just needs the DSP equipment running to be got off by effective real time record; Be convenient to operating personnel or programming personnel data and DSP buffer status through analytic record; To reach the purpose of judging the DSP equipment running, just as the black box of aircraft, state of flight that can the real time record aircraft; Be used for the ex-post analysis work of aircraft, guarantee the flight safety of aircraft.

More common DSP equipment does not generally have the equipment of duty real-time storage at present; When it breaks down, need professional programming personnel to connect special-purpose developing engine and debug, on computer interface, show operation result, like this with other computing machines; The duty with DSP that can not be real-time is reacted to the programming personnel; And, use developing engine to debug, can not reflect the state of DSP equipment running hours; Make that the general operation personnel can't be through observing, location of fault appears in the location.Therefore, provide the method for a kind of analysis and judgement DSP equipment failure position imperative.

Summary of the invention

In order to solve the existing in prior technology problem, the present invention provides the method for a kind of DSP equipment through Compact Flash store operational parameters state, is used to analyze, locate the abort situation of DSP equipment.

The technical scheme that technical solution problem of the present invention is adopted is following:

DSP equipment comprises the steps: through the method for Compact Flash store operational parameters state

1) FPGA (PLD) sends the EXT5 look-at-me to DSP, and DSP receives this look-at-me, and the response interrupt request; The running parameter status data of self chip is configured; Use the CLK2 clock as synchronously, the addressing of address that utilizes address wire A2 to send as data to A11 arrives seven address wires of D7 through D0; The running parameter status data is sent to FPGA, the transport process of completion status data from DSP to FPGA;

2) FPGA receives the status data that transmits from DSP, and the status data of DSP is stored among the inner buffer memory of FPGA, reads the BUSY signal of Compact Flash then;

3) when the BUSY of the Compact Flash that reads signal is low level; FPGA carries out read-write control to Compact Flash; The write signal of Compact Flash is put low, Compact Flash is carried out write operation, CE, OE, WAIT signal are put high level; Enable Compact Flash, and the data line that writes data and the address wire of gating Compact Flash;

4) according to the operation requirement of Compact Flash, dispose the status register of Compact Flash, confirm to write the starting cluster position of data, accomplish the initial configuration of Compact Flash;

5) will be buffered in the inner DSP running parameter status data of FPGA and be written in the Compact Flash, accomplish the storage of DSP running parameter status data.

The invention has the beneficial effects as follows: adopt method of the present invention, even DSP equipment generation sudden power can not have influence on the data that are stored in the Compact Flash the inside yet; When DSP breaks down, can analyze according to the data in the Compact Flash, the fault location position.

Description of drawings

Fig. 1 is the method schematic diagram of DSP equipment of the present invention through Compact Flash store operational parameters state.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the present invention is explained further details.

The present invention utilizes the data bus of DSP and FPGA to link, and through FPGA the video data that DSP sends is sent to Compact Flash, and Compact Flash is operated in the Memory pattern, and the data that obtain are carried out real-time storage.Like this, even DSP equipment generation sudden power can not have influence on the data that are stored in the Compact Flash the inside yet.

At first, utilize dsp chip, the buffer status data of dsp chip are read, carry out packing data, every bag data are 8, and the data number need add up according to register; Then, the every 20MS of fpga chip reads the packet of a dsp chip, carries out buffer memory, is written among the Compact Flash.

As shown in Figure 1, DSP of the present invention adopts the TMS320C6416 chip, and it is a kind of of company of Texas Instruments (TI) the TMS320C6000 series processors of producing.The TMS320C6000 series DSP is the high-performance digital signal processor that TI company produces, and is designed to Harvard's bus structure of revising in the sheet, the TMS320C6416A6E3 that present embodiment is selected for use, and the main clock frequency of DSP is 600MHz.

FPGA adopts the EP2C20 chip, and it is the FPGA FPGA that ALTERA company produces, and it can carry out programming Control according to the purposes difference.

Compact Flash adopts is that the capacity of SanDisk company is the CompactFlash storage card of 16GB, and memory rate is 30MB/S, and it can carry out real-time storage with the data in the FPGA.

Utilize the internal storage of EP2C20 chip to be barricaded as the dual-ported memory of a 1K*8bit.EP2C20 utilizes the CLK2 of TMS320C6416, and (this pin is 6416 output clock pin; The output clock is 150MHz; Insert the clock pin of EP2C20) the frequency division clocking, the one tunnel through six frequency divisions generation 25MHz clock signal, supplies with Compact Flash and makes clock signal; One the tunnel through frequency division counter generation 50Hz clock signal; Supply with the EXT5 pin of TMS320C6416; The EXT5 pin is the interruption 5 of TMS320C6416; When the upper edge of clock is come then; Cause the interruption (interrupt 5) of TMS320C6416, TMS320C6416 knows that new interruption arrives interrupting 5, TMS320C6416 interrupt in 5 through D0---D7 and A2---A11 ,/WR ,/control lines such as RD deposit the external interface buffer status of current DSP and the status data of DSP inner buffer distribution register in the dual-ported memory of the 1K*8bit in EP2C20 inside.CE2 is used for the chip selection signal end of the dual-ported memory of the inner 1K*8bit of EP2C20.The CE of Compact Flash, OE, Wait, REG are the control pins of Compact Flash; Be used for the initialization control of Compact Flash and writing of data; BUSY is the feedback of status signal of Compact Flash; When the BUSY signal was " 1 ", the expression Compact Flash was writing data, when the BUSY signal is " 0 ", representes that the Compact Flash data write completion.The dual-ported memory of EP2C20 uses the clock of 25MHz; At first control signals such as CE, OE, Wait, REG; Accomplish the configuration that the Compact Flash data write register; Data with dual-port send in the Compact Flash through data line then, realize that Compact Flash is written to the status register data in real time of DSP equipment in the middle of the Compact Flash.

When DSP receives after the EXT5 of fpga chip look-at-me, the response interrupt request is with DSRs such as the duty of chip itself, parameters; Use the CLK2 clock as synchronously, the addressing of address that utilizes address wire A2 to send as data to A11 arrives seven address wires of D7 through D0; Send the data to fpga chip, when sending data, the write data sign of DSP/WR zero setting level; Read data sign/RD puts high level, and DSP sends the chip selection signal CE2 gating of data port.Like this, status data has just been accomplished the transmission course from DSP to FPGA.After fpga chip EP2C20 accomplishes Data Receiving; The status data of DSP is stored among the inner buffer memory of FPGA, reads the BUSY signal of Compact Flash then, BUSY is the status signal of Compact Flash; When the BUSY signal is high level; Compact Flash is duty in the card, at this time, is invalid to the write operation of Compact Flash.When the BUSY of Compact Flash signal is low level, can operate Compact Flash.At first, fpga chip carries out read-write control to Compact Flash, puts the write signal of Compact Flash low; Compact Flash is carried out write operation; CE, OE, WAIT signal are put high level, enable Compact Flash, and the data line that writes data and the address wire of gating Compact Flash.According to the operation requirement of Compact Flash, dispose the status register of Compact Flash then, confirm to write the starting cluster position of data.Promptly utilize A0 to four address wire gatings of A3 different address, come on the same stage status register is not carried out gating, simultaneously, the data of configuration are write register through data bus DD0 to DD7.Accomplish the initial configuration of Compact Flash, just can be written in the Compact Flash to DD7 to A3 address wire and data bus DD0 through A0, accomplish the storage of data being buffered in the inner dsp chip status data of FPGA.Whenever write one group of status data, the memory address of Compact Flash will add up 1 successively on initialized starting cluster address, guarantees the continuous different position that is stored in of data, to avoid losing and covering of data, simultaneously, also makes things convenient for reading of data.

After the Compact Flash storage is full, program will begin that the data in the Compact Flash are carried out data from the starting cluster address and cover, and new data will be replaced original storage data.

After the DSP device powers down, Compact Flash takes off from DSP equipment, through the card reader of standard; Use a computer and just can read the data of storing in the Compact Flash; Through analyzing these data, thereby the programming personnel can recognize DSP equipment work situation, fault location promptly and accurately.

Claims

1.DSP equipment is characterized in that through the method for Compact Flash store operational parameters state this method comprises the steps:

1) FPGA sends the EXT5 look-at-me to DSP, and DSP receives this look-at-me, and the response interrupt request; The running parameter status data of self chip is configured; Use the CLK2 clock as synchronously, the addressing of address that utilizes address wire A2 to send as data to A11 arrives seven address wires of D7 through D0; The running parameter status data is sent to FPGA, the transport process of completion status data from DSP to FPGA;

5) will be buffered in the inner DSP running parameter status data of FPGA and be written in the Compact Flash, accomplish the storage of DSP running parameter status data;

Above-mentioned DSP is TMS320C6416A6E3, and the main clock frequency of DSP is 600MHz; FPGA is the EP2C20 chip; Compact Flash is that the capacity of SanDisk company is the CompactFlash storage card of 16GB, and memory rate is 30MB/S.

2. DSP equipment as claimed in claim 1 is through the method for Compact Flash store operational parameters state; It is characterized in that; After the storage of the status data in the Compact Flash is full; To begin that the data in the Compact Flash are carried out data from the starting cluster address and cover, new data are replaced original storage data.