CN101938285A - Method and device for realizing RRU data interface by using ping-pong operation - Google Patents
Method and device for realizing RRU data interface by using ping-pong operation Download PDFInfo
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Abstract
The invention relates to a method and a device for realizing an RRU data interface by using ping-pong operation. The structure of the device is as follows: a baseband processing module is respectively connected with a laser, a baseband and an intermediate-frequency (IF) data interface module; an IF processing module is respectively connected with a radio frequency (RF) processing module, the baseband and the intermediate-frequency data interface module; the RF processing module is connected with a receiving and transmitting antenna; and a CPU is connected with the baseband and the IF) data interface module. The method of the invention utilizes ping-pong operation to process interface data stream, compared with the traditional implementation method, seamless cache and process of data can be realized by using pipeline operation of the ping-pang operation on the data stream, in addition, space resources required by data cache can be saved, thereby improving the instantaneity of processing, greatly saving the internal resources of an FPGA, being favorable for lowering the cost of an RRU and minimizing the RRU, and being favorable for improving the stability and reliability of the system.
Description
Technical field
The present invention relates to a kind of method and apparatus that in the remote radio unit (RRU) system, utilizes ping-pong operation to realize the RRU data-interface.
Background technology
In distributed base station system, RRU (Remote Radio Unit, remote radio unit (RRU)) effect mainly is the modulation of finishing from the baseband carrier data to radiofrequency signal, and demodulation from radiofrequency signal to the baseband carrier data, the relation of itself and BBU (Base Band Unit, Base Band Unit) as shown in Figure 1.
Along with being growing more intense of development of Communication Technique and market competition, each operator has proposed more and more higher requirement to RRU, except product function is reliable and stable, also require software and hardware to support smooth upgrade, compatible strong, with low cost, environmental protection etc., this just makes RRU must adopt Software Radio platform on implementation, utilizes Digital Signal Processing to realize various functions.Because advantages such as FPGA (field programmable gate array) has technical maturity, cost performance height, the series of products compatibility is good, realization is simple have flexibly become indispensable important devices in the Software Radio platform.In the RRU product, in order to give full play to the advantage of FPGA, usually utilize it to realize the various interface design, comprise optical interface, control interface, data-interface etc., traditional implementation method be utilize that inner a large amount of register, look-up table or the FIFO resources such as (push-up storages) of FPGA realizes that the conversion of clock zone, time delay precision are adjusted, functions such as the string of data flow and conversion.Than higher, therefore cost also can increase many these methods, nor is beneficial to system's miniaturization, and then adds to the difficulties for the stability of a system, also is unfavorable for the location of problem after going wrong for the RRU resource requirement.
In the data-interface of RRU, base band and intermediate frequency data interface are relatively more crucial technology points that influences the RRU system stability.
Summary of the invention
Purpose of the present invention is in order to overcome the defective that conventional method exists, stability and reliability with assurance base band and intermediate frequency data interface are core, provide a kind of highly versatile, framework to realize simple, as to help the stability of a system method and apparatus that utilizes ping-pong operation realization RRU data-interface.The inventive method adopts ping-pong operation docking port data to handle, with respect to traditional implementation method, ping-pong operation can be realized the seamless buffer memory and the processing of data to the pipeline system operation of data flow, can save metadata cache requisite space resource in addition, therefore improve the real-time of handling and saved the FPGA internal resource greatly, help RRU to reduce cost and miniaturization, help improving the stability and the reliability of system.
Technical scheme of the present invention is:
Figure 2 shows that device block diagram of the present invention, utilize ping-pong operation to realize that the device of RRU data-interface mainly is made of following components: laser, FPGA, CPU, radio frequency processing module, reception transmitting antenna, FPGA comprises baseband processing module, intermediate frequency process module, base band and intermediate frequency data interface module.This device characteristic is: baseband processing module links to each other with the intermediate frequency data interface module with laser, base band respectively, the intermediate frequency process module links to each other with the intermediate frequency data interface module with radio frequency processing module, base band respectively, the radio frequency processing module links to each other with the reception transmitting antenna, and CPU links to each other with the intermediate frequency data interface module with base band; The function of each module is as follows: laser is finished the mutual conversion of photosignal; CPU is responsible for providing carrier wave to select and the time delay configuration information by the register of configuration FPGA to it, and FPGA is normally worked according to configuration information; FPGA is responsible for handling in real time the data of uplink downlink, realizes the base band/intermediate frequency conversion of data; The radio frequency processing module realizes the intermediate frequency/radio frequency conversion of data; In the up-downgoing data link processes of binary channels RRU system, the base band of FPGA and intermediate frequency data interface module are responsible for the translation function of the string of completion logic mapping, time delay adjustment, channel data stream and conversion, clock zone.
Utilize ping-pong operation to realize the method for RRU data-interface, two of up-downgoings independently data link adopt different ping-pong operation flow processs respectively, it is characterized in that:
Uplink direction, concrete operations flow process as shown in Figure 3, base band and intermediate frequency data interface module adopt the concrete steps of ping-pong operation as follows:
(1) CPU is responsible for providing carrier wave selection, time delay configuration information by the register of configuration FPGA to it;
(2) data of the intermediate frequency process module of FPGA two passages that will be received from reception antenna by the radio frequency processing module are finished parallel base band and the intermediate frequency data interface module exported to after the intermediate frequency process;
(3) base band of FPGA and intermediate frequency data interface module are made as a chip period with data caching period, and etc. the time be divided into two data processing cycles; Select for use two-port RAM as data buffer storage unit, and to divide equally in data buffer storage unit be two data buffer areas, the space of two-port RAM is reached single channel and is supported more than the twice of maximum carrier number; The ping-pong operation handling process: will be in a chip of parallel input of first metadata cache cycle two channel data streams be assigned to the 1st data buffer area of two data buffer units, the data of the data selection unit of output passage one in the 1st data buffer area of first data processing cycle sense data buffer unit 1 of second data caching period, the data of data selection unit passage two in the 1st data buffer area of the second data processing cycle sense data buffer unit 2 of output, simultaneously the metadata cache of next chip is advanced the 2nd data buffer area of two data buffer units, when the data for the treatment of the 1st data buffer area run through, the data of next chip have just been write, can continuously the data of next chip be read the 3rd data caching period, to advance the 1st data buffer area of two data buffer units at the metadata cache of next chip simultaneously, so processing that need not pause, the conversion of intermediate frequency/base band clock zone is finished in the final also string conversion that realizes data simultaneously; The logic carrier data that serial is put is separated according to the configuration information of the relation of logic carrier wave and physical carrier and CPU and is mapped to the corresponding physical carrier wave, buffer memory advances a two-port RAM, is transferred to baseband processing module after finishing the time delay adjustment according to the configuration information of CPU;
(4) baseband processing module of FPGA is with base band physical carrier and up C﹠amp; The M data are uploaded to BBU according to optical interface standard agreement framing after the conversion of laser electric light;
Down link direction, concrete operations flow process as shown in Figure 4, base band and intermediate frequency data interface module adopt the concrete steps of ping-pong operation as follows:
(1) CPU is responsible for providing carrier wave to select and the time delay configuration information by the register of configuration FPGA to it;
(2) baseband processing module of FPGA parses base band physical carrier data according to the optical interface standard agreement in downstream data flow;
(3) downgoing baseband of FPGA and intermediate frequency data interface module extract the physical carrier that belongs to this RRU by the configuration information of CPU, physical carrier are mapped on the logic carrier wave of down link according to the relation of logic carrier wave and physical carrier; The logic carrier wave buffer memory that serial is put advances in the two-port RAM, finishes the time delay adjustment according to the time delay configuration information that CPU provides; The downgoing baseband of ping-pong operation handling process: FPGA and intermediate frequency data interface module are made as a chip period with data caching period, and etc. the time be divided into two data processing cycles, at first the data allocations of a chip internal channel one is arrived the 1st data buffer area of data buffer storage unit 1 at first data processing cycle input traffic processing unit in first metadata cache cycle, the data allocations of a chip internal channel two is arrived the 1st data buffer area of data buffer storage unit 2 at second data processing cycle input traffic processing unit, second data caching period with the data of the 1st data buffer area of two cache modules data selection unit parallel read-out by output, simultaneously with the 2nd data buffer area of data allocations to two cache module of two passages in next chip, when the data for the treatment of the 1st buffer area run through, the data of next chip have also just been write, the data selection unit of output was read the data parallel of the 2nd data buffer area of two cache modules continuously the 3rd data caching period, to the 1st data buffer area of metadata cache to two cache module of next chip more simultaneously again, so repeat string and the conversion that ping-pong operation is realized channel data stream, finish the conversion of base band/intermediate frequency clock zone simultaneously, with and two channel datas of line output give the intermediate frequency process module;
(4) the intermediate frequency process module of FPGA is carried out intermediate frequency process to the channel data of parallel input, realizes conversion from if-to-rf by the radio frequency processing module, after transmitting antenna send;
The step (2) of carrying out the uplink downlink direction simultaneously can realize the parallel processing of the up-downgoing separated links of base band and intermediate frequency data interface module to step (4).
The present invention has the advantages that framework is realized simply, portability is strong, resource is few, cost is low, help the stability of a system.
Description of drawings
Fig. 1 is the position view of RRU and base station in the distributed base station system.
Fig. 2 realizes block diagram for RRU system base band and the intermediate frequency data interface module that the inventive method adopted.
Fig. 3 is the process chart of the ping-pong operation of up link employing.
Fig. 4 is the process chart of the ping-pong operation of down link employing.
Fig. 5 is the key step flow chart that the inventive method adopted.
Fig. 6 is a 10ms wireless frame structure schematic diagram in the distributed base station system.
Fig. 7 is the sequential chart of ping-pong operation method base band downlink data link and DUC interface.
Fig. 8 is the sequential chart of ping-pong operation method base band up data link and DDC interface.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
Shown in Figure 2, device of the present invention mainly is made of following components: laser, FPGA, CPU, radio frequency processing module, reception transmitting antenna, and FPGA comprises baseband processing module module, intermediate frequency process module, base band and intermediate frequency data interface module; This device characteristic is: baseband processing module links to each other with the intermediate frequency data interface module with laser, base band respectively, the intermediate frequency process module links to each other with the intermediate frequency data interface module with radio frequency processing module, base band respectively, the radio frequency processing module links to each other with the reception transmitting antenna, and CPU links to each other with the intermediate frequency data interface module with base band; The function of each module is as follows: laser is finished the mutual conversion of photosignal; CPU is responsible for providing carrier wave to select and the time delay configuration information by the register of configuration FPGA to it, and FPGA is normally worked according to configuration information; FPGA is responsible for handling in real time the data of uplink downlink, realizes the base band/intermediate frequency conversion of data; The radio frequency processing module realizes the intermediate frequency/radio frequency conversion of data; In the up-downgoing data link processes of binary channels RRU system, the base band of FPGA and intermediate frequency data interface module are responsible for the translation function of the string of completion logic mapping, time delay adjustment, channel data stream and conversion, clock zone.
According to flow chart shown in Figure 5, in the down link direction, the baseband processing module of FPGA parses the baseband carrier data according to the optical interface standard agreement, and the physical carrier that the baseband carrier that parses is put by serial is formed, and comprises corresponding frame synchronizing signal and enable signal; Select information according to the carrier wave that CPU issues, the physical module carrier wave in the base band is mapped on the logic carrier wave of corresponding downstream link; The result who measures according to the upper strata chain-circuit time delay disposes through CPU and finishes the time delay adjustment; Finish sending to the intermediate frequency process module after the conversion of the string of channel data and conversion and clock zone and carry out intermediate frequency process by ping-pong operation, finish radio frequency processing by the radio frequency processing module again; At uplink direction, by the radio frequency processing module IQ data that reception antenna receives are become intermediate frequency by radio frequency, send to base band and intermediate frequency data interface module after being drawn into base band data by the intermediate frequency process module again, base band and intermediate frequency data interface module send to baseband processing module after at first finishing conversion channel data stream and string conversion and clock zone by ping-pong operation; The carrier wave that base band and intermediate frequency data interface module issue according to CPU is selected information, realizes the separate mapping of logic carrier wave to physical carrier, and the result by the measurement of upper strata chain-circuit time delay disposes through CPU and finishes the time delay adjustment; The baseband processing module of FPGA is with base band physical carrier data and up C﹠amp; The M data send to BBU according to optical interface standard agreement framing through laser.
In uplink downlink was handled, the definite and ping-pong operation method of physical carrier and logic carrier wave relation was a key point of the present invention, is elaborated below.
The relation of logic carrier wave and physical carrier is determined by the data rate of base band minimal physical carrier wave and the relation of intermediate frequency data processing speed.For the downlink data link, suppose that the intermediate frequency data processing speed is N a times of minimal physical carrier data speed, represent the data of one of them logic carrier wave so with regard to corresponding every N minimal physical carrier data, select to isolate logic carrier number P by carrier wave again.For up data link, the data of each logic carrier wave will be equivalent to the data of N optical fiber physical carrier, and P logic carrier wave be corresponding to be mapped as P*N optical fiber physical carrier.
Ping-pong operation is a disposal skill that usually is applied to data flow con-trol, the handling process of the ping-pong operation that adopts according to up link of the present invention shown in Figure 3: the input data selection unit in base band and the intermediate frequency data interface module is assigned to two data buffer units with two channel parallel input traffics, data buffer storage unit selects to use two-port RAM, the space of data buffer storage unit need be reached more than the twice of the maximum number of supporting carrier wave of single channel, and to divide equally in each data buffer storage unit be two data buffer areas; The metadata cache cycle is a chip period, simultaneously is divided into two data processing cycles each caching period; The data flow of two passage inputs is cached to the 1st data buffer area of two data buffer units respectively in first caching period by the data selection unit of input; The 2nd the data buffer area that the data flow of two passage inputs is cached to two data buffer units by the data selection unit of input respectively of second caching period, simultaneously the data that will be buffered in passage one in the 1st the data buffer area of data buffer storage unit 1 at first data processing cycle of second caching period are delivered to the Data Stream Processing unit by the data selection unit of output, and second data processing cycle will be buffered in the 1st the data buffer area of data buffer storage unit 2 passage two data and deliver to the Data Stream Processing module by the data selection unit of output; The 3rd caching period is cached to the data flow of two passage inputs respectively by the data selection unit of input the 1st data buffer area of two data buffer units, simultaneously the 3rd caching period first data processing cycle data that will be buffered in passage one in the 2nd the data buffer area of data buffer storage unit 2 deliver to the Data Stream Processing module by the data selection unit of output, second data processing cycle delivered to the Data Stream Processing unit with the data that are buffered in passage two in the 2nd the data buffer area of data buffer storage unit 2 by the data selection unit of output; The Data Stream Processing unit is to two channel data serials output and carry out subsequent treatment.The handling process of the ping-pong operation that adopts according to down link of the present invention shown in Figure 4: two channel datas that serial is put in the Data Stream Processing unit of base band and intermediate frequency data interface module are cached to two data buffer units respectively, first data processing cycle of first caching period with input traffic in the data of passage one be cached to the 1st data buffer area of data buffer storage unit 1 by the data selection unit of input, second data processing cycle is cached to the data of passage in the input traffic 2 the 1st data buffer area of data buffer storage unit 2 by the data selection unit of input; Second data caching period, the data parallel that is buffered in the 1st data buffer area of each data buffer storage unit is delivered to passage one output processing unit, simultaneously first data processing cycle of second caching period is cached to the 2nd data buffer area of data buffer storage unit 1 with the data of passage in the input traffic one by the data selection unit of input, and second data processing cycle is cached to the data of passage two in the data flow of input the 2nd data buffer area of data buffer storage unit 2 by the data selection unit of input; The 3rd data caching period, the data parallel that is buffered in the 2nd data buffer area of each data buffer storage unit is delivered to passage two output processing units, simultaneously first data processing cycle of the 3rd caching period is cached to the 1st data buffer area of data buffer storage unit 1 with the data of passage in the input traffic one by the data selection unit of input, and second data processing cycle is cached to the data of passage two in the data flow of input the 1st data buffer area of data buffer storage unit 2 by the data selection unit of input; Passage one, passage two output processing units are exported to the intermediate frequency process module with the data of two passages simultaneously.Base band uplink and downlink parallel link carries out pipeline system by aforesaid operations to data stream to be handled, and finishes the seamless buffer memory and the processing of data, and ping-pong operation also helps to improve the precision that time delay is adjusted in the RRU system to the real-time of data processing simultaneously.
When specific embodiment was 2.4576Gbps as the data rate of interface protocol in 3G, its 10ms wireless frame structure comprised in the base band data that 48 data speed are the physical carrier of 1.28Mbps as shown in Figure 6.In downlink data link direction, in TD-SCDMA A+B RRU system, A frequency range maximum can be supported 12 carrier wave P=12, B frequency range maximum can be supported 9 carrier wave P=9, base band and intermediate frequency data interface rate are 1.28Mbps in the down link, and be identical with physical carrier data rate minimum in the optical interface, at this moment N=1, each corresponding group physical carrier data are just represented one of them logic carrier data, i.e. binary channels totally 21 effective physical carrier.In TD-LTE RRU system, data link can be supported four kinds of different bandwidth of 5M/10M/15M/20M, under the situation of 5M bandwidth, base band and intermediate frequency data interface rate are 7.68Mbps in the down link, be equivalent in the optical interface 6 times of minimum physical carrier data rate, N=6, data represented one of them logic carrier data of per 6 physical carrier that this moment is corresponding; Base band and intermediate frequency data interface rate are 15.36Mbps during the 10M bandwidth, this moment N=12, corresponding data represented one of them logic carrier data of per 12 physical carrier; Base band and intermediate frequency data interface rate are 23.04Mbps during the 15M bandwidth, this moment N=18, corresponding data represented one of them logic carrier data of per 18 physical carrier; Base band and intermediate frequency data interface rate are 30.72Mbps during the 20M bandwidth, this moment N=24, corresponding data represented one of them logic carrier data of per 24 physical carrier.TD-LTE RRU system is the antenna diversity dual channel system, single passage maximum can be supported the 20M bandwidth, with the 20M bandwidth situation is example, the binary channels maximum can be supported carrier number P=2, promptly select 48 corresponding fiber carriers of back wherein should have P*N=48 physical carrier effective mutually by the carrier wave mapping, have 48 effective carrier data in each chip this moment, and the system clock of baseband portion is 122.88MHz, and the system clock of intermediate-frequency section is 184.32MHz.After baseband processing module carried out the carrier wave mapping and postpones to handle, 24 of the front physical carrier were the valid data of passage one in each chip, 24 valid data that physical carrier is a passage two of back.The handling process of the ping-pong operation that adopts according to down link, be assigned to two data buffer units during with data of each chip etc., and it is two data buffer areas that data buffer storage unit is divided equally, the passage one that serial in the chip is put and the data of passage two are separated the 1st the data buffer area that writes two-port RAM respectively by ping-pong operation earlier, treat that the data placement in the chip finishes, export to the intermediate frequency process module with regard to the data parallel that begins to read simultaneously from two-port RAM two passages, the data of passage one that serial in the next chip is put and passage two are separated the 2nd the data buffer area that writes two-port RAM respectively by ping-pong operation simultaneously.When running through Deng the data of a chip, the data of next chip have also just been write, so continue the data of next chip are read, write clock and adopt Base-Band Processing clock 122.88MHz, read clock and adopt intermediate frequency process clock 184.32MHz, in order to guarantee the read-write data speed coupling of two-port RAM, note also the sequencing control that read-write enables, because this moment, the speed of interface was 30.72Mbps, so the read-write data speed of two-port RAM also should be 30.72Mbps, concrete sequential as shown in Figure 7.
In the up data link direction, in WCDMA RRU system, the data of up link are the data of binary channels 8 carrier waves, its each logic carrier data speed all is 7.68Mbps, be N=6, P=8, the optical fiber physical carrier data that it is 1.28Mbps that the data after the reorganization are equivalent to 48 data speed.In TD-LTE RRU system, base band and intermediate frequency data interface rate are 7.68Mbps when the 5M bandwidth, N=6, base band and intermediate frequency data interface rate are 15.36Mbps during the 10M bandwidth, this moment N=12, by that analogy, base band and intermediate frequency data interface rate are 30.72Mbps during the 20M bandwidth, at this moment N=24.In TD-LTE RRU dual channel system, the 20M bandwidth situation is an example, the intermediate frequency process module is exported to baseband processing module with the data parallel of two passages, baseband processing module is according to the handling process of the ping-pong operation of up link employing, two parallel channel data streams are write two-port RAM respectively, when treating that single pass 24 carrier waves write the 1st data buffer area of two-port RAM respectively in the chip, begin to read from the two-port RAM of placing passage one carrier data earlier, run through after 24 carrier data of a chip again from 24 carrier data of this chip of the two-port RAM read-out channel two of placing passage nd carrier data, data with next chip write the 2nd data buffer area of two-port RAM simultaneously, when running through Deng the carrier data of this chip of passage two, the data of next chip have also just been write, so continue 48 carrier waves of next chip are read, baseband processing module is recombinated two channel datas, the optical fiber physical carrier data that it is 1.28Mbps that the data after the reorganization are equivalent to 48 data speed.Write clock and adopt Base-Band Processing clock 184.32MHz, reading clock is Base-Band Processing clock 122.88MHz, in like manner in order to guarantee the read-write data speed coupling of two-port RAM, also note the sequencing control that read-write enables, because this moment, the speed of interface was 30.72Mbps, so the read-write data speed of two-port RAM also should be 30.72Mbps, concrete sequential as shown in Figure 8.
RRU system for other data rates and other standards in the interface protocol also is fit to handle with these apparatus and method, just caching period and the cache module space of distributing during the different and ping-pong operation of the relation of logic carrier wave and physical carrier is different, does not just elaborate at this.
Above-mentioned example of the present invention is only realized for explanation method of the present invention; anyly be familiar with the people of this technology in the disclosed technical scope of the present invention; all can expect its variation and replacement easily, so protection range of the present invention should be encompassed within the protection range that is limited by claims all.
Claims (2)
1. utilize ping-pong operation to realize the device of RRU data-interface, mainly constitute: laser by following components, FPGA, CPU, the radio frequency processing module, receive transmitting antenna, FPGA comprises baseband processing module, the intermediate frequency process module, base band and intermediate frequency data interface module, it is characterized in that: baseband processing module respectively with laser, base band links to each other with the intermediate frequency data interface module, the intermediate frequency process module respectively with the radio frequency processing module, base band links to each other with the intermediate frequency data interface module, the radio frequency processing module links to each other with the reception transmitting antenna, and CPU links to each other with the intermediate frequency data interface module with base band; The function of each module is as follows: laser is finished the mutual conversion of photosignal; CPU is responsible for providing carrier wave to select and the time delay configuration information by the register of configuration FPGA to it, and FPGA is normally worked according to configuration information; FPGA is responsible for handling in real time the data of uplink downlink, realizes the base band/intermediate frequency conversion of data; The radio frequency processing module realizes the intermediate frequency/radio frequency conversion of data; In the up-downgoing data link processes of binary channels RRU system, the base band of FPGA and intermediate frequency data interface module are responsible for the translation function of the string of completion logic mapping, time delay adjustment, channel data stream and conversion, clock zone.
2. utilize ping-pong operation to realize the method for RRU data-interface, two of up-downgoings independently data link adopt different ping-pong operation flow processs respectively, it is characterized in that:
Uplink direction, base band and intermediate frequency data interface module adopt the concrete steps of ping-pong operation as follows:
(1) CPU is responsible for providing carrier wave selection, time delay configuration information by the register of configuration FPGA to it;
(2) data of the intermediate frequency process module of FPGA two passages that will be received from reception antenna by the radio frequency processing module are finished parallel base band and the intermediate frequency data interface module exported to after the intermediate frequency process;
(3) base band of FPGA and intermediate frequency data interface module are made as a chip period with data caching period, and etc. the time be divided into two data processing cycles; Select for use two-port RAM as data buffer storage unit, and to divide equally in data buffer storage unit be two data buffer areas, the space of two-port RAM is reached single channel and is supported more than the twice of maximum carrier number; The ping-pong operation handling process: will be in a chip of parallel input of first metadata cache cycle two channel data streams be assigned to the 1st data buffer area of two data buffer units, the data of the data selection unit of output passage one in the 1st data buffer area of first data processing cycle sense data buffer unit 1 of second data caching period, the data of data selection unit passage two in the 1st data buffer area of the second data processing cycle sense data buffer unit 2 of output, simultaneously the metadata cache of next chip is advanced the 2nd data buffer area of two data buffer units, when the data for the treatment of the 1st data buffer area run through, the data of next chip have just been write, can continuously the data of next chip be read the 3rd data caching period, simultaneously the metadata cache of next chip is advanced the 1st data buffer area of two data buffer units, so processing that need not pause, the conversion of intermediate frequency/base band clock zone is finished in the final also string conversion that realizes data simultaneously; The logic carrier data that serial is put is separated according to the configuration information of the relation of logic carrier wave and physical carrier and CPU and is mapped to the corresponding physical carrier wave, buffer memory advances a two-port RAM, is transferred to baseband processing module after finishing the time delay adjustment according to the configuration information of CPU;
(4) baseband processing module of FPGA is with base band physical carrier and up C﹠amp; The M data are uploaded to BBU according to optical interface standard agreement framing after the conversion of laser electric light;
Down link direction, base band and intermediate frequency data interface module adopt the concrete steps of ping-pong operation as follows:
(1) CPU is responsible for providing carrier wave to select and the time delay configuration information by the register of configuration FPGA to it;
(2) baseband processing module of FPGA parses base band physical carrier data according to the optical interface standard agreement in downstream data flow;
(3) downgoing baseband of FPGA and intermediate frequency data interface module extract the physical carrier that belongs to this RRU by the configuration information of CPU, physical carrier are mapped on the logic carrier wave of down link according to the relation of logic carrier wave and physical carrier; The logic carrier wave buffer memory that serial is put advances in the two-port RAM, finishes the time delay adjustment according to the time delay configuration information that CPU provides; The downgoing baseband of ping-pong operation handling process: FPGA and intermediate frequency data interface module are made as a chip period with data caching period, and etc. the time be divided into two data processing cycles, at first the data allocations of a chip internal channel one is arrived the 1st data buffer area of data buffer storage unit 1 at first data processing cycle input traffic processing unit in first metadata cache cycle, the data allocations of a chip internal channel two is arrived the 1st data buffer area of data buffer storage unit 2 at second data processing cycle input traffic processing unit, second data caching period with the data of the 1st data buffer area of two cache modules data selection unit parallel read-out by output, simultaneously with the 2nd data buffer area of data allocations to two cache module of two passages in next chip, when the data for the treatment of the 1st buffer area run through, the data of next chip have also just been write, the data selection unit of output was read the data parallel of the 2nd data buffer area continuously the 3rd data caching period, to the 1st data buffer area of metadata cache to two cache module of next chip more simultaneously again, so repeat string and the conversion that ping-pong operation is realized channel data stream, finish the conversion of base band/intermediate frequency clock zone simultaneously, with and two channel datas of line output give the intermediate frequency process module;
(4) the intermediate frequency process module of FPGA is carried out intermediate frequency process to the channel data of parallel input, realizes conversion from if-to-rf by the radio frequency processing module, after transmitting antenna send;
The step (2) of carrying out the uplink downlink direction simultaneously can realize the parallel processing of the up-downgoing separated links of base band and intermediate frequency data interface module to step (4).
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| CN102742317A (en) * | 2011-11-25 | 2012-10-17 | 华为技术有限公司 | Communication system, communication method and communication apparatus |
| CN102740511A (en) * | 2011-04-12 | 2012-10-17 | 中兴通讯股份有限公司 | Baseband radio frequency interface based on software defined radio (SDR) and application method thereof |
| CN102882585A (en) * | 2012-09-05 | 2013-01-16 | 中国科学院对地观测与数字地球科学中心 | Data recording and playback device, system and method |
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| CN102740511A (en) * | 2011-04-12 | 2012-10-17 | 中兴通讯股份有限公司 | Baseband radio frequency interface based on software defined radio (SDR) and application method thereof |
| WO2012139389A1 (en) * | 2011-04-12 | 2012-10-18 | 中兴通讯股份有限公司 | Baseband radio frequency interface based on software defined radio and application method therefor |
| CN102740511B (en) * | 2011-04-12 | 2016-01-20 | 深圳市中兴微电子技术有限公司 | A kind of baseband radio interface based on software radio and application process thereof |
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| CN102742317A (en) * | 2011-11-25 | 2012-10-17 | 华为技术有限公司 | Communication system, communication method and communication apparatus |
| US9210612B2 (en) | 2011-11-25 | 2015-12-08 | Huawei Technologies Co., Ltd. | Communication system, method and device |
| CN102882585B (en) * | 2012-09-05 | 2014-10-15 | 中国科学院对地观测与数字地球科学中心 | Data recording and playback device, system and method |
| CN102882585A (en) * | 2012-09-05 | 2013-01-16 | 中国科学院对地观测与数字地球科学中心 | Data recording and playback device, system and method |
| CN103702374B (en) * | 2014-01-13 | 2017-03-29 | 武汉邮电科学研究院 | A kind of switched system and method for supporting LTE network topology |
| CN104467906A (en) * | 2014-12-01 | 2015-03-25 | 沈阳工业大学 | Super-speed digital signal wireless transceiver |
| CN105760922A (en) * | 2014-12-17 | 2016-07-13 | 联芯科技有限公司 | Radio frequency (RF) interface control method and digital RF interface controller |
| CN105760922B (en) * | 2014-12-17 | 2018-12-21 | 联芯科技有限公司 | The method of radio frequency interface control and digital radio frequency interface controller |
| CN105813093A (en) * | 2016-03-30 | 2016-07-27 | 武汉虹信通信技术有限责任公司 | Separated antenna coverage system for multi-service signal deep coverage and networking |
| CN105813093B (en) * | 2016-03-30 | 2019-10-25 | 武汉虹信通信技术有限责任公司 | Separated antenna for the covering networking of multi-service signal depth covers system |
| CN111241033A (en) * | 2020-01-10 | 2020-06-05 | 武汉先同科技有限公司 | Realization method of code spraying data storage system based on FPGA (field programmable Gate array) double-port RAM (random Access memory) ping-pong operation |
| CN113093623A (en) * | 2021-04-08 | 2021-07-09 | 浙江大辰北斗科技有限公司 | Navigation anti-interference method |
| CN117856809A (en) * | 2024-03-07 | 2024-04-09 | 成都玖锦科技有限公司 | SoC-based high-speed scanning circuit and broadband digital receiver |
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