CN101931416A - Parallel hierarchical decoder for low density parity code (LDPC) in mobile digital multimedia broadcasting system - Google Patents
Parallel hierarchical decoder for low density parity code (LDPC) in mobile digital multimedia broadcasting system Download PDFInfo
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Abstract
The invention discloses a parallel hierarchical decoder for a low density parity code (LDPC) in a mobile digital multimedia broadcasting system. The parallel hierarchical decoder adopts a partially parallel structure and is characterized in that: 1) each line of a check matrix is taken as a layer, check nodes of each layer are updated sequentially for each variable node, the variable node is updated after the check nodes of each layer are updated and a value obtained after updating is used in the updating of the check nodes of a next layer until an iteration is finished; and 2) the check nodes of a plurality of lines are selected for parallel computation under the condition that 1) is met, so that a partially parallel decoding structure can be realized. Compared with the conventional LDPC decoder, the parallel hierarchical decoder has the advantages of reducing average iteration times needed when a decoding convergence condition [bit error rate (BER) is less than or equal to 10 to 6] is met under the condition of the same signal to noise ratio and the same maximum iteration time, achieving higher error code performance, greatly increasing decoding throughput rate or effectively reducing power consumption and improving the error code performance of a system.
Description
Technical field
The present invention relates to the mobile digital multi-media broadcast communication technical field, low-density checksum in particularly a kind of mobile digital multi-media broadcast communication system (Low-Density Parity-Check, LDPC) Ma parallel hierarchical decoder.
Background technology
Data always can be introduced various noises in the process of transmission and storage, for example synchronization loss in random noise, the demodulating process and the multipath effect in the wireless transmission etc.Because the existence of these noises has limited message transmission rate and transmission quality under certain bandwidth greatly.Along with the continuous progress of modern communication technology, communication system direction higher to throughput gradually, that capacity is bigger and reliability is higher develops, and error control coding also thereby obtained widely using.The LDPC sign indicating number is a very important class sign indicating number in the error control code, adds glug (RobertGallager) in 1963 by the Robert
[1]Propose.Empirical tests, the LDPC sign indicating number can reach the error performance apart from shannon limit 0.0045dB, and simultaneously ldpc decoder is because check matrix structural, and has intrinsic decoding concurrency, can satisfy the requirement of high speed high-throughput.Thereby at aspects such as expansion new generation of wireless communication system service range, raising video broadcast system throughputs, the LDPC code table has revealed excellent performance and application prospect.
Yet along with mobile terminal device (as notebook computer and mobile phone etc.) plays an increasingly important role in wireless communication system, people have also proposed more and more higher requirement to the power consumption of wherein chip circuit.Ldpc decoder is the structure according to check matrix H, finishes decoding by iterative decoding algorithm.Because the H matrix is huge and sparse usually, thereby the structure of LDPC decoding is complicated usually, and hardware consumption is bigger.Because of the power consumption of its decoding is also very big, this is fatal weakness for a lot of mobile radio terminal equipment.Having superior error performance simultaneously is the requirement the most basic to error control coding, so reduce the emphasis that LDPC power consumption of deciphering and the error performance that improves decoder always are academia and industrial quarters research.To the present Research of ldpc code decoder, there are two kinds of main decoding algorithms with at present.Be respectively that (Two-Phase Message-Passing, TPMP) decoding algorithm and Turbo decoding information are transmitted (Turbo-Decoding Message-Passing, TDMP) decoding algorithm in two information transmission
[2] [3], wherein the TDMP algorithm is called hierarchical algorithm again.The TPMP algorithm that hierarchical algorithm is more traditional has the faster and better characteristics of error performance of algorithmic statement.Its reason is that hierarchical algorithm is divided into the little iteration of several times to an iteration in the TPMP algorithm carries out successively, and variable node all will be updated and be applied to next time little iteration after each time little iteration.Yet the hierarchical algorithm decoding time also is linear the increase with the increase of layering quantity, increase the throughput that degree of parallelism (quantity of CNU) improves algorithm usually, but this method can be brought the face of chip undoubtedly
Amass increase with power consumption.
Mobile digital multimedia broadcast system is the broadcast system that develops rapidly in recent years, and " mobile TV " is one of the most typical the most frequently used system in this system.Because the characteristic of its broadcast channel does not possess retransmission feedback mechanism, thereby the error performance of error correcting code is had relatively high expectations.Simultaneously, because it is applied to portable terminal, thereby low power dissipation design also becomes the difficult point of design.
Summary of the invention
(1) technical problem that will solve
Main purpose of the present invention is to provide a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system, the decoding time that brings of serial is long successively to overcome in the traditional batch algorithm little iteration in each iteration, and the big and big problem of hardware spending brought of degree of parallelism, reduce total iterations, thereby realize the reduction of system power dissipation, and the raising of system's error performance.
(2) technical scheme
For achieving the above object, the invention provides a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system, this decoder is made of memory cell, variable node arithmetic element VNU, check-node arithmetic element CNU, input-buffer, output buffers, control logic and internet; Wherein, come the information of self-channel at first to deposit memory cell in, in each iterative decoding process, the variable node arithmetic element receives by the information of memory cell input and by the internet and links to each other with the check-node arithmetic element, finishes information updating and deposits back memory cell; When decoding finished, hard-decision bits was by memory cell output (as shown in Figure 1).
In the such scheme, this parallel hierarchical decoder adopts the part parallel decoding architecture, uses 1 memory cell altogether, 36 VNU, 18 CNU, 1 output buffers, 1 output buffers, wherein 36 and 18 columns and the maximum numbers of lines that are respectively the basis matrix of check matrix H.
In the such scheme, described memory cell comprises 36 storing sub-units, each storing sub-units is made of 1 hard-decision bits memory Bit_mem, 1 channel information memory In_mem and 3 external information memory Ex_mem, and wherein 3 is the column weight of check matrix H.In the such scheme, described channel information memory In_mem is that 128 one-port memory constitutes by two degree of depth, is furnished with three and reads address wire and three DOL Data Output Line, is implemented in the function of finishing 3 read operations in two clock cycle.
In the such scheme, described external information memory Ex_mem is that 256 dual-ported memory constitutes by a degree of depth, be furnished with two and read address wire, a write address line, two DOL Data Output Line and a Data In-Line, be implemented in the function of finishing twice read operation and a write operation in two clock cycle.
In the such scheme, described variable node arithmetic element VNU is in each iteration, calculating will the input validation node the external information value and through the variable node hard decision value after this time iteration, it includes the add operation unit, after computing finishes information is pressed the raw address write storage unit.
In the such scheme, described check-node arithmetic element CNU adopts minimum-sum algorithm, the arithmetic element of being calculated minimum value by a batch total constitutes, each computing has heavy parallel input of input of row, CNU will calculate corresponding each input and not comprise input minimum under the situation itself, and by the internet with the check information write storage unit.
In the such scheme, in decode procedure with in the check matrix each the row as one deck, be about to each iteration and be divided into 256 little iteration, corresponding 1/2 code check and its basis matrix of 3/4 code check have 18 row and 9 row respectively, each has 18 or 9 row concurrent operations constantly respectively when decoding, wherein each two clock cycle of little iteration time spent, thereby finish iteration one time, i.e. 256 * 18 or 256 * 9 layers of computing need 256 * 2 clock cycle; Though have several layers to carry out computing at the same time at synchronization, but for each variable node, three layers of its correspondence then is to carry out computing successively one by one, thereby one deck updated information can be used for the computing of back one deck before utilizing, thereby realize the principle of stratification that variable node utilizes each layer information to go forward one by one and upgrade.
In the such scheme, the decode procedure of this parallel hierarchical decoder comprises:
Step 1: initialization;
During the decoding beginning, In_mem in the memory cell and Ex_mem will be written into the channel information from input; At a storing sub-units, definition address variables A ddr1, Addr2 and Addr3 represent the read/write address of In_mem and Ex_mem;
Step 2: interative computation;
General decode procedure will be divided into the several times iteration, and this decoder is divided into 256 second son iteration with each iteration;
Step 3: decoding finishes;
When hard decision satisfies all check equations, or total iterations when reaching predefined maximum iteration time decoding finish output hard decision information.
In the such scheme, the sub-iterative process of interative computation comprises in the step 2:
Sub-iterative step 1: external information computing;
In each iteration, system reads 3 channel informations and 6 hierarchical alterative information respectively from In_mem and Ex_mem, and inputs to the variable node arithmetic element; The variable node arithmetic element is exported 3 external informations to the check-node arithmetic element through add operation;
Sub-iterative step 2: check-node computing;
The check-node arithmetic element is utilized minimum-sum algorithm, check-node is upgraded, and the check-node information after will upgrading exports the variable node arithmetic element to.
Sub-iterative step 3: variable node computing;
The variable node arithmetic element as the hierarchical alterative information of this iteration, exports the check-node information of input and the external information addition of this iteration among the Ex_mem in the corresponding storing sub-units to by raw address then; Get the hard decision information of the highest order of this hierarchical alterative information as this iteration output simultaneously, export in the hard decision memory in the respective stored subelement, this moment, one second son iteration was finished;
After 256 second son iteration, one time iteration is finished; Storing respectively in each storing sub-units this moment through the iteration value of information afterwards, different fully for the content of three Ex_mem memories in the every storing sub-units.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1), a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system of the present invention's proposition, hierarchical algorithm is introduced in the mobile digital multimedia broadcast system, make under identical signal to noise ratio, identical maximum iteration time condition, reach the decoding condition of convergence (BER≤10
-6) required average iterations still less, error performance is better.Under the high s/n ratio condition, average iterations only is 1/2 of a conventional decoder.Thereby, can improve the decoding throughput greatly or effectively reduce power consumption, and improve the error performance of system.
2), a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system of proposing of the present invention, each layer of parallel processing realized the information transmission between each layer simultaneously.Under the condition of the data throughput that guarantees system requirements, the hardware consumption of hierarchical algorithm is reduced greatly.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples:
Fig. 1 is a kind of general function block diagram that is applied to the parallel hierarchical decoder of LDPC sign indicating number in the mobile digital multimedia broadcast system that the present invention proposes;
Storing sub-units functional block diagram in Fig. 2 is that the present invention proposes a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system;
The functional block diagram of variable node arithmetic element VNU in Fig. 3 is that the present invention proposes a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system;
Fig. 4 is that the present invention proposes a kind of parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system after finishing iteration, the memory contents of 3 Ex_mem memories in storing sub-units.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
This parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system that the present invention proposes, its corresponding check matrix is the accurate circular matrix that check matrix forms through row-column transform in the mobile digital multimedia broadcast system, and the column weight of its basis matrix is 3.Thereby to each enter code word (be in the check matrix each row) all will be from 3 row of its correspondence in each iteration acquired information, make the confidence level of self obtain upgrading.After iteration repeatedly, satisfy check equations or reach maximum iteration time.Therefore, parallel hierarchical ldpc decoder proposed by the invention is divided into 3 layers with each enter code word in an iteration.
Shown in Figure 1 is that wherein the row of check matrix heavily is 6 according to the ldpc decoder of the embodiment of the invention based on CMMB agreement 3/4 code check of China Broadcast ﹠ Television general bureau proposition, and column weight is 3.Adopt the part parallel decoding architecture, use 1 memory cell altogether, 36 VNU, 9 CNU (wherein 36 and 9 columns and the line numbers that are respectively the basis matrix of H), 1 input-buffer, 1 output buffers.
Shown in Figure 2 is structure chart according to embodiment of the invention storing sub-units, and storing sub-units is made of 1 hard-decision bits memory Bit_mem, 1 channel information memory In_mem and 3 external information memory Ex_mem, and wherein 3 is the column weight of check matrix H.In_mem is that 128 one-port memory constitutes by two degree of depth, is furnished with three and reads address wire and three DOL Data Output Line.Be implemented in the function of finishing 3 read operations in two clock cycle.And Ex_mem is that 256 dual-ported memory constitutes by a degree of depth, is furnished with two to read address wire, a write address line, two DOL Data Output Line and a Data In-Line, is implemented in the function of finishing twice read operation and a write operation in two clock cycle.
Shown in Figure 3 is structure chart according to embodiment of the invention variable node arithmetic element (VNU), in each iteration, calculate will the input validation node the external information value, and through the variable node hard decision value after this time iteration.Wherein only comprise the add operation unit, after computing finishes, information is pressed the raw address write storage unit.
The LDPC sign indicating number parallel hierarchical decoder of present embodiment, in decode procedure with in the check matrix each the row as one deck (be about to each iteration and be divided into 256 little iteration).Corresponding 3/4 code check, its basis matrix have 9 row.Each 9 row (layer) concurrent operation constantly when decoding.Wherein each two clock cycle of little iteration time spent, thereby finish an iteration (256 * 9 layers of computing) about 256 * 2 clock cycle of needs.
Though have several layers to carry out computing at the same time at synchronization, but for each variable node (row of one in the check matrix), three layers of its correspondence then is to carry out computing successively one by one, thereby one deck updated information can be used for the computing of back one deck before utilizing, thereby realize the principle of stratification that variable node utilizes each layer information to go forward one by one and upgrade.
The decode procedure of the LDPC sign indicating number parallel hierarchical decoder of this example is as follows:
Step 1: initialization
During the decoding beginning, In_mem in the memory cell and Ex_mem will be written into the channel information from input.At a storing sub-units (as shown in Figure 2), definition address variables A ddr1, Addr2 and Addr3 represent the read/write address of In_mem and Ex_mem.
Step 2: interative computation
General decode procedure will be divided into the several times iteration, and decoder in the present invention is divided into 256 second son iteration with each iteration, and each sub-iterative process is divided into following three steps:
Sub-iterative step 1: external information computing
In each iteration, system reads 3 channel informations and 6 hierarchical alterative information respectively from In_mem and Ex_mem, and inputs to the variable node arithmetic element.The variable node arithmetic element is exported 3 external informations to the check-node arithmetic element through add operation.
Sub-iterative step 2: check-node computing
The check-node arithmetic element is utilized minimum-sum algorithm, check-node is upgraded, and the check-node information after will upgrading exports the variable node arithmetic element to.
Sub-iterative step 3: variable node computing
The variable node arithmetic element exports the check-node information of input and the external information addition of this iteration among the Ex_mem in the corresponding storing sub-units to by raw address as the hierarchical alterative information of this iteration.The highest order of getting this hierarchical alterative information simultaneously exports in the hard decision memory in the respective stored subelement as the hard decision information of this iteration output.This moment, one second son iteration was finished.
After 256 second son iteration, one time iteration is finished.Storing respectively in each storing sub-units this moment through the iteration value of information afterwards.It should be noted that for the content of three Ex_mem memories in the every storing sub-units different fully.If Ini_addr1, Ini_addr2 and Ini_addr3 are respectively the initial address of Addr1, Addr2 and Addr3, and satisfy Ini_addr1＞Ini_addr2＞Ini_addr3, and then the content of three Ex_mem memories as shown in Figure 4.Wherein dash area represent information via 3 layers of check-node (be made as C1, C2, renewal C3), just the order difference of upgrading.Under the structure of this information stores, next iteration can directly begin.
Step 3: decoding finishes
When hard decision satisfies all check equations, or total iterations when reaching predefined maximum iteration time decoding finish output hard decision information.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
List of references:
[1]R.G.Gallager，Low?Density?Parity?Check?Codes.Cambridge，MA：MIT?Press，1963.
[2]M.M.Mansour?and?N.R.Shanbhag，“High?throughput?LDPCdecoders，”IEEE?Trans.VLSI?Syst.，vol.11，no.12，pp.976-996，Dec.2003.
[3]M.M.Mansour?and?N.R.Shanbhag，“A?640-Mb/s?2048-bitprogrammable?LDPC?decoder?chip，”IEEE?J.Solid-State?Circuits，vol.41，no.3，pp.684-698，Mar.2006.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system is characterized in that, this decoder is made of memory cell, variable node arithmetic element VNU, check-node arithmetic element CNU and internet; Wherein, come the information of self-channel at first to deposit memory cell in, in each iterative decoding process, the variable node arithmetic element receives by the information of memory cell input and by the internet and links to each other with the check-node arithmetic element, finishes information updating and deposits back memory cell; When decoding finished, hard-decision bits was exported by memory cell.
2. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 1, it is characterized in that, this parallel hierarchical decoder adopts the part parallel decoding architecture, use 1 memory cell altogether, 36 VNU, 18 CNU, 1 output buffers, 1 output buffers, wherein 36 and 18 columns and the maximum numbers of lines that are respectively the basis matrix of check matrix H.
3. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 1, it is characterized in that, described memory cell comprises 36 storing sub-units, each storing sub-units is made of 1 hard-decision bits memory Bit_mem, 1 channel information memory In_mem and 3 external information memory Ex_mem, and wherein 3 is the column weight of check matrix H.
4. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 3, it is characterized in that, described channel information memory In_mem is that 128 one-port memory constitutes by two degree of depth, be furnished with three and read address wire and three DOL Data Output Line, be implemented in the function of finishing 3 read operations in two clock cycle.
5. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 3, it is characterized in that, described external information memory Ex_mem is that 256 dual-ported memory constitutes by a degree of depth, be furnished with two and read address wire, a write address line, two DOL Data Output Line and a Data In-Line, be implemented in the function of finishing twice read operation and a write operation in two clock cycle.
6. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 1, it is characterized in that, described variable node arithmetic element VNU is in each iteration, calculating will the input validation node the external information value and through the variable node hard decision value after this time iteration, it includes the add operation unit, after computing finishes information is pressed the raw address write storage unit.
7. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 1, it is characterized in that, described check-node arithmetic element CNU adopts minimum-sum algorithm, the arithmetic element of being calculated minimum value by a batch total constitutes, each computing has heavy parallel input of input of row, CNU will calculate corresponding each input and not comprise input minimum under the situation itself, and by the internet with the check information write storage unit.
8. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 1, it is characterized in that, in decode procedure with in the check matrix each the row as one deck, be about to each iteration and be divided into 256 little iteration, corresponding 1/2 code check and its basis matrix of 3/4 code check have 18 row and 9 row respectively, each has 18 or 9 row concurrent operations constantly respectively when decoding, wherein each two clock cycle of little iteration time spent, thereby finish iteration one time, i.e. 256 * 18 or 256 * 9 layers of computing need 256 * 2 clock cycle; Though have several layers to carry out computing at the same time at synchronization, but for each variable node, three layers of its correspondence then is to carry out computing successively one by one, thereby one deck updated information can be used for the computing of back one deck before utilizing, thereby realize the principle of stratification that variable node utilizes each layer information to go forward one by one and upgrade.
9. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 1 is characterized in that, the decode procedure of this parallel hierarchical decoder comprises:
Step 1: initialization;
During the decoding beginning, In_mem in the memory cell and Ex_mem will be written into the channel information from input; At a storing sub-units, definition address variables A ddr1, Addr2 and Addr3 represent the read/write address of In_mem and Ex_mem;
Step 2: interative computation;
General decode procedure will be divided into the several times iteration, and this decoder is divided into 256 second son iteration with each iteration;
Step 3: decoding finishes;
When hard decision satisfies all check equations, or total iterations when reaching predefined maximum iteration time decoding finish output hard decision information.
10. the parallel hierarchical decoder that is applied to LDPC sign indicating number in the mobile digital multimedia broadcast system according to claim 9 is characterized in that, the sub-iterative process of interative computation comprises in the step 2:
Sub-iterative step 1: external information computing;
In each iteration, system reads 3 channel informations and 6 hierarchical alterative information respectively from In_mem and Ex_mem, and inputs to the variable node arithmetic element; The variable node arithmetic element is exported 3 external informations to the check-node arithmetic element through add operation;
Sub-iterative step 2: check-node computing;
The check-node arithmetic element is utilized minimum-sum algorithm, check-node is upgraded, and the check-node information after will upgrading exports the variable node arithmetic element to.
Sub-iterative step 3: variable node computing;
The variable node arithmetic element as the hierarchical alterative information of this iteration, exports the check-node information of input and the external information addition of this iteration among the Ex_mem in the corresponding storing sub-units to by raw address then; Get the hard decision information of the highest order of this hierarchical alterative information as this iteration output simultaneously, export in the hard decision memory in the respective stored subelement, this moment, one second son iteration was finished;
After 256 second son iteration, one time iteration is finished; Storing respectively in each storing sub-units this moment through the iteration value of information afterwards, different fully for the content of three Ex_mem memories in the every storing sub-units.
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Application publication date: 20101229 |