CN101931368B - Low-noise amplifier - Google Patents
Low-noise amplifier Download PDFInfo
- Publication number
- CN101931368B CN101931368B CN 200910149518 CN200910149518A CN101931368B CN 101931368 B CN101931368 B CN 101931368B CN 200910149518 CN200910149518 CN 200910149518 CN 200910149518 A CN200910149518 A CN 200910149518A CN 101931368 B CN101931368 B CN 101931368B
- Authority
- CN
- China
- Prior art keywords
- couples
- transistor
- source electrode
- order
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention relates to low-noise amplifier comprising an amplifier core circuit and a direct current bias unit. The amplifier core circuit is used for receiving single input signal or a pair of differential input signals and processing single input signal or a pair of differential input signals so as to output a pair of differential output signals in the base interlaced coupling mode. The direct current bias unit is coupled with the amplifier core circuit and processes a signal source according to the circuit configuration thereof so as to generate the signal input signal or the pair of differential input signal, namely, the low-noise amplifier still can synchronously support two receiving ways of single-end and double end by changing the circuit configuration of the direct current bias unit.
Description
Technical field
The present invention relates to electronic circuit, especially a kind of low noise amplifier.
Background technology
Low noise amplifier (low noise amplifier, LNA) in the radio frequency chip (RF chip) determines for product orientation that mostly it is single-ended reception (single receiving) or is both-end reception (differential receiving).In other words, after radio frequency chip completed, the receive mode of low noise amplifier was not that single-ended reception is exactly that both-end receives.Thus, under the condition that radio frequency chip completes, low noise amplifier possibly can't be supported single-ended and these two kinds of receive modes of both-end simultaneously.
Summary of the invention
In order to address the above problem, the object of the invention is to after radio frequency chip completes, design the circuit configurations of current bias unit for product orientation, can allow the receive mode of low noise amplifier change to adaptively single-ended or both-end receives.
To achieve these goals, the invention provides a kind of low noise amplifier, it comprises amplifier core circuit and current bias unit.The amplifier core circuit is in order to receiving single input signal or a pair of differential input signal, and adopts the mode of the staggered coupling of a base stage to process described single input signal or described a pair of differential input signal, thereby exports a pair of differential output signal.Current bias unit couples the amplifier core circuit, and according to the circuit configurations of itself signal source is processed, thereby produces described single input signal or described a pair of differential input signal.
In an embodiment of the present invention, the amplifier core circuit of described low noise amplifier comprises:
The input transconductance cell couples current bias unit, in order to receiving and to process single input signal or a pair of differential input signal, thereby produces a pair of differential current signal;
The current buffering unit couples the input transconductance cell, in order to receiving and to cushion a pair of differential current signal, thereby exports a pair of buffering differential current signal later; And
The output loading unit couples the current buffering unit, in order to receiving a pair of buffering differential current signal later, and exports according to this a pair of differential output signal.
In an embodiment of the present invention, the input transconductance cell of described low noise amplifier comprises:
The first transistor, its grid is in order to receive the first bias voltage, and it drains in order to export the first current signal of a pair of differential current signal, and its source electrode is then in order to receive the first input signal of single input signal or a pair of differential input signal; And
Transistor seconds, its grid is in order to receive the first bias voltage, its base stage couples the source electrode of the first transistor, its drain electrode is in order to exporting the second current signal of a pair of differential current signal, and its source electrode then couples the base stage of the first transistor and is coupled to ground in order to the second input signal of receiving a pair of differential input signal or by current bias unit.
In an embodiment of the present invention, the input transconductance cell of described low noise amplifier also comprises:
The first resistance, its first end is in order to receive the first bias voltage, and its second end then couples the grid of the first transistor;
The first electric capacity, its first end couples the grid of the first transistor, and its second end then couples the source electrode of transistor seconds;
The second resistance, its first end is in order to receive the first bias voltage, and its second end then couples the grid of transistor seconds; And
The second electric capacity, its first end couples the grid of transistor seconds, and its second end then couples the source electrode of the first transistor.
In an embodiment of the present invention, the current buffering unit of described low noise amplifier comprises:
The 3rd transistor, its grid is in order to receive the second bias voltage, and its source electrode couples the drain electrode of the first transistor, and its drain electrode is then in order to export the first buffer current signal of a pair of buffering differential current signal later; And
The 4th transistor, its grid is in order to receive the second bias voltage, and its source electrode couples the drain electrode of transistor seconds, and its drain electrode is then in order to export the second buffer current signal of a pair of buffering differential current signal later.
In an embodiment of the present invention, the current buffering unit of described low noise amplifier also comprises:
The 3rd resistance, its first end is in order to receive the second bias voltage, and its second end then couples the 3rd transistorized grid;
The 3rd electric capacity, its first end couple the 3rd transistorized source electrode, and its second end then couples the 4th transistorized grid;
The 4th resistance, its first end is in order to receive the second bias voltage, and its second end then couples the 4th transistorized grid; And
The 4th electric capacity, its first end couple the 4th transistorized source electrode, and its second end then couples the 3rd transistorized grid.
In an embodiment of the present invention, the output loading unit of described low noise amplifier comprises:
The first load, its first end is coupled to system voltage, and its second end then couples the 3rd transistorized drain electrode to export the first output signal of a pair of differential output signal; And
The second load, its first end is coupled to system voltage, and its second end then couples the 4th transistorized drain electrode to export the second output signal of a pair of differential output signal.
In an embodiment of the present invention, the current bias unit of described low noise amplifier comprises:
Balun, have elementary and secondary, elementary first end is in order to receive signal source, the second elementary end is coupled to ground, secondary first end couples the source electrode of the first transistor to produce the first input signal, secondary center tap terminal is coupled to ground, and the second secondary end couples the source electrode of transistor seconds to produce the second input signal.
In an embodiment of the present invention, the current bias unit of described low noise amplifier comprises:
Balun, have elementary and secondary, elementary first end is in order to receive signal source, the second elementary end then is coupled to ground, secondary first end couples the source electrode of the first transistor to produce the first input signal, and the second secondary end then couples the source electrode of transistor seconds to produce the second input signal.
In an embodiment of the present invention, the current bias unit of described low noise amplifier also comprises:
The first inductance, its first end couples secondary first end, and its second end then is coupled to ground; And
The second inductance, its first end couple the second secondary end, and its second end then is coupled to ground.
In an embodiment of the present invention, the current bias unit of described low noise amplifier also comprises:
The first high impedance assembly, its first end couples secondary first end, and its second end then is coupled to ground; And
The second high impedance assembly, its first end couple the second secondary end, and its second end then is coupled to ground.
In an embodiment of the present invention, the current bias unit of described low noise amplifier also comprises:
The 5th transistor, its grid is in order to receive the 3rd bias voltage, and its drain electrode couples the source electrode of the first transistor, and its source electrode then is coupled to ground; And
The 6th transistor, its grid is in order to receive the 3rd bias voltage, and its drain electrode couples the source electrode of transistor seconds, and its source electrode then is coupled to ground.
In an embodiment of the present invention, the current bias unit of described low noise amplifier comprises:
Inductance, its first end is in order to receive signal source and to couple the source electrode of the first transistor, and its second end then is coupled to ground.
In an embodiment of the present invention, the second end of the inductance of described low noise amplifier also is coupled to the source electrode of transistor seconds.
In an embodiment of the present invention, the current bias unit of described low noise amplifier comprises:
The first high impedance assembly, its first end couples the source electrode of the first transistor, and its second end then is coupled to ground;
The second high impedance assembly, its first end couples the source electrode of transistor seconds, and its second end then is coupled to ground; And
The 5th electric capacity, itself and the second high impedance assembly are together connected with each other.
In an embodiment of the present invention, the current bias unit of described low noise amplifier comprises:
The 5th transistor, its grid is in order to receive the 3rd bias voltage, and its drain electrode couples the source electrode of the first transistor, and its source electrode then is coupled to ground;
The 6th transistor, its grid is in order to receive the 3rd bias voltage, and its drain electrode couples the source electrode of transistor seconds, and its source electrode then is coupled to ground; And
The 5th electric capacity, its first end couples the source electrode of transistor seconds, and its second end then is coupled to ground.
In an embodiment of the present invention, the single input signal of described low noise amplifier is single voltage input signal.
In an embodiment of the present invention, a pair of differential input signal of described low noise amplifier is a pair of differential voltage input signal.
In an embodiment of the present invention, the amplifier core circuit of described low noise amplifier is the inside that is produced on chip, and current bias unit be the inside that is produced on chip with outside one of them.
Technique effect of the present invention is as follows:
(being under the constant state of amplifier core circuit) under the condition that radio frequency chip completes, by changing the circuit configurations of current bias unit, low noise amplifier still can be supported single-ended and these two kinds of receive modes of both-end simultaneously.
Description of drawings
Fig. 1 is the calcspar of the low noise amplifier 100 of an example embodiment.
Fig. 2 is the circuit diagram of the amplifier core circuit 101 of an example embodiment.
Fig. 3, Fig. 4, Fig. 5, Fig. 6 are respectively the circuit diagram of the current bias unit 103 of an example embodiment, and it can allow the receive mode of low noise amplifier 100 be that both-end receives.
Fig. 7, Fig. 8, Fig. 9 are respectively the circuit diagram of the current bias unit 103 of another example embodiment, and it can allow the receive mode of low noise amplifier 100 be single-ended reception.
Wherein, the accompanying drawing identifier declaration is as follows:
100: low noise amplifier
101: the amplifier core circuit
103: current bias unit
201: the input transconductance cell
203: the current buffering unit
205: the output loading unit
T, T ': balun
Vs: single input signal
Vs+, Vs-: differential input signal
Vo+, Vo-: differential output signal
I+, I-: differential current signal
IB+, IB-: buffering differential current signal later
M1--M5: transistor
R1--R5: resistance
C1--C5: electric capacity
L, L1, L2: inductance
ZL1, ZL2: load
ZH1, ZH2: high impedance assembly
GND: ground
VB1, VB2, VB3: bias voltage
SS: signal source
VDD: system voltage
Embodiment
Now incite somebody to action the in detail several example embodiment of reference, and the example of described several example embodiment is described in the accompanying drawings, so that above-mentioned feature and advantage can be become apparent.In addition, all possibility parts, the assembly of use same numeral in drawings and the embodiments/the identical or similar portions of member representative.
Fig. 1 is the calcspar of the low noise amplifier 100 of an example embodiment.Please refer to Fig. 1, low noise amplifier 100 comprises amplifier core circuit 101 and current bias unit 103.Wherein, amplifier core circuit 101 is in order to reception and process single input signal Vs or a pair of differential input signal Vs+ and Vs-, thereby exports a pair of differential output signal Vo+ and Vo-(for example being a pair of differential voltage output signal).Current bias unit 103 couples amplifier core circuit 101, and according to the circuit configurations of itself signal source SS is processed, thereby produce single input signal Vs and (for example be single voltage input signal, but be not restricted to this) or differential input signal Vs+ and Vs-(for example be a pair of differential voltage input signal, but be not restricted to this).
In this example embodiment, amplifier core circuit 101 and the current bias unit 103 non-inside that are produced on simultaneously chip (not drawing, for example is radio frequency chip, but is not restricted to this).Clearer, amplifier core circuit 101 can be produced on the inside of chip, and current bias unit 103 can be produced on the outside (for example being produced on the printed circuit board (PCB)) of chip.Also because of so, after radio frequency chip completes, need only the circuit configurations that design current bias unit 103 for product orientation, just can allow the receive mode of low noise amplifier 100 change to adaptively single-ended or the both-end reception.Thus, (being under the constant state of amplifier core circuit 101) under the condition that radio frequency chip completes, low noise amplifier 100 still can be supported single-ended and these two kinds of receive modes of both-end simultaneously.
Yet in other example embodiment, amplifier core circuit 101 and current bias unit 103 also can be produced on the inside of chip simultaneously.In other words, current bias unit 103 is not limited to be produced on the outside of chip.
Fig. 2 is the circuit diagram of the amplifier core circuit 101 of an example embodiment.Please merge with reference to Fig. 1 and Fig. 2, amplifier core circuit 101 comprises input transconductance cell 201, current buffering unit 203, and the output loading unit.Input transconductance cell 201 couples current bias unit 103, in order to receiving and to process single input signal Vs or differential input signal Vs+ and Vs-, thereby produces a pair of differential current signal I+ and I-.Current buffering unit 203 couples input transconductance cell 201, in order to reception and buffering differential current signal I+ and I-, thereby exports a pair of buffering differential current signal IB+ and IB-later.Output loading unit 205 couples current buffering unit 203, cushions differential current signal IB+ and IB-later in order to receive, and exports according to this differential output signal Vo+ and Vo-.
Clearer, input transconductance cell 201 comprises transistor M1 and M2, resistance R 1 and R2, and capacitor C 1 and C2.The grid of transistor M1 (gate) can receive voltage bias VB 1 by resistance R 1, and is coupled to the source electrode (source) of transistor M2 by capacitor C 1.The drain electrode of transistor M1 (drain) is in order to export the positive current signal I+ of differential current signal I+ and I-.The source electrode of transistor M1 is in order to receive the positive input signal Vs+ of single input signal Vs or differential input signal Vs+ and Vs-.
The grid of transistor M2 can receive voltage bias VB 1 by resistance R 2, and is coupled to the source electrode of transistor M1 by capacitor C 2.The base stage of transistor M2 (bulk) couples the source electrode of transistor M1.The drain electrode of transistor M2 is in order to export the negative current signal I-of differential current signal I+ and I-.The source electrode of transistor M2 couples the base stage of transistor M1, and is coupled to ground GND in order to the negative input signal Vs-that receives differential input signal Vs+ and Vs-or by current bias unit 103.
In addition, current buffering unit 203 comprises transistor M3 and M4, resistance R 3 and R4, and capacitor C 3 and C4.The grid of transistor M3 can receive voltage bias VB 2 by resistance R 3, and is coupled to the source electrode of transistor M4 by capacitor C 3.The source electrode of transistor M3 couples the drain electrode of transistor M1.The drain electrode of transistor M3 cushions differential current signal IB+ later and the positive buffer current signal IB+ of IB-in order to output.The grid of transistor M4 can receive voltage bias VB 2 by resistance R 4, and is coupled to the source electrode of transistor M3 by capacitor C 4.The source electrode of transistor M4 couples the drain electrode of transistor M2.The drain electrode of transistor M4 cushions differential current signal IB+ later and the negative buffer current signal IB-of IB-in order to output.
Moreover output loading unit 205 comprises load ZL1 and ZL2.The first end of load ZL1 is coupled to system voltage VDD, and the second end of load ZL1 then couples the drain electrode of transistor M3 with the positive output signal Vo+ of output differential output signal Vo+ and Vo-.The first end of load ZL2 is coupled to system voltage VDD, and the second end of load ZL2 then couples the drain electrode of transistor M4 with the negative output signal Vo-of output differential output signal Vo+ and Vo-.
Allow the receive mode of low noise amplifier 100 be that both-end receives in this hypothesis wish, then the circuit configurations of current bias unit 103 have following several selection, but are not restricted to this.
Fig. 3 is the circuit diagram of the current bias unit 103 of an example embodiment, and it can allow the receive mode of low noise amplifier 100 be that both-end receives.Please merge with reference to Fig. 1--Fig. 3, current bias unit 103 comprises balun (Balance-unbalance-converter, Balun) T (for example can be transformer, but be not restricted to this).Balun T has elementary (primary side) and secondary (secondary side).The elementary first end of balun T is in order to receive signal source SS.Wherein, signal source SS can be the signal that is received by antenna for example, but is not restricted to this.
The second elementary end of balun T is coupled to ground GND.The secondary first end of balun T couples the source electrode of transistor M1, to produce the positive input signal Vs+ of differential input signal Vs+ and Vs-.The secondary centre cap of balun T (center tap) end is coupled to ground GND.The second secondary end of balun T couples the source electrode of transistor M2, to produce the negative input signal Vs-of differential input signal Vs+ and Vs-.
Fig. 4 is the circuit diagram of the current bias unit 103 of another example embodiment, and it can allow the receive mode of low noise amplifier 100 be that both-end receives equally.Please merge with reference to Fig. 1, Fig. 2 and Fig. 4, current bias unit 103 comprise balun T ' (for example can for transformer or can with reference to described in " http://en.wikipedia.org/wiki/Balun " and each assembly, but all be not restricted to this) and inductance L 1 and L2.Balun T ' has elementary and secondary.The elementary first end of balun T ' is in order to receive signal source SS.Wherein, signal source SS can be the signal that is received by antenna for example, but is not restricted to this.The second elementary end of balun T ' then is coupled to ground GND.The secondary first end of balun T ' couples the source electrode of transistor M1, to produce the positive input signal Vs+ of differential input signal Vs+ and Vs-.The second secondary end of balun T ' couples the source electrode of transistor M2, to produce the negative input signal Vs-of differential input signal Vs+ and Vs-.The first end of inductance L 1 couples the secondary first end of balun T ', and the second end of inductance L 1 then is coupled to ground GND.The first end of inductance L 2 couples the second secondary end of balun T ', and the second end of inductance L 2 then is coupled to ground GND.
Fig. 5 is the circuit diagram of the current bias unit 103 of another example embodiment, and it can allow the receive mode of low noise amplifier 100 be that both-end receives equally.Please merge with reference to Fig. 4 and Fig. 5, Fig. 5 is that than the different part of Fig. 4 Fig. 5 replaces inductance L 1 and L2 with high impedance assembly ZH1 and ZH2.Wherein, high impedance assembly ZH1 and ZH2 can be resistance, but are not restricted to this.
Fig. 6 is the circuit diagram of the current bias unit 103 of an again example embodiment, and it can allow the receive mode of low noise amplifier 100 be that both-end receives equally.Please merge with reference to Fig. 4 and Fig. 6, Fig. 6 is that than the different part of Fig. 4 Fig. 6 replaces inductance L 1 and L2 with transistor M5 and M6.Wherein, the grid of transistor M5 couples the source electrode of transistor M1 in order to the drain electrode that receives voltage bias VB 3, transistor M5, and the source electrode of transistor M5 then is coupled to ground GND.The grid of transistor M6 couples the source electrode of transistor M2 in order to the drain electrode that receives voltage bias VB 3, transistor M6, and the source electrode of transistor M6 then is coupled to ground GND.
The current bias unit 103 that Fig. 3 to Fig. 6 draws respectively can allow the receive mode of low noise amplifier 100 be that both-end receives, and this moment transistor M1 and M2 be set to the common grid amplifier configuration.Because the staggered coupling of capacitor C 1 and C2 (cross-coupling) grid and source electrode between transistor M1 and M2, and the base stage of transistor M1 and M2 adopts again the skill of staggered coupling.Therefore, be made as under 1: 1 the condition input mutual conductance (g at the coil ratio of balun T/T '
m) can effectively be enlarged into 2* (g
m+ g
mB), g wherein
mB is the base stage mutual conductance.Thus, the input impedance (Zin) that has a low noise voltage device 100 that both-end receives can be regarded as and is similar to 1/ (g
m+ g
mB), and voltage gain (Av) can equal 2*k* (g
m+ g
Mb) * ZL.Wherein, k=2*Zin/ (Rs+Zin), and under the condition of perfect matching antenna impedance (Rs=50 ohm), its value is 1; And ZL is the resistance of load ZL1 and ZL2.
Allow the receive mode of low noise amplifier 100 be single-ended reception in this hypothesis wish, then the circuit configurations of current bias unit 103 have following several selection, but are not restricted to this.
Fig. 7 is the circuit diagram of the current bias unit 103 of an example embodiment, and it can allow the receive mode of low noise amplifier 100 be single-ended reception.Please merge with reference to Fig. 1, Fig. 2 and Fig. 7, current bias unit 103 comprises inductance L.The first end of inductance L is in order to receiving signal source SS, and couples the source electrode of transistor M1, and the second end of inductance L then is coupled to the source electrode of ground GND and transistor M2.Wherein, signal source SS can be the signal that is received by antenna for example, but is not restricted to this.
Fig. 8 is the circuit diagram of the current bias unit 103 of another example embodiment, and it can allow the receive mode of low noise amplifier 100 be single-ended reception equally.Please merge with reference to Fig. 1, Fig. 2 and Fig. 8, current bias unit 103 comprises high impedance assembly ZH1 and ZH2 and capacitor C 5.The first end of high impedance assembly ZH1 couples the source electrode of transistor M1, and the second end of high impedance assembly ZH1 then is coupled to ground GND.The first end of high impedance assembly ZH2 couples the source electrode of transistor M2, and the second end of high impedance assembly ZH2 then is coupled to ground GND.Capacitor C 5 is together connected with each other with high impedance assembly ZH2.Wherein, high impedance assembly ZH1 and ZH2 can be resistance, but are not restricted to this.
Fig. 9 is the circuit diagram of the current bias unit 103 of another example embodiment, and it can allow the receive mode of low noise amplifier 100 be single-ended reception equally.Please merge with reference to Fig. 1, Fig. 2 and Fig. 9, current bias unit 103 comprises transistor M5 and M6 and capacitor C 5.The grid of transistor M5 is in order to receive voltage bias VB 3, and the drain electrode of transistor M5 couples the source electrode of transistor M1, and the source electrode of transistor M5 then is coupled to ground GND.The grid of transistor M6 is in order to receive voltage bias VB 3, and the drain electrode of transistor M6 couples the source electrode of transistor M2, and the source electrode of transistor M6 then is coupled to ground GND.The first end of capacitor C 5 couples the source electrode of transistor M2, and the second end of capacitor C 5 then is coupled to ground GND.
Fig. 7 to Fig. 9 current bias unit that illustrates 103 out of the ordinary all can allow the receive mode of low noise amplifier 100 be single-ended reception, and this moment transistor M1 and M2 be set to respectively common grid amplifier configuration and commonsource amplifier configuration.Because the base stage of transistor M1 and M2 adopts the skill of staggered coupling.Therefore, input mutual conductance (g
m) can effectively be enlarged into (g
m+ g
Mb), thereby realize the effect that mutual conductance is amplified, wherein g
MbBe the base stage mutual conductance.Thus, the input impedance (Zin) that has a low noise voltage device 100 of single-ended reception can be regarded as equally and is similar to 1/ (g
m+ g
Mb), and voltage gain (Av) can equal 2*k* (g equally
m+ g
Mb) * ZL.
Accordingly, no matter the receive mode of low noise amplifier 100 is single-ended or both-end receives, and its input impedance (Zin) can not change with voltage gain (Av).Therefore, low noise amplifier 100 can under the prerequisite of not changing amplifier core circuit 101, by changing the circuit configurations of current bias unit 103, can cause low noise amplifier 100 can support simultaneously single-ended and these two kinds of receive modes of both-end.
In addition, low noise amplifier 100 can be according to different product orientation demands, for example: high-performance or low cost, high (the single system chip of integrating, SoC) or the product development of degree of integration lower (radio frequency pass receipts machine), and change adaptively the circuit configurations of current bias unit 103, thereby allow the receive mode of low noise amplifier 100 can adaptability change to single-ended or both-end receives.
Although disclose as above with a plurality of embodiment; so it is not to limit this enforcement example; have in the technical field under any and usually know the knowledgeable; in the spirit and scope that do not break away from this enforcement example; when doing a little change and retouching, so the protection range of this enforcement example is as the criterion when looking accompanying the claim person of defining.
Claims (17)
1. a low noise amplifier is characterized in that, comprising:
The amplifier core circuit in order to receiving single input signal or a pair of differential input signal, and adopts the mode of the staggered coupling of a base stage to process this single input signal or this a pair of differential input signal, thereby exports a pair of differential output signal; And
Current bias unit couples this amplifier core circuit, and according to the circuit configurations of itself signal source is processed, thereby produces this single input signal or this a pair of differential input signal;
This amplifier core circuit comprises:
The input transconductance cell couples this current bias unit, in order to reception and this single input signal of processing or this a pair of differential input signal, thereby produces a pair of differential current signal;
The current buffering unit couples this input transconductance cell, in order to reception and this a pair of differential current signal of buffering, thereby exports a pair of buffering differential current signal later; And
The output loading unit couples this current buffering unit, in order to receiving this a pair of buffering differential current signal later, and this a pair of differential output signal of output according to this;
This input transconductance cell comprises:
The first transistor, its grid is in order to receive the first bias voltage, and it drains in order to export the first current signal of this a pair of differential current signal, and its source electrode is then in order to receive the first input signal of this single input signal or this a pair of differential input signal; And
Transistor seconds, its grid is in order to receive this first bias voltage, its base stage couples the source electrode of this first transistor, its drain electrode is in order to exporting the second current signal of this a pair of differential current signal, and its source electrode then couples the base stage of this first transistor and is coupled to ground in order to the second input signal of receiving this a pair of differential input signal or by this current bias unit.
2. low noise amplifier as claimed in claim 1 is characterized in that, this input transconductance cell also comprises:
The first resistance, its first end is in order to receive this first bias voltage, and its second end then couples the grid of this first transistor;
The first electric capacity, its first end couples the grid of this first transistor, and its second end then couples the source electrode of this transistor seconds;
The second resistance, its first end is in order to receive this first bias voltage, and its second end then couples the grid of this transistor seconds; And
The second electric capacity, its first end couples the grid of this transistor seconds, and its second end then couples the source electrode of this first transistor.
3. low noise amplifier as claimed in claim 2 is characterized in that, this current buffering unit comprises:
The 3rd transistor, its grid is in order to receive one second bias voltage, and its source electrode couples the drain electrode of this first transistor, and its drain electrode is then in order to export the first buffer current signal of this a pair of buffering differential current signal later; And
The 4th transistor, its grid is in order to receive this second bias voltage, and its source electrode couples the drain electrode of this transistor seconds, and its drain electrode is then in order to export the second buffer current signal of this a pair of buffering differential current signal later.
4. low noise amplifier as claimed in claim 3 is characterized in that, this current buffering unit also comprises:
The 3rd resistance, its first end is in order to receive this second bias voltage, and its second end then couples the 3rd transistorized grid;
The 3rd electric capacity, its first end couple the 3rd transistorized source electrode, and its second end then couples the 4th transistorized grid;
The 4th resistance, its first end is in order to receive this second bias voltage, and its second end then couples the 4th transistorized grid; And
The 4th electric capacity, its first end couple the 4th transistorized source electrode, and its second end then couples the 3rd transistorized grid.
5. low noise amplifier as claimed in claim 4 is characterized in that, this output loading unit comprises:
The first load, its first end is coupled to system voltage, and its second end then couples the 3rd transistorized drain electrode to export the first output signal of this a pair of differential output signal; And
The second load, its first end is coupled to this system voltage, and its second end then couples the 4th transistorized drain electrode to export the second output signal of this a pair of differential output signal.
6. low noise amplifier as claimed in claim 5 is characterized in that, this current bias unit comprises:
Balun, have elementary and secondary, this elementary first end is in order to receive this signal source, this second elementary end is coupled to ground, this secondary first end couples the source electrode of this first transistor to produce this first input signal, this secondary center tap terminal is coupled to ground, and this second secondary end couples the source electrode of this transistor seconds to produce this second input signal.
7. low noise amplifier as claimed in claim 5 is characterized in that, this current bias unit comprises:
Balun, have elementary and secondary, this elementary first end is in order to receive this signal source, this second elementary end then is coupled to ground, this secondary first end couples the source electrode of this first transistor to produce this first input signal, and this second secondary end then couples the source electrode of this transistor seconds to produce this second input signal.
8. low noise amplifier as claimed in claim 7 is characterized in that, this current bias unit also comprises:
The first inductance, its first end couple this secondary first end, and its second end then is coupled to ground; And
The second inductance, its first end couple this second secondary end, and its second end then is coupled to ground.
9. low noise amplifier as claimed in claim 7 is characterized in that, this current bias unit also comprises:
The first high impedance assembly, its first end couple this secondary first end, and its second end then is coupled to ground; And
The second high impedance assembly, its first end couple this second secondary end, and its second end then is coupled to ground.
10. low noise amplifier as claimed in claim 7 is characterized in that, this current bias unit also comprises:
The 5th transistor, its grid is in order to receive one the 3rd bias voltage, and its drain electrode couples the source electrode of this first transistor, and its source electrode then is coupled to ground; And
The 6th transistor, its grid is in order to receive the 3rd bias voltage, and its drain electrode couples the source electrode of this transistor seconds, and its source electrode then is coupled to ground.
11. low noise amplifier as claimed in claim 5 is characterized in that, this current bias unit comprises:
Inductance, its first end is in order to receive this signal source and to couple the source electrode of this first transistor, and its second end then is coupled to ground.
12. low noise amplifier as claimed in claim 11 is characterized in that, the second end of this inductance also is coupled to the source electrode of this transistor seconds.
13. low noise amplifier as claimed in claim 5 is characterized in that, this current bias unit comprises:
The first high impedance assembly, its first end couples the source electrode of this first transistor, and its second end then is coupled to ground;
The second high impedance assembly, its first end couples the source electrode of this transistor seconds, and its second end then is coupled to ground; And
The 5th electric capacity, itself and this second high impedance assembly is together connected with each other.
14. low noise amplifier as claimed in claim 5 is characterized in that, this current bias unit comprises:
The 5th transistor, its grid is in order to receive one the 3rd bias voltage, and its drain electrode couples the source electrode of this first transistor, and its source electrode then is coupled to ground;
The 6th transistor, its grid is in order to receive the 3rd bias voltage, and its drain electrode couples the source electrode of this transistor seconds, and its source electrode then is coupled to ground; And
The 5th electric capacity, its first end couples the source electrode of this transistor seconds, and its second end then is coupled to ground.
15. low noise amplifier as claimed in claim 1 is characterized in that, this single input signal is single voltage input signal.
16. low noise amplifier as claimed in claim 1 is characterized in that, this a pair of differential input signal is a pair of differential voltage input signal.
17. low noise amplifier as claimed in claim 1 is characterized in that, this amplifier core circuit is the inside that is produced on a chip, and this current bias unit be the inside that is produced on this chip with outside one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910149518 CN101931368B (en) | 2009-06-25 | 2009-06-25 | Low-noise amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910149518 CN101931368B (en) | 2009-06-25 | 2009-06-25 | Low-noise amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101931368A CN101931368A (en) | 2010-12-29 |
| CN101931368B true CN101931368B (en) | 2013-05-01 |
Family
ID=43370342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910149518 Active CN101931368B (en) | 2009-06-25 | 2009-06-25 | Low-noise amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101931368B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8588726B2 (en) * | 2011-02-03 | 2013-11-19 | Futurewei Technologies, Inc. | Low noise mixer |
| US8928407B2 (en) * | 2013-03-11 | 2015-01-06 | Futurewei Technologies, Inc. | Current conveyor circuit and method |
| TWI595745B (en) * | 2016-03-28 | 2017-08-11 | 立積電子股份有限公司 | Amplifier |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1528047A (en) * | 2000-12-22 | 2004-09-08 | ӡ�����Ƽ��ɷ�����˾ | Circuit for low noise, fully differential amplification |
| CN101282110A (en) * | 2008-04-25 | 2008-10-08 | 北京大学 | Low-power consumption single-ended input difference output low-noise amplifier |
| CN101373952A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科创微电子（北京）有限公司 | Low noise amplifier capable of implementing differential amplification and method thereof |
-
2009
- 2009-06-25 CN CN 200910149518 patent/CN101931368B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1528047A (en) * | 2000-12-22 | 2004-09-08 | ӡ�����Ƽ��ɷ�����˾ | Circuit for low noise, fully differential amplification |
| CN101373952A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科创微电子（北京）有限公司 | Low noise amplifier capable of implementing differential amplification and method thereof |
| CN101282110A (en) * | 2008-04-25 | 2008-10-08 | 北京大学 | Low-power consumption single-ended input difference output low-noise amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101931368A (en) | 2010-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7224225B2 (en) | Differential inductor based low noise amplifier | |
| US7688146B2 (en) | Single-ended input to differential-ended output low noise amplifier | |
| US8838042B2 (en) | RF front-end with integrated T/R switch | |
| CN112187194B (en) | Push-pull power amplifier, radio frequency front-end circuit and wireless device | |
| US9397714B1 (en) | Radio frequency receiver circuit and the inductor-coupling single-ended input differential-output low-noise amplifier thereof | |
| US8472894B2 (en) | Signal transmitting/receiving circuit including an impedance matching circuit | |
| US7129803B2 (en) | Tuned transformer balun circuit and applications thereof | |
| US20120178400A1 (en) | Amplifiers and related receiver systems | |
| US10651806B2 (en) | Method and system for a pseudo-differential low-noise amplifier at KU-band | |
| TWI387198B (en) | Low noise amplifier | |
| US7603091B2 (en) | Hybrid balun apparatus and receiver comprising the same | |
| US8860507B2 (en) | Amplifier with gain circuit coupeld to primary coil of transformer | |
| CN101931368B (en) | Low-noise amplifier | |
| US7567142B2 (en) | Quasi-balun | |
| CN213243932U (en) | Radio frequency power amplification system and radio frequency front end module | |
| CN100576722C (en) | Single-ended input both-end output amplifier circuit and signal processing circuit | |
| CN107809220A (en) | Low-noise amplifier, RF IC, signal receiving module and rf chip | |
| CN108880481B (en) | Low noise amplifier, receiver for low noise amplifier and method | |
| CN108988797B (en) | Low noise amplifier and electronic device | |
| CN103378864B (en) | Radio frequency signal receiving device | |
| US11606069B2 (en) | Single-ended-to-differential amplifier and radio frequency receiver | |
| CN100438595C (en) | Ultra high frequency active antenna amplifier for digital video frequency broadcast receiver and relative circuit | |
| CN113179087A (en) | Low-noise amplifier and differential amplification assembly | |
| EP3139498A1 (en) | Method and apparatus for amplifying signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |