CN101923458B - Decimal divider capable of randomly selecting division rate range - Google Patents
Decimal divider capable of randomly selecting division rate range Download PDFInfo
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- CN101923458B CN101923458B CN 201010241870 CN201010241870A CN101923458B CN 101923458 B CN101923458 B CN 101923458B CN 201010241870 CN201010241870 CN 201010241870 CN 201010241870 A CN201010241870 A CN 201010241870A CN 101923458 B CN101923458 B CN 101923458B
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Abstract
The invention relates to a decimal divider capable of randomly selecting division rate range, which is used in a phase-locked loop (PLL). The decimal divider is provided with a Sigma Delta decimal divider loop formed by connecting a plurality of unit dividers in cascade, wherein each unit divider is one stage; the last stage or a plurality of stages of the Sigma Delta decimal divider loop is/are respectively provided with a logic control circuit; and the signal output end and the control input end of the Sigma Delta decimal divider loop are connected with a selector. The minimum division rateof the invention is free from the restriction of the number of 2/3 of the unit dividers, so the designer can freely select the required division rate range. Meanwhile, the outputs of the divider can be ensured to be within all the division rate ranges; and all the outputs are signals with proper frequency and the same initial phase.
Description
Technical field:
The present invention relates to a kind of fractional divider that can select arbitrarily removal frequency range, be used for phaselocked loop (PLL).
Background technology:
In Fig. 1 phaselocked loop (PLL), the signal of phase/frequency Discr. (PFD) input is respectively the clock of reference clock and divider output, PFD compares by frequency and the phase place to two signals, produce error signal UP and DN, error signal just can generate to control the direct-current control voltage VCTRL of voltage-controlled oscillator (VCO) (VCO) output frequency by charge pump and loop filter.This is an automatic feedback system, and when this feedback system locking, REF_CKL=DIV_CKL=OUT_CKL/M has also just realized the purpose by a high-frequency signal of a low frequency signal generation.As very crucial ingredient in the pll system, divider has directly determined the frequency of output clock and the highest running speed of whole PLL.In the application of PLL, usually need a PLL to export the clock signal of multiple different frequency, this just needs divider to have programmable functions, that is to say that divider will provide the multiple different rate (divide ratio) of removing.Divider generally divides two kinds, integer divider and fractional divider, and corresponding PLL is integer P LL (Integer PLL) and decimal PLL (Fractional-N PLL).In the wireless communications application field, usually face the problem of a plurality of frequency channels, integer P LL requires the bandwidth of passage must equal the input reference clock frequency, and because the requirement of PLL stability, bandwidth=Fref/10 of PLL, namely 1/10th of reference clock frequency, the bandwidth of this spline channel had just both limited the frequency of input reference clock, had also limited the bandwidth range of PLL, and decimal PLL does not have such restriction, so decimal PLL has become the first selection of deviser day by day.The core of decimal PLL just is fractional divider, adopt at present maximum be ∑ Δ modulation fractional divider, as shown in Figure 2.By the control of ∑ Delta modulator, divider can produce a rate of removing between N and N+1, and its maximum advantage just is that noiseproof feature is best.
Summary of the invention:
In order to solve its technical matters, the invention provides a kind of fractional divider that can select arbitrarily removal frequency range.
The technical solution adopted for the present invention to solve the technical problems is: a kind of fractional divider that can select arbitrarily removal frequency range, be provided with the ∑ Δ fractional divider loop that is formed by the divider cascade of a plurality of units, each unit divider is one-level, the afterbody of described ∑ Δ fractional divider loop or what being respectively equipped with logic control circuit at, the signal output part of described ∑ Δ fractional divider loop is connected with selector switch with the control input end.
Further: the logic control circuit on afterbody unit's divider of described ∑ Δ fractional divider loop is by first or door and second or form, described second or gate control signal provided by the overhead control signal on afterbody unit's divider and the selector switch, and its input end that is connected with overhead control signal on the selector switch is the not gate input end, its output signal then passes to the second last level unit divider, described first or gate control signal provided by the control signal of the overhead control signal controlling on the selector switch and afterbody unit's divider.
The above logic control circuit of described the second last level that ∑ Δ fractional divider loop is set or the second last level is by the 4th or door and the 5th or form, the described the 4th or gate control signal by the unit divider of this logic control circuit place level and thereafter the logic control circuit on one-level unit's divider provide, and its input end that is connected with logic control circuit on the rear one-level unit divider is the not gate input end, its output signal then passes to its previous stage unit's divider, the described the 5th or gate control signal then by the control signal of the unit divider of this logic control circuit place level and thereafter the logic control circuit on one-level unit's divider determine.
Minimum of the present invention except rate not the number of the unit's of being subjected to divider 2/3 limit, the deviser can freely select needed removal frequency range, simultaneously, its output can guarantee in all removals frequency range, output all is the identical signal of correct frequency and initial phase.
Description of drawings:
Fig. 1 is phase-locked loop circuit figure.
Fig. 2 is ∑ Δ modulation fractional divider circuit diagram.
Fig. 3 is ∑ Δ fractional divider loop circuit figure.
Fig. 4 is the circuit diagram of unit divider.
Fig. 5 is the circuit diagram after ∑ Δ fractional divider loop circuit increases the logic control function.
Fig. 6 is integrated circuit figure of the present invention.
Among the figure: 1, selector switch; 2, first or the door; 3, second or the door; 4, not gate input end; 5, first input end; 6, the second input end; 7, ∑ Delta modulator; 8, overhead control signal; 9, the 4th or the door; 10, the 5th or the door; 11, logic inverter input end; 12, upper input end.
Embodiment:
The present invention is further described below in conjunction with drawings and Examples.
A kind of fractional divider that can select arbitrarily removal frequency range as shown in Figure 6, be provided with the ∑ Δ fractional divider loop that is formed by the divider cascade of a plurality of units, each unit divider is one-level, the signal output part of described ∑ Δ fractional divider loop is connected with selector switch 1 with the control input end, last two-stage at described ∑ Δ fractional divider loop is respectively equipped with logic control circuit, be arranged at logic control circuit on afterbody unit's divider and comprise first or door 2 and second or door 3, described second or door 3 control signal determined by the overhead control signal 8 on unit one belongs to's divider and the selector switch 1, and the input end that is connected with overhead control signal 8 on the selector switch 1 is not gate input end 4, its output signal passes to the second last level unit divider, described first or door 2 control signals by the control signal decision of the control of the overhead control signal 8 on the selector switch 1 and afterbody unit's divider, its output signal then is connected with the 5th or the upper input end 12 of door 10 with the logic inverter input end 11 of the 4th or door 9 of the second last level unit divider, the described the 4th or door another control signal of 9 then provided by the second last level unit divider, the 5th or another control signal of door 10 then determined by the control signal of the second last level unit divider.
Fig. 3 is ∑ Δ fractional divider loop used among the present invention, and wherein employed unit divider is for except 2 or except 3 unit divider, and each unit divider is except 2 or controlled by the ∑ Delta modulator except 3.The sort circuit structure can be finished from 2
nIf (C
0To C
N-1All be 0) to 2
N+1-1 (if C
0To C
N-1All be 1) division.The circuit structure of unit divider 2/3 as shown in Figure 4.
Because being minimum number except rate (divide ratio) unit's of being subjected to divider 2/3, a subject matter of ∑ Δ fractional divider shown in Figure 3 limits, in some application, can not meet the demands, therefore increased on this basis removal frequency range, on the afterbody of ∑ Δ fractional divider loop or what, increased respectively logic control circuit, as shown in Figure 5, the function of the logic control circuit that increases is that afterbody or what are opened selectively or closed, take Fig. 5 as example, if minimum can realize 2 except rate
N_min, in this case, 2/3 unit divider Close All of last two-stage, this cyclic system is comprised of 1 to n-2 level unit's divider; If maximum except rate then be 2
N+1-1, this moment, 2/3 unit divider of last two-stage was all opened, and this cyclic system is comprised of 1 to n level unit's divider.So the minimum that this structure can realize is 2 except rate
N_min, and maximum is 2 except rate
N+1-1, the deviser can freely select needed removal frequency range.
Although ∑ Δ fractional divider loop can increase range of choice except rate effectively by increasing the logic control function, has also brought new problem when the function of realization division of decimal.The final output signal of divider shown in Figure 5 is F
Out, and one-level F in the end not why
nOutput be because:
When the removal frequency range of divider from 2
N_minTo 2
N-1-1 o'clock, loop progression was the n-2 level, F
Out=F
N-2, F
N-1=F
n=0; (scope 1)
When the removal frequency range of divider from 2
N-1To 2
n-1 o'clock, loop progression was the n-1 level, F
Out=F
N-1, F
n=0; (scope 2)
When the removal frequency range of divider from 2
nTo 2
N+1-1 o'clock, loop progression was the n level, F
Out=F
n(scope 3)
So, F
OutWhat can guarantee to export in all removals frequency range all is the signal of correct frequency.But F
OutHave a phase problem, it is at backfeed loop, and its phase place determines by the initial phase of loop, and when except rate during in different range, the progression of loop is different, so initial phase is also different, and this has just brought problem for ∑ Δ fractional divider.Take three rank ∑ Delta modulators as example, when the rate of removing is 2
N-1-1 o'clock, three rank ∑ Δ modulation just meaned that the rate of removing is 2
N-1-4 to 2
N-1Random variation in+3 the scope produces one 2 at last
N-1Near-1 decimal is except rate, just mean that also the rate of removing is random variation in scope 1 and 2 two intervals of scope, we know in scope 1, the divider loop becomes to n-2 unit's divider stage joint group by 1, and in scope 2, the divider loop becomes to n-1 unit's divider stage joint group by 1, and the initial phase of two different loops is different, and such result is exactly as final output signal F
OutWhen these two interval variations, the phase place of signal is always in continuous saltus step.This continual phase hit finally can cause whole phase-locked loop pll to lock.With F
OutThat different is F
N-2, F
N-1And F
nOn forward path, its initial phase is all the time by input signal F
InDetermine, be not subjected to the impact of loop progression, therefore the selection in final output signal improves, as shown in Figure 6, and final output signal F
OutAt F
N-2, F
N-1And F
nBetween select, the control of selection is by C
N-3, C
N-2, C
N-1And C
nFinish.
It is emphasized that: above only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, every foundation technical spirit of the present invention all still belongs in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment does.
Claims (1)
1. the fractional divider that can select arbitrarily removal frequency range, be provided with the ∑ Δ fractional divider loop and the selector switch that are formed by the divider cascade of a plurality of units, each unit divider is one-level, it is characterized in that: the signal output part of described ∑ Δ fractional divider loop is connected with selector switch with the control input end;
Increased respectively logic control circuit on the afterbody of ∑ Δ fractional divider loop or what, the afterbody of ∑ Δ fractional divider loop or what logic control circuit opened or close;
Logic control circuit on afterbody unit's divider of described ∑ Δ fractional divider loop comprises first or door and second or door, the above logic control circuit of the second last level of ∑ Δ fractional divider loop or the second last level is set by the 4th or door and the 5th or form;
Described second or the control signal of door by the overhead control signal deciding on unit one belongs to's divider and the selector switch, and the input end that is connected with overhead control signal on the selector switch is the not gate input end, its output signal passes to the second last level unit divider;
Described first or gate control signal determined by the control signal of the overhead control signal controlling on the selector switch and afterbody unit's divider, described first or the door output signal then be connected with the 5th or the upper input end of door with the logic inverter input end of the 4th or door of the second last level unit divider, the described the 4th or another control signal of door then provided by the second last level unit divider, the 5th or another control signal of door then determined by the control signal of the second last level unit divider;
The described the 4th or gate control signal by the unit divider of this logic control circuit place level and thereafter the logic control circuit on one-level unit's divider provide, and its input end that is connected with logic control circuit on the rear one-level unit divider is the not gate input end, and its output signal then passes to its previous stage unit's divider;
The described the 5th or gate control signal then by the control signal of the unit divider of this logic control circuit place level and thereafter the logic control circuit on one-level unit's divider determine.
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| CN 201010241870 CN101923458B (en) | 2010-07-30 | 2010-07-30 | Decimal divider capable of randomly selecting division rate range |
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| CN 201010241870 CN101923458B (en) | 2010-07-30 | 2010-07-30 | Decimal divider capable of randomly selecting division rate range |
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| CN101923458B true CN101923458B (en) | 2013-09-18 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1172302A (en) * | 1996-07-31 | 1998-02-04 | 许肖梅 | Analog multiplier using oversampling segma delta modulator |
| EP2056469A1 (en) * | 2007-10-30 | 2009-05-06 | Sony Corporation | Data processing apparatus and method |
| CN201754274U (en) * | 2010-07-30 | 2011-03-02 | 苏州科山微电子科技有限公司 | Decimal divider capable of arbitrarily selecting dividing rate range |
-
2010
- 2010-07-30 CN CN 201010241870 patent/CN101923458B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1172302A (en) * | 1996-07-31 | 1998-02-04 | 许肖梅 | Analog multiplier using oversampling segma delta modulator |
| EP2056469A1 (en) * | 2007-10-30 | 2009-05-06 | Sony Corporation | Data processing apparatus and method |
| CN201754274U (en) * | 2010-07-30 | 2011-03-02 | 苏州科山微电子科技有限公司 | Decimal divider capable of arbitrarily selecting dividing rate range |
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|---|---|
| CN101923458A (en) | 2010-12-22 |
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Effective date of registration: 20170329 Address after: Siming District Feng Yu Road Xiamen City, Fujian province 361000 No. 57 room 402 Patentee after: Xiamen science and Technology Co., Ltd. Address before: 215021, Jiangsu, Suzhou Industrial Park, Jinji Lake Avenue, No. 1355, international science and Technology Park, phase A404, 2 Patentee before: Suzhou Cosine Microelectronics Technology Co., Ltd. |
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Effective date of registration: 20181023 Address after: 362000 3001 Luoshan three Century Avenue, Luoshan, Quanzhou, Fujian. Patentee after: Keshan core creation (Fujian) Technology Co., Ltd. Address before: 361000 room 402, 57 Feng Yu Road, Siming District, Xiamen, Fujian. Patentee before: Xiamen science and Technology Co., Ltd. |