CN101902626B

CN101902626B - Bitstream buffer controller and control method thereof

Info

Publication number: CN101902626B
Application number: CN 200910142703
Authority: CN
Inventors: 林展世; 苏胤合
Original assignee: Himax Media Solutions Inc
Current assignee: Himax Technologies Ltd; Himax Media Solutions Inc
Priority date: 2009-05-31
Filing date: 2009-05-31
Publication date: 2012-11-28
Anticipated expiration: 2029-05-31
Also published as: CN101902626A

Abstract

The invention provides a bitstream buffer controller for a video decoder. The bitstream buffer controller comprises a first first-in first-out buffer, a second first-in first-out buffer and an interrupt controller, wherein the first first-in first-out buffer is used for storing input bitstream, and the second first-in first-out buffer is used for storing effective load, wherein the effective load is taken from the input bitstream; and the interrupt controller generates an interrupt signal according to the full states of the first first-in first-out buffer and the second first-in first-out buffer, therefore, when the effective load is loaded at every time, the video decoder can be switched without detecting the full states so as to load the effective load.

Description

Bitstream buffer controller and control method thereof

Technical field

The present invention is about a kind of Video Decoder, particularly about a kind of bitstream buffer controller that is used for decoder H.264/AVC with and control method.

Background technology

First-in first-out buffer is used in the bit stream controller of Video Decoder usually, is used for temporary and flow control, its also often by as round-robin queue with the read-write pointer.Previous read-write pointer is all identical memory location; And fifo queue is empty; As a rule the dummy status of Video Decoder inquiry first in first out earlier, the correctness of the data that store when guaranteeing each reading of data, thereby reduce the efficient of Video Decoder.

Therefore, current demand provides a bitstream buffer controller, and it can reduce the unnecessary formation of the first in first out dummy status of Video Decoder.

Summary of the invention

The present invention provides a kind of effective bitstream buffer controller, and it has the inspection module of the dummy status of scalable bitstream.

A kind of bitstream buffer controller that is used for Video Decoder; It comprises first first-in first-out buffer, second first-in first-out buffer and interrupt control unit; This first first-in first-out buffer is in order to store incoming bit stream, and second first-in first-out buffer is in order to store Payload, and wherein this Payload is taken from this incoming bit stream; And this interrupt control unit system according to the full state (fullness status) of this first first-in first-out buffer and this second first-in first-out buffer to produce interrupt signal; Make at every turn when loading this Payload, this Video Decoder can need not to check that this full state promptly switches, to load this Payload.

A kind of spy who is used for Video Decoder flows buffer control method; It comprises: the incoming bit stream that receives and store first first-in first-out buffer; Obtain and store Payload; This Payload is taken from this incoming bit stream in second first-in first-out buffer, and produces interrupt signal according to the full state of first first-in first-out buffer and second first-in first-out buffer, makes this Video Decoder at checking mode with do not switch between the checking mode; To load this Payload, consequently check that the frequency of this full state can reduce.

Via producing suitable interrupt signal and keeping SW letter formula index; Interrupt as long as trigger, the present invention helps to allow processor inspection index state, that is to say; The state index that bit stream need not to confirm first-in first-out buffer just can be by access, and reaches the effect of raising process process usefulness.

The aforementioned paragraphs summary description characteristic of the present invention and technical advantages, in order to more clearly understand specification specified of the present invention, further feature of the present invention and advantage are exposed in the following specification

Description of drawings

Accompanying drawing simple declaration and accompanying drawing thereof below are provided, thereby more completely disclose details of the present invention and advantage:

Fig. 1 is the calcspar of configuration that shows the bitstream buffer controller of relevant one embodiment of the present of invention.

Fig. 2 shows the control signal of the bitstream buffer controller that is used for Fig. 1 and the calcspar of data streaming detail.

Fig. 3 is the flow chart of operation of the bitstream buffer controller of displayed map 1.

[primary clustering symbol description]

100 bitstream buffer controllers

101 Video Decoders

102 external memory storages

103 memory interfaces

104 bit stream first-in first-out buffers

105 management of process devices

The elementary bit stream parser of 107 packetizeds

The parser of 108 network abstract layer units to raw byte sequence load

109 raw byte sequence load first-in first-out buffer

110 interrupt control units

112 bit stream managers

201 bitstream buffer controllers

202 multiplexers

301,302,303,304,305 steps

Embodiment

The associated description of the following embodiment of the invention is about accompanying drawing of the present invention.

Fig. 1 is the calcspar of configuration that shows the bitstream buffer controller 100 of relevant one embodiment of the present of invention, and bitstream buffer controller 100 can be avoided the unnecessary inspection of first-in first-out buffer dummy status, for example applies to H.264/AVC decoder.

Bitstream buffer controller 100 comprises memory interface 103, bit stream first-in first-out buffer (BSB FIFO; Bit-stream Buffer First-in First-Out) 104 elementary bit stream parser (the PES parser of management of process device 105, packetized; Packetized Elementary Stream Parser) 107 network abstract layer unit to raw byte sequence load (NALU2RBSP; Network AbstractLayer Unit to Raw Byte Sequence Payload) parser 108, raw byte sequence load first-in first-out buffer (RBSP FIFO; Raw Byte Sequence Packet First-in First-Out) 109, interrupt control unit 110 and bit stream manager 112.Bitstream buffer controller 100 is used to receive bit stream; This bit stream be not the basic bit of packetized streamed be exactly that basic bit is streamed; An external memory storage 102 for example; And bitstream buffer controller 100 also is used to export an interrupt signal, makes that this Video Decoder 101 can be at checking mode or do not take from this bit stream and be stored in RBSP FIFO 109 in the checking mode.In checking mode, when each Video Decoder 101 loaded the raw byte sequence load that is stored in RBSPFIFO 109, Video Decoder 101 can be checked the full state of RBSP FIFO 109; On the contrary, in checking mode not, when each Video Decoder 101 loaded the raw byte sequence load that is stored in RBSPFIFO 109, Video Decoder 101 can not checked the full state of RBSP FIFO 109.

Suppose that external memory storage 102 provides a bit stream; Memory interface 103 connects the external memory storage 102 with BSB FIFO104; Management of process device 105 control BSB FIFO 104 load this bit stream; And this bit stream not to be basic bit streamed is exactly that the basic bit of packetized is streamed, wherein this bit stream is to load from external memory storage 102 via memory interface 103.In addition, external memory storage 102 is preferably double data rate (DDR) Synchronous Dynamic Random Access Memory (DDR SDRAM; And external memory storage 102 is by double data rate (DDR) Synchronous Dynamic Random Access Memory controller (DDR controller) (not shown) of controlling Double Data RateSynchronous Dynamic Random Access Memory).In one embodiment; BSB FIFO 104 can produce first index; The different conditions of the signable five kinds of BSB FIFO 104 of this first index; Just empty, empty, half-full, full and full state or the like almost almost, in an alternate embodiment, the signable BSB FIFO 104 of this first index much more more or the state of less kind.

The elementary bit stream parser 107 of packetized is used for: if be stored in the bit stream of BSB FIFO 104 is that the basic bit of packetized is streamed, and then the elementary bit stream parser 107 of this packetized this bit stream from be stored in this BSB FIFO 104 is obtained the streamed Payload of a basic bit; In alternate embodiment; If it is streamed to be stored in the bit stream of BSB FIFO 104 and to be the basic bit of packetized; The bit stream that the elementary bit stream parser 107 of packetized also can be walked around this input is to next stage, just the parser 108 of NALU2RBSP.In the present embodiment, the elementary bit stream parser 107 of packetized also can be obtained demonstration time label (PTS in the streamed bit stream of the basic bit of packetized; Presentation Time Stamp) information is to be used for video decoding process subsequently.

After the elementary bit stream parser 107 of packetized; The emulation that the parser 108 of NALU2RBSP is used to remove the streamed Payload of basic bit prevents 3 bytes (emulation prevention threebyte) (0*00_00_03); Wherein to prevent 3 bytes be to be obtained by 107 of the elementary bit stream parsers of packetized in the emulation of the streamed Payload of this basic bit; Also or the emulation that is used to remove the streamed bit stream of basic bit that is stored in BSB FIFO 104 of the parser 108 of NALU2RBSP prevent 3 bytes, to obtain the raw byte sequence load.

RBSP FIFO 109 is used to load the raw byte sequence load of being obtained by the parser 108 of NALU2RBSP; In the present embodiment; RBSP FIFO 109 can produce second index, the different conditions of the signable five kinds of RBSP FIFO 109 of this second index, just empty, empty, half-full, full and full state or the like almost almost; In alternate embodiment, the state of the more or less kind of the signable RBSP FIFO 109 of this first index.

In addition, bit stream manager 112 is used for according to grammars Video Decoder 101 being cancelled the raw byte sequence load that conversion are stored in RBSP FIFO 109.

Interrupt control unit 110 is used to reduce the unnecessary inspection first in first out dummy status process of Video Decoder 101; In the present embodiment; Interrupt control unit 110 is used to produce an interrupt signal; Make Video Decoder 101 at checking mode or do not switch in the checking mode, be stored in the raw byte sequence load among the RBSP FIFO 109 with loading.As herewith routine, interrupt signal can arrive checking mode in order to Switch Video decoder 101 for one [sky] interrupt signal, is stored in the raw byte sequence load among the RBSP FIFO 109 with loading; Also perhaps interrupt signal can arrive not checking mode in order to Switch Video decoder 101 for one [expiring] interrupt signal, is stored in the raw byte sequence load among the RBSP FIFO 109 with loading.

In the example of [sky] interrupt signal; Whether the state index that interrupt control unit 110 is used to detect BSB FIFO 104 and RBSP FIFO 109 reaches preset empty configuration (empty configuration); As example herewith, this preset empty configuration can design first index as almost empty BSB FIFO 1045, and second index of empty RBSP FIFO 109 almost; Have only when the state index that interrupts controller 110 reception BSBFIFO 104 and RBSP FIFO 109; And when confirm satisfying preset empty configuration, Video Decoder 101 can switch to checking mode, is stored in the raw byte sequence load among the RBSP FIFO 109 with loading.In another alternate embodiment about [expiring] interrupt signal; Whether the state index that interrupt control unit 110 is used to detect BSB FIFO 104 and RBSP FIFO 109 reaches preset full configuration (full configuration); As it is herewith routine; Should preset full configuration can design first index as almost full BSBFIFO 1045; And second index of almost full RBSP FIFO 109, have only when interrupting controller 110 to receive the state index of BSB FIFO 104 and RBSP FIFO 109, and when confirming to satisfy preset full configuration; Video Decoder 101 can switch to not checking mode, is stored in the raw byte sequence load among the RBSP FIFO 109 with loading.In addition, those skilled in the art all can understand under any this invention: in order to produce interrupt signal and to make BSB FIFO 104 and RBSPFIFO 109 can reach preferable utilance, but preset interruption configuration individual design.

Through Switch Video decoder 101 rightly to checking mode not; Be stored in the raw byte sequence load among the RBSPFIFO 109 with loading; Therefore reduce the frequency of inquiry first in first out state; And have the help of interrupt control unit 101 and the utilance of BSB FIFO 104 and RBSP FIFO 109, so the usefulness of Video Decoder 101 can improve significantly.

Fig. 2 shows the control signal of the bitstream buffer controller 100 that is used for Fig. 1 and the calcspar of data streaming detail; In addition; For example, the management of process device 105 of Fig. 1 can be bitstream buffer controller 201 and multiplexer 202, and its detailed features discloses as follows.

Bitstream buffer controller 201 adjustment access rates make BSB FIFO 104 be full state; Bitstream buffer controller 201 generations one are used for the control protocol of memory interface 103; And then flow to BSB FIFO 104 from external memory storage 102 bit loading, and this bit stream not to be the basic bit of packetized streamed is exactly that basic bit is streamed.If the state index of BSB FIFO 104 becomes full or almost full; Bitstream buffer controller 201 will be ended from external memory storage 102 bit loading to flow to BSB FIFO 104 based on this control protocol; And that if the state index of BSB FIFO 104 becomes is half-full, almost empty or empty, bitstream buffer controller 201 will require to flow to BSB FIFO 104 from external memory storage 102 bit loading based on this control protocol.

Multiplexer 202 connects BSB FIFO 104 or has the elementary bit stream parser 107 of packetized of the parser 108 of NALU2RBSP; As aforementioned; When incoming bit stream is that the basic bit of packetized is streamed; Multiplexer 202 will have the streamed bit stream of basic bit of packetized; The streamed bit stream of the basic bit of this packetized is stored among the BSB FIFO 104 flowing through the elementary bit stream parser 107 of packetized, and then obtains the streamed Payload of basic bit, and the parser 108 that then gets into NALU2RBSP is to obtain the raw byte sequence load.In an alternate embodiment; When incoming bit stream is that basic bit is streamed; Multiplexer 202 will have the streamed bit stream of basic bit; The streamed bit stream of this basic bit is stored among the BSB FIF 104, and the parser 108 that directly flows to NALU2RBSP is to obtain the raw byte sequence load.In addition; The elementary bit stream parser 107 of packetized is used for obtaining the streamed Payload of basic bit from the bit stream that is stored in BSB FIFO 104; And being used to remove the emulation of the streamed Payload of basic bit, the parser 108 of NALU2RBSP prevents 3 bytes; Wherein to prevent 3 bytes be to be obtained by 107 of the elementary bit stream parsers of packetized in the emulation of the streamed Payload of this basic bit; Or directly be stored in BSB FIFO 104 to obtain the raw byte sequence load, what above-mentioned these technical characterictic and Fig. 1 disclosed is similar.Multiplexer 202 is used for: almost full or full if the state index of second first-in first-out buffer 109 becomes; Multiplexer 202 will be ended parser 108 that the elementary bit stream Payload is loaded on NALU2RBSP to obtain the raw byte sequence load that stores usefulness in second first-in first-out buffer 109; And that if the state index of second first-in first-out buffer 109 becomes is half-full, almost empty or empty, 202 of multiplexers require parser 108 that the elementary bit stream Payload is loaded on NALU2RBSP to obtain the raw byte sequence load that stores usefulness in second first-in first-out buffer 109.

Bit stream manager 112 reads the raw byte sequence load that is stored among the RBSP FIFO 109, and according to grammars and 101 cancellation conversion are stored in the raw byte sequence load among the RBSP FIFO 109 to Video Decoder.

Except the elementary bit stream/basic bit that stores packetized streamed bit stream and raw byte sequence load; BSB FIFO 104 here and RBSP FIFO 109 are used for indicating bit stream according to different purposes, and (for example: empty, empty, half-full, full or state completely almost almost) to point out its full state produce its state index that has separately.The state index of BSB FIFO 104 and RBSP FIFO 109 can be transmitted and received by interrupt control unit 110; And be used to produce interrupt signal based on preset interruption configuration; For example one [sky] interrupt signal or one [expiring] interrupt signal; Wherein should preset interruption configuration can be preset empty configuration or preset full configuration, make that Video Decoder 101 can be at checking mode or do not switch in the checking mode, be stored in the raw byte sequence load among the RBSP FIFO 109 with loading.In a similar embodiment; Those skilled in the art all can understand under any this invention: in order to produce interrupt signal and to make BSB FIFO 104 and RBSP FIFO 109 can reach preferable utilance, but preset interruption configuration individual design.

Fig. 3 is the flow chart of the operation of displayed map 1 bitstream buffer controller 100.

About step 301; Bitstream buffer controller 100 is in initial condition, and incoming bit stream is stored among the BSB FIFO 104 herein, and the raw byte sequence load of taking from incoming bit stream then is stored among the RBSP FIFO 109; Video Decoder 101 then is in checking mode, to load the raw byte sequence load that is stored among the RBSPFIFO 109; That is to say that when Video Decoder 101 was stored in the raw byte sequence load among the RBSP FIFO 109 in loading, Video Decoder 101 is the full state index of inspection RBSP FIFO 109 at every turn; For example, bit stream can load through memory interface.In addition; Incoming bit stream is loaded on the process of BSB FIFO 104 and can be ended or requirement according to the full state of BSB FIFO 104, and the raw byte sequence that is removed load is loaded on the process of RBSPFIFO 109 and can also be ended or requirement according to the full state of RBSP FIFO 109.In addition; If incoming bit stream is that the basic bit of packetized is streamed; The incoming bit stream that is stored in BSB FIFO 104 can be by analysis to obtain the streamed Payload of basic bit, and streamed bit stream of the basic bit that is transfused to or the streamed Payload of basic bit that is removed can be by analysis to obtain the raw byte sequence load that stores usefulness among the RBSPFIFO 109.

About step 302, the interrupt control unit 110 of bitstream buffer controller 100 detects the full state of BSB FIFO104 and RBSP FIFO 109.

About step 303, whether the full state that interrupt control unit 110 detects BSB FIFO 104 and RBSP FIFO 109 satisfies preset interruption configuration, and for example preset [sky] interrupts configuration or preset [expiring] interruption configuration.

Then, Video Decoder 101 is not switching between checking mode and the checking mode, is stored in the raw byte sequence load of RBSP FIFO 109 with loading, so reduces the frequency of inquiry first in first out state.For example; At step 304 place; Satisfy should presetly interrupt configuration the time when interrupting full state that controller 110 detects BSB FIFO 104 and BSP FIFO109, Video Decoder 101 is loading the raw byte sequence load that is stored among the RBSP FIFO 109 in the checking mode; On the contrary; At step 305 place; Do not satisfy should presetly interrupt configuration the time when interrupting full state that controller 110 detects BSB FIFO 104 and BSP FIFO 109, Video Decoder 101 loads the raw byte sequence that is stored among the RBSP FIFO 109 and loads in checking mode.The aforementioned configuration of should preset interrupting can be that one preset [sky] interrupts configuration, one preset [expire] and interrupt configuration, perhaps by individual design producing interrupt signal, and then make BSB FIFO 104 and RBSP FIFO 109 can reach preferable utilance.

Get back to step 302 and step 303 subsequently; The interrupt control unit 110 of this place's bitstream buffer controller 100 detects the full state of BSB FIFO 104 and RBSP FIFO 109 once more, and whether the state index that detects BSBFIFO 104 and RBSP FIFO 109 satisfies and should presetly interrupt configuration.

Do not switching rightly between checking mode and the checking mode through Video Decoder 101; Be stored in the raw byte sequence load among the RBSP FIFO 109 with loading; Therefore reduce the frequency of inquiry first in first out state; And have the help of interrupt control unit 101 and the utilance of BSB FIFO 104 and RBSP FIFO 109, so the usefulness of Video Decoder 101 can improve significantly.

At last; Those skilled in the art all understand under this invention, and more than narration and embodiment are merely the preferred embodiment and the implementation detail of the present invention's demonstration and exposure, are not intended to limit scope of the present invention; Those skilled in the art should know and do not breaking away from the spirit and scope of the present invention under any this invention; Can do a little change and retouching, therefore, protection scope of the present invention is when accurate with the position of defining in the accompanying claims.

Claims

1. bitstream buffer controller that is used for Video Decoder, it comprises:

First first-in first-out buffer is in order to store incoming bit stream;

Second first-in first-out buffer, in order to store Payload, wherein this Payload is taken from this incoming bit stream; And

Interrupt control unit; Second state index in order to first state index of following the trail of this first first-in first-out buffer and this second first-in first-out buffer; And, first and second state indexs according to this first first-in first-out buffer and this second first-in first-out buffer produce interrupt signal when pre-conditioned when satisfying; Make this Video Decoder to from the Payload of second first-in first-out buffer with a kind of loading the in first operator scheme and second operator scheme; Wherein, When this Video Decoder loaded with first operator scheme the pay(useful) load from second first-in first-out buffer, this this second state index of Video Decoder inspection was when this Video Decoder loads with second operator scheme the pay(useful) load from second first-in first-out buffer; This Video Decoder is not checked this second state index, and this this interrupt signal of Video Decoder response is switched between first operator scheme and second operator scheme.

2. bitstream buffer controller as claimed in claim 1; Wherein this Video Decoder is decoder H.264/AVC; This first first-in first-out buffer is the bit stream first-in first-out buffer, and this second first-in first-out buffer is a raw byte sequence load first-in first-out buffer.

3. bitstream buffer controller as claimed in claim 2; Also comprise: the elementary bit stream parser of packetized; If this incoming bit stream is that the basic bit of packetized is streamed, then the elementary bit stream parser of this packetized this incoming bit stream from be stored in this bit stream first-in first-out buffer is obtained the streamed Payload of basic bit; And the parser of network abstract layer unit to raw byte sequence load; If this incoming bit stream is that the basic bit of packetized is streamed; Then the parser of this network abstract layer unit to raw byte sequence load is obtained the raw byte sequence load from the streamed Payload of basic bit of the elementary bit stream parser output of packetized; If this incoming bit stream is that basic bit is streamed, then the basic bit streamed bit stream of parser from be stored in this bit stream first-in first-out buffer of this network abstract layer unit to raw byte sequence load obtained the raw byte sequence load.

4. bitstream buffer controller as claimed in claim 2 also comprises the management of process device, in order to control the process that this incoming bit stream loads this bit stream first-in first-out buffer and this raw byte sequence load first-in first-out buffer.

5. bitstream buffer controller as claimed in claim 4; Wherein this management of process device comprises bitstream buffer controller and multiplexer; This bitstream buffer controller can be according to first state index of this bit stream first-in first-out buffer and in order to ending and to require this incoming bit stream to load this bit stream first-in first-out buffer, and this multiplexer is according to second state index of this raw byte sequence load first-in first-out buffer and in order to end and to require the raw byte sequence load to load this raw byte sequence load first-in first-out buffer.

6. bitstream buffer controller as claimed in claim 2 also comprises memory interface, and it connects this incoming bit stream of the storage of this bit stream first-in first-out buffer.

7. bitstream buffer controller as claimed in claim 2 also comprises the bit stream manager, in order to cancel conversion raw byte sequence load according to grammars.

8. bitstream buffer controller as claimed in claim 2; Wherein when first state index of this bit stream first-in first-out buffer was preset the interruption configuration with second state index of this raw byte sequence load first-in first-out buffer is satisfied, this interrupt control unit made this Video Decoder switch to first operator scheme in order to produce interrupt signal.

9. bit stream buffer control method that is used for Video Decoder, it comprises:

Receive and store the incoming bit stream of first first-in first-out buffer;

Obtain Payload and be stored in second first-in first-out buffer, this Payload is taken from this incoming bit stream in first first-in first-out buffer; And

When second state index of first state index of this first first-in first-out buffer and second first-in first-out buffer satisfies when pre-conditioned; Produce interrupt signal; Make this Video Decoder switch to second mode of operation from first mode of operation; Wherein when this Video Decoder loads with first operator scheme the pay(useful) load from second first-in first-out buffer; This this second state index of Video Decoder inspection, when this Video Decoder loaded with second operator scheme the pay(useful) load from second first-in first-out buffer, this Video Decoder was not checked this second state index.

10. bit stream buffer control method as claimed in claim 9; Wherein this Video Decoder is decoder H.264/AVC; This first first-in first-out buffer is the bit stream first-in first-out buffer, and this second first-in first-out buffer is a raw byte sequence load first-in first-out buffer.

11. bit stream buffer control method as claimed in claim 10; Also comprise: streamed if this incoming bit stream is the basic bit of packetized, then this incoming bit stream from be stored in this bit stream first-in first-out buffer is obtained the streamed Payload of basic bit; And obtain the raw byte sequence load from the streamed bit stream of basic bit of the streamed Payload of this basic bit obtained or input.

12. bit stream buffer control method as claimed in claim 10 also comprises: end and require this this bit stream first-in first-out buffer of incoming bit stream loading according to first state index of this bit stream first-in first-out buffer; And end and require the raw byte sequence load to load raw byte sequence load first-in first-out buffer according to second state index of this raw byte sequence load first-in first-out buffer.

13. bit stream buffer control method as claimed in claim 10 also comprises through memory interface to receive the step of this incoming bit stream.

14. bit stream buffer control method as claimed in claim 10 also comprises the step of exporting the raw byte sequence load of being obtained according to the grammars of this Video Decoder.