CN101888181B - Charge pump circuit based on feedback - Google Patents

Abstract

The invention relates to a charge pump circuit which comprises a high-voltage generating unit, a voltage reducing unit and a feedback control unit. The voltage reducing unit and the feedback control unit are added on the basis of the traditional charge pump circuit; the gain of a charge pump of the high-voltage generating unit is irrelevant to the threshold voltage of an MOS (Metal Oxide Semiconductor) pipe, and the boosting efficiency is improved by more than 20 percent; the charge pump adopts such a way that two charge passages alternately charge a load so that the charge speed of the charge pump is improved more than twice; and the charge pump obtains a continuous output voltage value in a certain range in a feedback way, and an output voltage value is larger than the voltage of a power supply. The invention has the advantages of high boosting efficiency, high charge speed and continuous voltage value output, effectively overcomes the defects of low boosting efficiency, low charge speed and discrete voltage value output of the traditional charge pump circuit and can be widely applied to the field of digital-analog mixing circuits.

Description

Charge pump circuit based on feedback

Technical field

The present invention relates to a kind of charge pump circuit, particularly a kind of charge pump circuit based on feedback.Its direct applied field is the hybrid digital analog circuit greater than the high voltage drive of supply voltage.

Background technology

In hybrid digital analog circuit, along with the further reduction of supply voltage, fully conducting, the not even conducting in normal supply voltage scope of some analog switches.Therefore, need the charge pump circuit that can produce high voltage (greater than supply voltage), be used to drive the analog switch of high voltage requirements.

At present, traditional charge pump circuit is based on the charge pump circuit that Dickson proposes, and the gain of this type charge pump circuit is:

$\mathrm{\ΔV}=V_{\mathrm{DD}}\×\frac{C_{\mathrm{pump}}}{C_{\mathrm{pump}}+C_{\mathrm{parasitic}}}-V_{\mathrm{thn}}---\left(1\right)$

The magnitude of voltage that charge pump gain increases for each charge pump stage, in the formula, Δ V is a charge pump gain, V _DDBe the change in voltage (equaling supply voltage this moment) of pump node, C _PumpBe pump electric capacity, C _ParasiticBe parasitic capacitance, V _ThnThreshold voltage for nmos pass transistor.

The output voltage of charge pump circuit is:

V _OUT＝V _DD+n·ΔV (2)

In the formula, V _OUTBe output voltage, n is the progression of charge pump.

Can know that by (1) formula charge pump gain is the difference that the change in voltage dividing potential drop of pump node deducts the threshold voltage of NMOS pipe, if the V that adopts _DDBe 3.3V, V _ThnBe 0.8V, C _PumpMuch larger than C _Parasitic, then charge pump gain is merely about 75% of pump node voltage variation, and therefore the supercharging efficient of traditional charge pump circuit is not high; Can know by (2) formula, increase or reduce V _OUTCan only increase or reduce the progression n of charge pump, because V _OUTCan only increase or reduce the integral multiple of Δ V, cause the output voltage of conventional charge pump circuit not regulate continuously; In addition, conventional charge pump circuit is to charge to load with single-channel mode, and therefore, charging rate is also slower.

Summary of the invention

For overcoming the problem that supercharging efficient is not high, output voltage can not be regulated continuously, charging rate is slow of conventional charge pump circuit, the present invention provides a kind of charge pump circuit based on feedback that high voltage (greater than supply voltage) can be provided.

For realizing above-mentioned purpose, the present invention solves the problems of the technologies described above the technical scheme of being taked and is: a kind of charge pump circuit based on feedback, and it contains:

A high voltage generation unit comprises:

PMOS manages P ₁～P ₅, NMOS manages N ₁～N ₈, capacitor C ₁～C ₄, wherein, P ₁Grid meet the input V of this high voltage generation unit _J, P ₁Source electrode meet power supply V _DD, P ₁Drain electrode and P ₂Source electrode and substrate, P ₃Source electrode and substrate join and and C ₁Top crown link together C ₁Bottom crown ground connection V _SS, P ₂, N ₁Grid meet the first clock end CLK ₁, P ₃, N ₂Grid meet second clock end CLK ₂, P ₂, N ₁Drain electrode and C ₃Bottom crown join P ₃, N ₂Drain electrode and C ₂Bottom crown join N ₁, N ₂Source ground V _SS, N ₃Source electrode and N ₅Source electrode, N ₆Grid, P ₄Grid, P ₅Drain electrode, N ₈Drain electrode join and and C ₂Top crown link together N ₄Source electrode and N ₆Source electrode, N ₅Grid, P ₅Grid, P ₄Drain electrode, N ₇Drain electrode join and and C ₃Top crown link together N ₃Grid, N ₃Drain electrode, N ₄Grid, the drain electrode of N4, N ₅Drain electrode, N ₆Drain electrode all meet power supply V _DD, N ₇Grid meet second clock end CLK ₂, N ₈Grid meet the first clock end CLK ₁, N ₇Source electrode and P ₄Source electrode, P ₄Substrate, P ₅Source electrode, P ₅Substrate, N ₈Source electrode join and form first tie point, this first tie point and C ₄Top crown link together and said first tie point output of high voltage generation unit, i.e. the output V of whole charge pump circuit for this reason _OUT, C ₄Bottom crown ground connection V _SSWith

A pressure unit comprises:

PMOS manages P ₆～P ₇, NMOS manages N ₉～N ₁₄, capacitor C ₅～C ₇, wherein, N ₉Source electrode, P ₆Source electrode, P ₆Substrate, P ₇Source electrode, P ₇Substrate, N ₁₀The source electrode all input of pressure unit, i.e. the output V of high-voltage generating unit therewith _OUTJoin N ₉Drain electrode and P ₆Drain electrode, N ₁₁Drain electrode, N ₁₂Drain electrode, P ₇Grid, N ₁₃Grid join and and C ₅Top crown link together N ₁₀Drain electrode and P ₇Drain electrode, N ₁₃Drain electrode, N ₁₄Drain electrode, P ₆Grid, N ₁₂Grid join and and C ₆Top crown link together N ₉Grid, C ₅Bottom crown, N ₁₄Grid and second clock end CLK ₂Join N ₁₀Grid, C ₆Bottom crown, N ₁₁The grid and the first clock end CLK ₁Join N ₁₁Source electrode and N ₁₂Source electrode, N ₁₃Source electrode, N ₁₄Source electrode join and form second tie point, this second tie point and C ₇Top crown link together and said second tie point output V of pressure unit for this reason _FB, C ₇Bottom crown ground connection V _SSWith

A feedback control unit comprises:

PMOS manages P ₈～P ₉, NMOS manages N ₁₅～N ₁₈, wherein, P ₈Source electrode, P ₉Source electrode meet power supply V _DD, P ₈Grid and drain electrode, P ₉Grid and N ₁₅Drain electrode join P ₉Drain electrode and N ₁₆Drain electrode join and form the 3rd tie point, the 3rd tie point is the output V of feedback control unit for this reason _J, i.e. the input V of high-voltage generating unit _J, N ₁₅Grid meet the input of this feedback control unit, i.e. the output V of pressure unit _FB, N ₁₆Grid meet the input V of this feedback control unit _REF, N ₁₅Source electrode, N ₁₆Source electrode and N ₁₇Drain electrode join N ₁₇Grid, N ₁₈Grid, N ₁₈Drain electrode input I of feedback control unit therewith all _BIASJoin N ₁₇Source electrode, N ₁₈Source grounding V _SS

Said charge pump circuit can produce the continually varying output voltage values, and output voltage is greater than supply voltage.

Said charge pump circuit can utilize feedback function to regulate the output voltage of charge pump, and output voltage is changed with the variation of input voltage.

The charge pump gain of said charge pump circuit and the threshold voltage of metal-oxide-semiconductor are irrelevant.

Said charge pump circuit comprises two charging paths, under the control of clock, alternately charges to load.

Beneficial effect:

Charge pump circuit based on feedback of the present invention comprises a high voltage generation unit, a pressure unit and a feedback control unit, compares with conventional charge pump circuit, and it has following characteristics:

1. conventional charge pump circuit only comprises a high-voltage generating unit; And charge pump circuit of the present invention has increased a pressure unit and a feedback control unit on the conventional charge pump circuit basis, and the function that makes full use of feedback is regulated the output voltage of charge pump.

2. the charge pump gain of conventional charge pump circuit is influenced by threshold voltage, causes its supercharging efficient low, and charge pump circuit of the present invention, the threshold voltage of its charge pump gain and metal-oxide-semiconductor is irrelevant, can make supercharging efficient improve more than 20%.

3. conventional charge pump circuit only has a charging path, and under clock control, pump electric capacity needs half clock cycle precharge; Charge to load with half clock cycle again, so charging rate is slower, and charge pump circuit of the present invention adopts two charging paths; Alternately to the load charging modes; Pump electric capacity was all charged to load in the whole clock cycle, add the raising of supercharging efficient, so charging rate is brought up to more than the twice.

4. in the conventional charge pump circuit; Change output voltage values and realize that through the progression that changes charge pump every grade of charge pump gain is fixed, can only obtain some discrete magnitudes of voltage; Therefore its output voltage values is discontinuous; And charge pump circuit of the present invention can be realized the continuous adjusting of charge pump output voltage through the input voltage that continuously changes feedback control unit, so can obtain any output voltage values in the certain limit.

In sum; The charge pump circuit advantage that tool supercharging efficient is high simultaneously, charging rate is fast, output voltage values is continuous based on feedback of the present invention, the supercharging efficient that has effectively overcome conventional charge pump circuit is low, output voltage values discrete, the slow shortcoming of charging rate.

Description of drawings

Fig. 1 is the overall circuit block diagram based on the charge pump circuit that feeds back of the present invention;

Fig. 2 is the circuit diagram of the high voltage generation unit among Fig. 1 of the present invention;

Fig. 3 is the circuit diagram of the pressure unit among Fig. 1 of the present invention;

Fig. 4 is the circuit diagram of the feedback control unit among Fig. 1 of the present invention.

Embodiment

Embodiment of the present invention is not limited only to following description, combines accompanying drawing to further specify at present.

A kind of charge pump circuit general structure based on feedback of practical implementation of the present invention is as shown in Figure 1.It is made up of a high-voltage generating unit, a pressure unit and a feedback control unit.Wherein, the circuit diagram of high-voltage generating unit is as shown in Figure 2, comprising: PMOS manages P ₁～P ₅, NMOS manages N ₁～N ₈, capacitor C ₁～C ₄, high-voltage generating unit is used to produce the high voltage greater than supply voltage.The circuit diagram of pressure unit is as shown in Figure 3, comprising: PMOS manages P ₆～P ₇, NMOS manages N ₉～N ₁₄, capacitor C ₅～C ₇, pressure unit reduces high voltage in the supply voltage scope, so that feedback control unit compares feedback.The circuit diagram of feedback control unit is as shown in Figure 4, comprises PMOS pipe P ₈～P ₉, NMOS manages N ₁₅～N ₁₈, feedback control unit compares value and the input voltage of output voltage after step-down, and result relatively is used to control circuit for producing high voltage, realizes the FEEDBACK CONTROL to the charge pump circuit output HIGH voltage.

Concrete annexation among Fig. 2 is identical with the summary of the invention part of this specification, no longer repeats here.Its operation principle is following:

Clock CLK ₁And CLK ₂Be two mutually non-overlapping clocks, work as CLK ₁Be high level, CLK ₂During for low level, N ₁Conducting, C ₃The sole plate earthing, N ₄Or N ₆Be C ₃Charging (N during initial state ₄Be C ₃Charging, during stable state, N ₆Be C ₃Charging), C during stable state ₃Top crown is charged to V _DDWork as CLK ₁Be low level, CLK ₂During for high level, P ₂Conducting, C ₃Sole plate and C ₁Top crown (the C that links to each other ₁Be V during top crown voltage stable state ₁), therefore by C ₃Top crown node charge conservation, C in the time of can getting stable state ₃Top crown voltage is lifted height and is arrived:

$V_3=V_1\×\frac{C_3}{C_3+C_{p3}}+V_{\mathrm{DD}}---\left(3\right)$

In the formula, C _P3Be C ₃The parasitic capacitance of top crown node.

In like manner, work as CLK ₁Be low level, CLK ₂During for high level, C during stable state ₂Top crown is charged to V _DDWork as CLK ₁Be high level, CLK ₂During for low level, C during stable state ₂Top crown voltage is lifted height and is arrived:

$V_2=V_1\×\frac{C_2}{C_2+C_{p2}}+V_{\mathrm{DD}}---\left(4\right)$

In the formula, C _P2Be C ₂The parasitic capacitance of top crown node.

Because circuit adopts symmetric design, therefore

C ₂＝C ₃＝C _2，3 (5)

C _p2＝C _p3＝C _p2，3 (6)

Have (3)～(6) Shi Kede:

V ₃＝V ₂＝V _DD+ΔV ₁ (7)

Wherein, ${\mathrm{\Δ\; V}}_1=V_1\×\frac{C_3}{C_3+C_{p3}}=V_1\×\frac{C_2}{C_2+C_{p2}}=V_1\×\frac{C_{\mathrm{2,3}}}{C_{\mathrm{2,3}}+C_{p\mathrm{2,3}}}---\left(8\right)$

If

ΔV ₁＞|V _thp| (9)

In the formula, V _ThpBe the transistorized threshold voltage of PMOS.

Work as CLK ₁Be high level, CLK ₂During for low level, during initial state, P ₄, P ₅, N ₇End N ₈Conducting, C ₂To C ₄Charging; During stable state, because C ₂Top crown voltage is lifted high to (V _DD+ Δ V ₁), C ₃Top crown voltage is V _DD, can know P by (9) formula ₄, N ₇, N ₈End P ₅Conducting, C ₂With C ₄Top crown is charged to (V _DD+ Δ V ₁).Work as CLK ₁Be low level, CLK ₂During for high level, during initial state, P ₄, P ₅, N ₈End N ₇Conducting, C ₃To C ₄Charging; During stable state, because C ₃Top crown voltage is lifted high to (V _DD+ Δ V ₁), C ₂Top crown voltage is V _DD, by ( ₉) formula can know P ₅, N ₇, N ₈End P ₄Conducting, C ₃With C ₄Top crown is charged to (V _DD+ Δ V ₁).Thus it is clear that, at clock CLK ₁And CLK ₂Control under, C ₂And C ₃Alternately to C ₄Charging finally makes C ₄Top crown voltage, promptly output voltage reaches following stationary value:

V _OUT＝V _DD+ΔV ₁ (10)

Concrete annexation among Fig. 3 is identical with the summary of the invention part of this specification, no longer repeats here.Its operation principle is following:

Work as CLK ₁Be high level, CLK ₂During for low level, during initial state, P ₆, P ₇, N ₉End N ₁₀Conducting, V _OUTTo C ₆Charging, N ₁₂, N ₁₃, N ₁₄End N ₁₁Conducting, C ₅To C ₇Charging; During stable state, P ₆, N ₉, N ₁₀End P ₇Conducting, N ₁₁, N ₁₃, N ₁₄End N ₁₂Conducting.At this moment, C ₆Top crown voltage is V _OUT, by C ₅Top crown node charge conservation can get C ₅Top crown voltage is:

$V_5=V_{\mathrm{OUT}}-V_{\mathrm{DD}}\×\frac{C_5}{C_5+C_{p5}}---\left(11\right)$

In the formula, C _P5Be C ₅The parasitic capacitance of top crown node, at this moment, C ₅With C ₇Top crown is charged to V ₅

Work as CLK ₁Be low level, CLK ₂During for high level, during initial state, P ₆, P ₇, N ₁₀End N ₉Conducting, V _OUTTo C ₅Charging, N ₁₁, N ₁₂, N ₁₃End N ₁₄Conducting, C ₆To C ₇Charging; During stable state, P ₇, N ₉, N ₁₀End P ₆Conducting, N ₁₁, N ₁₂, N ₁₄End N ₁₃Conducting.At this moment, C ₅Top crown voltage is V _OUT, by C ₆Top crown node charge conservation can get C ₆Top crown voltage is:

$V_6=V_{\mathrm{OUT}}-V_{\mathrm{DD}}\×\frac{C_6}{C_6+C_{p6}}---\left(12\right)$

In the formula, C _P6Be C ₆The parasitic capacitance of top crown node, at this moment, C ₆With C ₇Top crown is charged to V ₆

Because circuit adopts symmetric design, therefore have:

C ₅＝C ₆＝C ₅， ₆ (13)

C _p5＝C _p6＝C _p5，6 (14)

By (11)～(14) formula, can get:

V ₅＝V ₆＝V _OUT-ΔV ₂ (15)

In the formula, ${\mathrm{\Δ\; V}}_2=V_{\mathrm{DD}}\×\frac{C_5}{C_5+C_{p5}}=V_{\mathrm{DD}}\×\frac{C_6}{C_6+C_{p6}}=V_{\mathrm{DD}}\×\frac{C_{\mathrm{5,6}}\×}{C_{\mathrm{5,6}}+C_{p\mathrm{5,6}}}---\left(16\right)$

Thus it is clear that, C ₅With C ₆Under clock control, replace by V _OUTCharging, and to C ₇Charging obtains V _OUTValue after step-down:

V _FB＝V ₅＝V ₆＝V _OUT-ΔV ₂ (17)

Concrete annexation among Fig. 4 is identical with the summary of the invention part of this specification, no longer repeats here.Its operation principle is following:

I _BIASFor the bias current input, through N ₁₈To N ₁₇Mirror image, for amplifier provides biasing, V _REFBe input voltage.Work as V _FBLess than V _REFThe time, V _JReduce, make V among Fig. 2 ₁Raise, can know by (8) and (10) formula, during stable state, V _OUTTo raise; Work as V _FBGreater than V _REFThe time, V _JIncrease, make V among Fig. 2 ₁Reduce, can know V during stable state by (8) and formula (10) formula _OUTTo reduce; Up to V _FBEqual V _REFThe time, V _OUTReach homeostasis, can know by (16) and (17) formula, at this moment,

$V_{\mathrm{OUT}}={\mathrm{\ΔV}}_2+V_{\mathrm{FB}}=V_{\mathrm{DD}}\×\frac{C_{\mathrm{5,6}}}{C_{\mathrm{5,6}}+C_{p\mathrm{5,6}}}+V_{\mathrm{REF}}---\left(18\right)$

In sum, at first, contrast (1) formula can be known charge pump gain Δ V with (8) formula ₁Irrelevant with the threshold voltage of NMOS pipe, and work as the change in voltage V of pump node ₁=V _DDThe time, the charge pump gain Δ V of circuit of the present invention ₁Charge pump gain Δ V than conventional charge pump circuit has increased a threshold voltage value V _Thn, if C _2,3Much larger than C _P2,3, then charge pump gain is about 100% of pump node voltage variation; Secondly, can know,, make to continuously change V owing to introduced feedback by formula (18) _REFCan make V _OUTContinuously change thereupon, therefore, the problem that the circuit structure of circuit of the present invention has avoided the output voltage of conventional charge pump circuit not regulate continuously; Simultaneously, the mode that circuit of the present invention has adopted binary channel to replace, the full clock cycle is added the raising of charge pump gain continuously to the load charging, and charging rate is brought up to more than 2 times of conventional charge pump circuit.

In addition, in order further to improve operating rate, the metal-oxide-semiconductor that discharges and recharges on the path of the present invention, i.e. P ₂～P ₇, N ₁～N ₁₄All adopt minimum grid long.For realizing to output voltage V _OUTTrickle charge and continuous sampling feedback, make C ₂, C ₃To C ₄Alternately charging, C ₅, C ₆To V _OUTAlternating sampling and step-down, circuit of the present invention adopts symmetric design, i.e. P ₂, P ₃Physical dimension is identical, N ₁, N ₂Physical dimension is identical, C ₂, C ₃Physical dimension is identical, N ₃, N ₄Physical dimension is identical, N ₅, N ₆Physical dimension is identical, N ₇, N ₈Physical dimension is identical, P ₄, P ₅Physical dimension is identical, N ₉, N ₁₀Physical dimension is identical, P ₆, P ₇Physical dimension is identical, N ₁₁, N ₁₄Physical dimension is identical, N ₁₂, N ₁₃Physical dimension is identical, P ₈, P ₉Physical dimension is identical, N ₁₅, N ₁₆Physical dimension is identical, N ₁₇And N ₁₈Channel length is identical, and width is proportional.

Manufacturing process of the present invention is general Si-gate N trap CMOS technology.

The basic parameter of the PMOS in the circuit of the present invention, NMOS pipe is:

The threshold voltage V of NMOS pipe _Thn: 0.6～0.8V;

The threshold voltage V of PMOS pipe _Thp:-0.6～-0.8V;

Input voltage V _REF＞1V.

Claims (5)

1. One kind based on the feedback charge pump circuit, it is characterized in that it contains:

   A high voltage generation unit comprises:

   PMOS manages P ₁～P ₅, NMOS manages N ₁～N ₈, capacitor C ₁～C ₄, wherein, P ₁Grid meet the input V of this high voltage generation unit _J, P ₁Source electrode meet power supply V _DD, P ₁Drain electrode and P ₂Source electrode and substrate, P ₃Source electrode and substrate join and and C ₁Top crown link together C ₁Bottom crown ground connection V _SS, P ₂, N ₁Grid meet the first clock end CLK ₁, P ₃, N ₂Grid meet second clock end CLK ₂, P ₂, N ₁Drain electrode and C ₃Bottom crown join P ₃, N ₂Drain electrode and C ₂Bottom crown join N ₁, N ₂Source ground V _SS, N ₃Source electrode and N ₅Source electrode, N ₆Grid, P ₄Grid, P ₅Drain electrode, N ₈Drain electrode join and and C ₂Top crown link together N ₄Source electrode and N ₆Source electrode, N ₅Grid, P ₅Grid, P ₄Drain electrode, N ₇Drain electrode join and and C ₃Top crown link together N ₃Grid, N ₃Drain electrode, N ₄Grid, the drain electrode of N4, N ₅Drain electrode, N ₆Drain electrode all meet power supply V _DD, N ₇Grid meet second clock end CLK ₂, N ₈Grid meet the first clock end CLK ₁, N ₇Source electrode and P ₄Source electrode, P ₄Substrate, P ₅Source electrode, P ₅Substrate, N ₈Source electrode join and form first tie point, this first tie point and C ₄Top crown link together and said first tie point output of high voltage generation unit, i.e. the output V of whole charge pump circuit for this reason _OUT, C ₄Bottom crown ground connection V _SSWith

   A pressure unit comprises:

   PMOS manages P ₆～P ₇, NMOS manages N ₉～N ₁₄, capacitor C ₅～C ₇, wherein, N ₉Source electrode, P ₆Source electrode, P ₆Substrate, P ₇Source electrode, P ₇Substrate, N ₁₀The source electrode all input of pressure unit, i.e. the output V of high-voltage generating unit therewith _OUTJoin N ₉Drain electrode and P ₆Drain electrode, N ₁₁Drain electrode, N ₁₂Drain electrode, P ₇Grid, N ₁₃Grid join and and C ₅Top crown link together N ₁₀Drain electrode and P ₇Drain electrode, N ₁₃Drain electrode, N ₁₄Drain electrode, P ₆Grid, N ₁₂Grid join and and C ₆Top crown link together N ₉Grid, C ₅Bottom crown, N ₁₄Grid and second clock end CLK ₂Join N ₁₀Grid, C ₆Bottom crown, N ₁₁The grid and the first clock end CLK ₁Join N ₁₁Source electrode and N ₁₂Source electrode, N ₁₃Source electrode, N ₁₄Source electrode join and form second tie point, this second tie point and C ₇Top crown link together and said second tie point output V of pressure unit for this reason _FB, C ₇Bottom crown ground connection V _SSWith

   A feedback control unit comprises:

   PMOS manages P ₈～P ₉, NMOS manages N ₁₅～N ₁₈, wherein, P ₈Source electrode, P ₉Source electrode meet power supply V _DD, P ₈Grid and drain electrode, P ₉Grid and N ₁₅Drain electrode join P ₉Drain electrode and N ₁₆Drain electrode join and form the 3rd tie point, the 3rd tie point is the output V of feedback control unit for this reason _J, i.e. the input V of high-voltage generating unit _J, N ₁₅Grid meet the input of this feedback control unit, i.e. the output V of pressure unit _FB, N ₁₆Grid meet the input V of this feedback control unit _REF, N ₁₅Source electrode, N ₁₆Source electrode and N ₁₇Drain electrode join N ₁₇Grid, N ₁₈Grid, N ₁₈Drain electrode input I of feedback control unit therewith all _BIASJoin N ₁₇Source electrode, N ₁₈Source grounding V _SS
2. 2. a kind of charge pump circuit based on feedback according to claim 1, it is characterized in that: said charge pump circuit can produce the continually varying output voltage values, and output voltage is greater than supply voltage.
3. 3. a kind of charge pump circuit based on feedback according to claim 1, it is characterized in that: said charge pump circuit can utilize feedback function to regulate the output voltage of charge pump, and output voltage is changed with the variation of input voltage.
4. 4. a kind of charge pump circuit based on feedback according to claim 1, it is characterized in that: the charge pump gain of said charge pump circuit and the threshold voltage of metal-oxide-semiconductor are irrelevant.
5. 5. a kind of charge pump circuit based on feedback according to claim 1, it is characterized in that: said charge pump circuit comprises two charging paths, under the control of clock, alternately charges to load.

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