CN101882468B - Address signal transmission method and storage system - Google Patents
Address signal transmission method and storage system Download PDFInfo
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- CN101882468B CN101882468B CN 200910138195 CN200910138195A CN101882468B CN 101882468 B CN101882468 B CN 101882468B CN 200910138195 CN200910138195 CN 200910138195 CN 200910138195 A CN200910138195 A CN 200910138195A CN 101882468 B CN101882468 B CN 101882468B
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Abstract
The invention discloses an address signal transmission method and a storage system. The address signal transmission method is used for transmitting an address signal to a storage, and the address signal is divided into an original MSB (Most Significant Bit) group and an LSB (Least Significant Bit) group. The address signal transmission method comprises the steps of: firstly, transmitting the MSB group, wherein the transmitted MSB group comprises one part of the original MSB group and one part of the LSB group; and secondly, transmitting the LSB group.
Description
Technical field
The invention relates to a kind of address signal transmission method, and particularly relevant for a kind of address signal transmission method that is applied to serial type flash memory (Serial flash).
Background technology
In existing technology, serial type flash memory (Serial Flash) technology exists, and is widely used in the various electronic products.In general, serial type flash memory receives access instruction and address signal via its output input pin (Pin) sequence ground, and the sending and receiving access data.
In general, serial type flash memory selects pin, input pin and output connecting pin to come receiving frequency signals, receiving chip selection signal, reception access control set and address signal and output access data respectively via frequency signal pin, chip.Read operation with serial type flash memory is an example; The chip select signal CS that chip selects pin to receive is low-signal levels constantly; Frequency signal pin receiving frequency signals SCLK; And read serial data comprise with frequency signal SCLK be 8 (Bit) steering orders, 24 bit address signals and some pens of benchmark (Clock Based) with 8 reading of data, as shown in Figure 1.Wherein in 6 buffer circles (Dummy Cycle) after receiving address signal, flash memory carries out read operation according to the start address of address signal indication to the memory array of flash memory.So, behind n buffer circle, to provide many to be the reading of data of unit with 8.
Yet in above-mentioned example, flash memory needs in 6 buffer circles, to accomplish the read operations such as data that the corresponding memory block of activation word line (WordLine) voltage, bit line (Bit Line) voltage and sensing stores.In general, too short time for reading can cause reading the result and makes a mistake easily.Therefore, how to strive under existing communications protocol that the more data time for reading is one of direction of constantly endeavouring of industry.
Summary of the invention
The invention relates to a kind of accumulator system, it is to use a plurality of output input pins to come the receiver address data.The accumulator system that the present invention is correlated with is more utilized some idle most significant bits (Most Significant Bit in the address signal according to the memory capacity of storer; MSB) come least significant bits in the signal of transport address (Least Significant Bit, LSB) middle position partly.So, compared to conventional flash memory, the accumulator system that the present invention is correlated with can be striven for the more data time for reading effectively.
According to an aspect of the present invention; Propose a kind of address signal transmission method, to storer, address signal is divided into an original most significant bits (Most Significant Bit in order to the transport address signal; MSB) crowd and a least significant bits (Lest Significant Bit, LSB) crowd.Address signal transmission method comprises the following steps.At first transmit a MSB crowd, this MSB crowd comprises this a part of original MSB crowd and this a part of LSB crowd.Transmit this LSB crowd afterwards.
According to a further aspect in the invention, propose a kind of accumulator system, comprise storer and host side circuit.The host side circuit determines an idle MSB crowd and a normal bit crowd of an address signal according to the memory span of storer.The host side circuit is exported this replacement position crowd to storer, and is exported this normal bit crowd between second transmission period to storer according to this idle MSB crowd in this address signal of replacement position crowd's replacement of this address signal between first transmission period.Wherein this replaces the last position crowd of order of transmission in the corresponding normal bit so far of position crowd.
In accordance with a further aspect of the present invention, propose a kind of address signal transmission method, to storer, address signal transmission method comprises the following steps in order to the transport address signal.At first determine an idle MSB crowd and a normal bit crowd of address signal according to the memory span of storer.Then replace the position crowd according to one of this address signal and replace this idle MSB crowd in the address signal, wherein this replaces the last position crowd of order of transmission among the corresponding normal bit crowd so far of position crowd.This replacement position crowd of output is to storer in then between first transmission period.This normal bit of output crowd is to storer in afterwards between second transmission period.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts a preferred embodiment, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Fig. 1 illustrates the sequential chart that reads sequence signal of conventional serial formula flash memory.
Fig. 2 illustrates the calcspar according to the accumulator system of the embodiment of the invention.
Fig. 3 illustrates the detailed block diagram of the storer 12 that is Fig. 2.
Fig. 4 illustrates the synoptic diagram of the memory array 24 that is storer 12.
Fig. 5 illustrates the transmission signals sequential chart of the pin circuit of storer 12.
Fig. 6 illustrates another transmission signals sequential chart of the pin circuit of storer 12.
Fig. 7 illustrates a transmission signals sequential chart again of the pin circuit of storer 12.
Fig. 8 illustrates a transmission signals sequential chart again of the pin circuit of storer 12.
[main element symbol description]
1: accumulator system
12: storer
14: the host side circuit
IF: interface
P_SI/SIO0, P_SO/SIO1, P_WP#/SIO2, P_HOLD#/SIP3: output input pin
P_CS#: chip select signal pin
P_SCLK: frequency signal pin
20: the address signal generator
The 22:X code translator
24: memory array
26: the storage page impact damper
The 28:Y code translator
30: sensing circuit
32: output buffer
38: data buffer
34: high voltage generation circuit
36: control circuit
Ma, Mb, Mc, Md: memory block
Embodiment
The accumulator system of present embodiment is to see through adjusted interface to carry out the transmission of address signal.
The accumulator system of present embodiment comprises storer and host side circuit.The host side circuit determines idle most significant bits (Most SignificantBit, MSB) crowd and the normal bit crowd of an address signal according to the memory span of storer.The host side circuit is exported this replacement position crowd to storer, and is exported this normal bit crowd between second transmission period to storer according to this idle MSB crowd in replacement position crowd's replacement address signal of this address signal between first transmission period.Wherein, this replaces the last position crowd of order of transmission among the corresponding normal bit crowd so far of position crowd.
Please with reference to Fig. 2, it illustrates the calcspar according to the accumulator system of the embodiment of the invention.Accumulator system 1 comprises storer 12 and host side circuit 14.Storer 12 for example is serial type flash memory (Serial Flash).Host side in order to the access instruction Cm that provides via interface IF and address signal S_ad to storer 12.
Please with reference to Fig. 3, it illustrates the detailed block diagram of the storer 12 that is Fig. 2.Storer 12 comprises pin circuit, address signal generator 20, X code translator 22, memory array 24, storage page impact damper (Page Buffer) 26, Y code translator 28, sensing circuit 30, output buffer 32, reaches data buffer 38.
Please with reference to Fig. 4, it illustrates the synoptic diagram of the memory array 24 that is storer 12.For instance, memory array 24 comprises 4 memory block Ma, Mb, Mc and Md, the memory capacity of each memory block Ma-Md be 32 megabits (Megabit, MB).In other words, the memory capacity of memory array 24 is 128MB.
For instance, memory array is a minimum access unit with a byte (Byte), and memory array 24 utilizes address signal S_ad to come the individual byte of 224 in the memory array 24 (128MB=224Bytes) is carried out addressing.Address signal S_ad comprise 24 position A0, A1 ..., A23, its meta A0 and A23 be respectively least significant bits (Least Significant Bit, LSB) and most significant bits (MostSignificant Bit, MSB).For instance, the numerical value of address signal S_ad (000000) 16--(3FFFFF) 16-corresponds to memory block Ma; Numerical value (400000) 16--(7FFFFF) 16-corresponds to memory block Mb; Numerical value (800000) 16--(BFFFFF) 16-corresponds to memory block Mc; Numerical value (C00000) 16--(FFFFFF) 16-corresponds to memory block Md.
In view of the above, as position A22 and A23 (promptly being two MSB of address signal S_ad) when corresponding to numerical value 00, address signal S_ad points to the memory block Ma in the memory array 24; When position A22 and A23 corresponded to numerical value 01, address signal S_ad pointed to the memory block Mb in the memory array 24; When position A22 and A23 corresponded to numerical value 10, address signal S_ad pointed to the memory block Mc in the memory array 24; When position A22 and A23 corresponded to numerical value 11, address signal S_ad pointed to the memory block Md in the memory array 24.
General serial type flash memory is applied in the application scenario of low memory capacity (Low Density) more, and for instance, memory block Mb-Md is an anergy, is activation and memory block Ma is only arranged.So, storer 12 is regarded as the serial type flash memory that memory capacity is 32MB.In this example, position A22 and A23 perseverance correspond to numerical value 00.
The pin circuit receives instruction Cm and address signal S_ad that host side circuit 14 provides in order to see through interface IF.The pin circuit for example comprises high voltage signal pin (not illustrating) and ground voltage signal pin (not illustrating), respectively in order to receiving circuit high voltage signal and circuit ground voltage signal.The pin circuit more for example comprises output input pin P_SI/SIO0, P_SO/SIO1, P_WP#/SIO2, P_HOLD#/SIP3, frequency signal pin P_SCLK and chip select signal pin P_CS#, and the operational order and the address signal that provide via interface IF reception host side circuit 14 come storer 12 is carried out accessing operation.
In an operational instances, operational order is a reading command, and this moment, the transmission signals sequential chart of pin circuit was as shown in Figure 5.Output input pin P_SI/SIO0 is that the pulse 0～7 in clock signal SCLK receives 8 reading order.Output input pin P_SI/SIO0, P_SO/SIO1, P_WP#/SIO2 and P_HOLD#/SIP3 receive position A23-A0 in order in time sequential pulse 8～13 then, and it is temporary among the data buffer 36a.
Then, n recurrence interval is to read buffering in order to conduct, and n is a natural number.For instance, n equals 6.Finish back (complete reception position A23-A0) the 13rd recurrence interval; Address signal generator 20 starts read operation according to the address signal S_ad among the data buffer 36a; Read the byte that reads that address signal S_ad points in the memory array 24 to drive X code translator 22, storage page impact damper 26, Y code translator 28 and sensing circuit 30, and general's data storing wherein is in output buffer 32.In this example, comprise 8 sense amplifiers (corresponding so far read byte 8 positions) in the sensing circuit 30, read 8 bit data that store in the byte by this of address signal S_ad addressing in order to sensing in two recurrence intervals.
After time sequential pulse 19 finishes, the reading of data that output buffer 32 is unit via output input pin P_SI/SIO0, P_SO/SIO1, P_WP#/SIO2 and many of P_HOLD#/SIP3 outputs with a byte.
In another operational instances, address signal generator 20 finishes back (receiving position A23-A4) in the 12nd recurrence interval and promptly starts read operation.In other words, this example starts read operation under the situation that does not receive the A3-A0 that puts in place, so, can correspond to the individual byte of 16 (24=16) according to 20 MSB of address signal S_ad.Address signal generator 20 drives X code translator 22, storage page impact damper 26 and sensing circuit 30 and reads the data that store in 16 corresponding in the memory array 24 bytes.Afterwards after reception puts A0-A3 in place, address signal generator 20 drives Y code translator 28 according to position A0-A3, and choosing the data of desiring to read in the byte in 16 from then on corresponding bytes, and the data storing that will read byte is in output buffer 32.
Compared to finishing the operational instances that the back starts read operation the 13rd recurrence interval; Aforementionedly finish the operational instances that the back starts read operation the 12nd recurrence interval and can do sth. in advance a recurrence interval (being advanced to the 12nd recurrence interval by the 13rd recurrence interval) starts read operation; So, can prolong the read operation time of storer 12 in fact.Yet the sensing circuit 30 that the aforementioned operational instances of a recurrence interval startup read operation ahead of time need be used to comprise the individual sensing amplifier in 128 (8 * 24) is realized.So, it is can be because of the sensing amplifier number that uses too high and use four groups of output input pins simultaneously to finish operational instances that the back starts read operation the 12nd recurrence interval, causes the too high problem of circuit noise of storer 12.
In another operational instances, operational order also is a reading command, and this moment, the transmission signals sequential chart of pin circuit was as shown in Figure 6.Different ground with example shown in Figure 5, host side circuit 14 determine idle MSB crowd and the normal bit crowd of address signal S_ad according to the memory span of storer 12.In an example, this idle MSB crowd is that corresponding numerical value perseverance is 00 position A22 and A23, and this normal bit crowd comprises an A0-A21.
Host side circuit 14 more according to this idle MSB crowd of replacement position crowd's replacement of address signal S_ad, is exported this replacement position crowd to storer 12, and is exported this normal bit crowd between second transmission period to storer 12 between first transmission period.For example correspond to the 8th recurrence interval between this first transmission period, for example correspond to 8-13 recurrence interval between this second transmission period.
This replaces the last position crowd of order of transmission among the corresponding normal bit crowd so far of position crowd.In other words, host side circuit 14 changes the last position crowd of order of transmission among the signal S_ad of transport address in former this idle MSB crowd's of transmission impulse duration.
For instance, this replaces position A2 and A3 that the position crowd comprises that output input pin P_WP#/SIO2 and P_NC/SIO3 received in the 13rd recurrence interval.In other words, in the 8th recurrence interval, host side circuit 14 provides an A2 and A3 to storer 12 respectively via output input pin P_WP#_SIO2 and P_NC/SIO3.So, for host side circuit 14, host side circuit 14 is accomplished the operation of transport address signal S_ad meta A2-A21 to storer 12 in fact after the 12nd impulse duration finishes.
From another angle, host side circuit 14 is transmission one a MSB crowd and a LSB crowd in 8-13 recurrence interval; This MSB crowd for example comprises the part among the original MSB crowd among the address signal S_ad.For instance, this original MSB crowd comprises an A23-A16, and this MSB crowd comprises an A2, A3 and A21-A16.This LSB crowd comprises an A15-A0.
Need to use the sensing circuit 30 of the individual sensing amplifier in 32 (8 * 22) to realize in the operational instances of an aforementioned recurrence interval startup read operation ahead of time.
Compared to the signal timing diagram of pin circuit such as Fig. 5 and after the 12nd recurrence interval finishes, promptly drive the operational instances of read operation, just be illustrated in the aforementioned operation instance of Fig. 6 can obtain 20 position A2-A21 among this normal bit crowd after the 12nd recurrence interval finishes information.In other words; Promptly drive read operation even if coexist after the 12nd recurrence interval end, the sensing amplifier quantity (being reduced to 32 sensing amplifiers) that the aforementioned operation instance that is illustrated in Fig. 6 can reduce the byte (being reduced to 4 bytes by 16 bytes) that need read in the read operation effectively and need to use by 128 sensing amplifiers.So, finish the operational instances of rear drive read operations compared to the signal timing diagram of pin circuit such as Fig. 5 and 12 recurrence intervals, the aforementioned operation instance that is illustrated in Fig. 6 has the advantage that can effectively reduce the sensing amplifier number and reduce circuit noise.
In the present embodiment, though be that example is done explanation with storer 12 for being set the situation with memory capacity 32MB only, right, the storer 12 of present embodiment is not limited thereto.In another example, storer 12 also can be set has other memory capacity.For instance, storer 12 also can be set and have memory capacity 64MB.In this example, the idle MSB crowd of this of address signal S_ad for example has an A23 accordingly, and in another example, the transmission signals sequential chart of pin circuit is as shown in Figure 7.
So; Drive in the situation of read operation in the 12nd recurrence interval in advance in desire; This example also can transmit through idle MSB crowd's (corresponding to an A23) and be transmitted in the replacement position of one in the 13rd recurrence interval group (corresponding to an A3) originally, to reduce byte number (being reduced to 8 bytes by 16 bytes) that need read in the read operation and the sensing amplifier number (being reduced to 64 sensing amplifiers by 128 sensing amplifiers) that needs use.
In other example, storer 12 also can be set has memory capacity 16MB.In this example, the idle MSB crowd of this of address signal S_ad for example has an A21-A23 accordingly, and in an example, the transmission signals sequential chart of pin circuit is as shown in Figure 8.So; Drive in the situation of read operation in the 12nd recurrence interval in advance in desire; This example also can transmit through idle MSB crowd's (corresponding to an A21-A23) and be transmitted in the replacement position of one in the 13rd recurrence interval group (corresponding to an A1-A3) originally, to reduce byte number (being reduced to 2 bytes by 16 bytes) that need read in the read operation and the sensing amplifier number (being reduced to 16 sensing amplifiers by 128 sensing amplifiers) that needs use.
The accumulator system of present embodiment is to utilize adjusted interface to carry out the transmission of address signal.The accumulator system of present embodiment more starts read operation when intactly not receiving the position of all address signals.So, compared to legacy memory, the accumulator system of present embodiment can prolong the accessing operation time of storer effectively.
In addition, the accumulator system of present embodiment more utilizes some idle MSB in the address signal to come in the signal of transport address among some LSB position partly according to the corresponding memory capacity of storer.So, compared to legacy memory, the sensing amplifier number that the accumulator system of present embodiment more can shorten the byte number that need read in the accessing operation effectively and need to use is to reduce the circuit noise of storer.
In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope defined.
Claims (9)
1. address signal transmission method; In order to transmit address signal to a storer; This address signal has an original highest significant position (Most Significant Bit, MSB) crowd and a least significant bit (LSB) (Lest Significant Bit, LSB) crowd; It is characterized in that this address signal transmission method comprises:
Transmit a highest significant position crowd, this highest significant position crowd comprises a part of this original highest significant position crowd and a part of this least significant bit (LSB) crowd; And
Transmit this least significant bit (LSB) crowd;
Wherein, this storer is at the not complete read operation that starts when receiving the position of all address signals.
2. address signal transmission method according to claim 1 is characterized in that, the step of transmitting this highest significant position crowd more comprises:
According to a memory span of this storer, determine this original highest significant position crowd's an idle highest significant position crowd;
According to this original highest significant position crowd's idle highest significant position crowd, determine this part least significant bit (LSB) crowd position; And
Replace the highest significant position crowd of to leave unused with this part least significant bit (LSB) crowd position, to obtain this highest significant position crowd.
3. address signal transmission method according to claim 1 is characterized in that, the step of transmitting this highest significant position crowd more comprises:
In a plurality of transmission channels are between a highest significant position crowd transmission period, transmit this highest significant position crowd in order.
4. address signal transmission method according to claim 3 is characterized in that, the step of transmitting this least significant bit (LSB) crowd comprises:
In these a plurality of transmission channels are between a least significant bit (LSB) crowd transmission period, transmit this least significant bit (LSB) crowd in order.
5. an accumulator system is characterized in that, comprising:
One storer; And
One host side circuit; Memory span according to this storer; (this host side circuit is according to the highest significant position crowd of should leaving unused in this address signal of replacement position crowd's replacement of this address signal for Most Significant Bit, MSB) crowd and a normal bit crowd for highest significant position to determine to leave unused one of an address signal; Should replace the position crowd to this storer with output between one first transmission period, and export this normal bit crowd between one second transmission period in to this storer;
Wherein, this replacement position crowd corresponds to the last position crowd of order of transmission among this normal bit crowd, and this storer is at the not complete read operation that starts when receiving the position of all address signals.
6. accumulator system according to claim 5 is characterized in that:
In between this second transmission period, this host side circuit is that (Least Significant Bit LSB) exports this normal bit crowd in order, and N is the natural number greater than 1 by highest significant position to least significant bit (LSB) between N sub-transmission period; And
Transmit between N transmission period during this replacement position crowd corresponds among this normal bit crowd between this N transmission period group.
7. accumulator system according to claim 5 is characterized in that, this storer comprises:
One address signal produces circuit, produces an access address signal according to this replacements position group and this normal bit crowd and comes this storer of access.
8. address signal transmission method, is characterized in that this address signal transmission method comprises in order to transmit address signal to a storer:
Determine idle highest significant position (Most Significant Bit, MSB) crowd and a normal bit crowd of this address signal according to a memory span of this storer;
Replacement position crowd with this address signal replaces the highest significant position crowd of should leaving unused in this address signal, and wherein this replacement position crowd corresponds to the last position crowd of order of transmission among this normal bit crowd;
Output should replace the position crowd to this storer between one first transmission period; And
This normal bit of output crowd is to this storer between one second transmission period;
Wherein, this storer is at the not complete read operation that starts when receiving the position of all address signals.
9. address signal transmission method according to claim 8 is characterized in that:
Step in this normal bit of transmission crowd to this storer more comprises:
In between the sub-transmission period of the N between this second transmission period by highest significant position (Most Significant Bit, MSB) (Least Significant Bit LSB) exports this normal bit crowd in order, and N is the natural number greater than 1 to least significant bit (LSB); And
Transmit between N transmission period during this replacement position crowd corresponds among this normal bit crowd between this N transmission period group.
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| CN103544991B (en) * | 2012-07-12 | 2016-06-22 | 华邦电子股份有限公司 | The method of flash memory device and operation thereof |
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| CN101162452A (en) * | 2006-10-13 | 2008-04-16 | 旺宏电子股份有限公司 | Multi-input/output serial peripheral interface and method for data transmission |
| CN101226456A (en) * | 2007-01-08 | 2008-07-23 | 旺宏电子股份有限公司 | Method and system for a serial peripheral interface |
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| CN101162452A (en) * | 2006-10-13 | 2008-04-16 | 旺宏电子股份有限公司 | Multi-input/output serial peripheral interface and method for data transmission |
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