CN101882199A - Bus type bar code decoding chip - Google Patents
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- CN101882199A CN101882199A CN 201010181904 CN201010181904A CN101882199A CN 101882199 A CN101882199 A CN 101882199A CN 201010181904 CN201010181904 CN 201010181904 CN 201010181904 A CN201010181904 A CN 201010181904A CN 101882199 A CN101882199 A CN 101882199A
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Abstract
The invention provides a bus type bar code decoding chip. The decoding chip comprises a data memory, a register block, a bar code decoding assembly line, a master control logic module and a bus interface, wherein the data memory is used for memorizing a bar code image; the register block comprises a command register and a data register; the command register is used for temporarily storing a command; the data register is used for temporarily storing the data; the bar code decoding assembly line is used for processing the bar code image; the master control logic module acquires a processing command from the command register and transmits the bar code image stored in the data memory to the bar code decoding assembly line for decoding according to the processing command; and the bus interface receives the command from an external bus and transmits the command to the command register. Through the arrangement, the bar code decoding chip can be connected with the bus of a normal microprocessor, so that the burden of research personnel is relieved and the bus type bar code decoding chip has the advantages of convenient use, high decoding speed, low cost and the function of processing various bar code images of different encoding types.
Description
[technical field]
The invention belongs to the barcode technology field, especially, relate to a kind of bus type bar code decoding chip.
[background technology]
Barcode technology is an emerging technology that integrates coding, printing, identification, data acquisition and processing (DAP) that grows up on computer technology and infotech basis.Barcode technology is because its identification is quick, accurate, reliable and low cost and other advantages, be widely used in fields such as commerce, taking care of books, storage, post and telecommunications, traffic and Industry Control, and certainly will in " Internet of Things " that rise gradually used, bring into play great function.
The bar code that is widely used at present comprises bar code and two-dimensional bar code.Bar code claims linear bar code again, is made up of a plurality of " bars " that are arranged in parallel and " sky " unit, and bar code information is expressed by bar and empty different in width and position.Bar code is not then expressed any information just in a direction (generally being horizontal direction) expressing information in vertical direction, so information capacity and space availability ratio are lower, and promptly can't discern after bar code is damaged.
Two-dimensional bar code is made up of the chequered with black and white particular geometric figure that distributes on two-dimensional directional according to certain rules, its can be on two-dimensional directional expressing information, so information capacity and space availability ratio are higher, and have certain verifying function.Two-dimensional bar code can be divided into stack two-dimensional bar code and matrix two-dimensional barcode.The stack two-dimensional bar code is that the bar code by the multirow cutting back piles up and forms, and representational stack two-dimensional bar code comprises PDF417, Code 49, Code 16K etc.Matrix two-dimensional barcode is made up of black, the white module that is distributed in by pre-defined rule in the matrix, and representational matrix two-dimensional barcode comprises Codeone, Aztec, Data Matrix, OR sign indicating number etc.
As a rule, the implementation of bar-code identification is, obtains bar code image by optical image sensor array, utilize processor that bar code image is carried out Flame Image Process, to obtain code word, the code word of being obtained is decoded the information that is implied to obtain in the bar code according to certain encoding law.
It generally is to utilize the mode of software decode to realize that existing bar code decoding is handled, and need write a series of software programs of realizing decoding algorithm in processor, and software program is reversed engineering easily and cracks; Because single processor can only be is simultaneously carried out decoding processing at a kind of barcode standard of particular type, so decoding speed is slower, can not handle the bar code of multiple Format Type; Moreover owing to realize that the software algorithm of bar code decoding is comparatively complicated, therefore generally speaking the processor that is adopted is high-end processor (as 32 bit processors), because high-end processor price is comparatively expensive, therefore causes cost to raise.
Generally speaking, if conventional equipment needs the integrating bar code decoding function, need to use manual routing's mode that barcode recognition equipment is linked to each other by various communication protocols with existing processor, as using I
2C (Inter-Integrated Circuit, internal integrated circuit) bus thus, can be researched and developed progress by very big floor mop slowly with barcode recognition equipment and processor interconnection, strengthens research staff's burden.
Therefore, above deficiency at the prior art existence, a kind of bar code decoding scheme that provides is provided badly, can realize bar code decoding chip is linked to each other with the bus of common microprocessor, thereby alleviate research staff's burden, have more easy to use, decoding speed is faster, cost is lower, and can handle the function of the bar code image of multiple different coding type.
[summary of the invention]
In order to overcome the slow and shortcomings such as type is single of decoding of cost increase, difficult wiring, decoding process easy crack, decoding speed that prior art exists, the invention provides a kind of bus type bar code decoding chip, to overcome the problems referred to above.
The invention provides a kind of bus type bar code decoding chip, comprising: data-carrier store is used to store bar code image; Registers group comprises command register and data register, and command register is used for temporary order, and data register is used for temporal data; Bar code decoding pipeline is used to handle bar code image; The master control logic module is obtained processing command from command register, according to processing command the bar code image of storing in the data-carrier store is transferred to bar code decoding pipeline and decodes; Bus interface is ordered to command register from the external bus reception.
According to a preferred embodiment of the present invention, bus interface further receives bar code image to data register from external bus, and the master control logic module transfers to data-carrier store with bar code image.
According to a preferred embodiment of the present invention, bus type bar code decoding chip further comprises config memory, config memory is electrically connected with registers group, the computing parameter and the data of tabling look-up when being used to store bar code decoding pipeline work, bar code decoding pipeline is obtained the computing parameter and the data of tabling look-up by master control logic module and registers group from config memory.
According to a preferred embodiment of the present invention, bus type bar code decoding chip further comprises config memory, and config memory is arranged on bar code decoding pipeline inside, the computing parameter and the data of tabling look-up when being used to store bar code decoding pipeline work.
According to a preferred embodiment of the present invention, bus type bar code decoding chip comprises a plurality of bar code decoding pipeline that realized by hardware logic, and a plurality of bar code decoding pipeline are carried out parallel processing to bar code image.
According to a preferred embodiment of the present invention, bus interface comprises that basic input and output pin, command latch enable pin, address latch enable pin, sheet select pin, write enable pin and read enable pin.
According to a preferred embodiment of the present invention, bus type bar code decoding chip further comprises the optical image sensor array that is used to obtain bar code image.
According to a preferred embodiment of the present invention, bus type bar code decoding chip further comprises the exposure control module, and the exposure control module is temporary to command register according to the duty generation processing command of optical image sensor array.
By above setting, disclosed bus type bar code decoding chip can be realized bar code decoding chip is linked to each other with the bus of common microprocessor, thereby alleviate research staff's burden, have more easy to use, decoding speed is faster, cost is lower, and can handle the function of the bar code image of multiple different coding type.
[description of drawings]
Fig. 1 is the circuit connection block diagram according to the bus type bar code decoding chip of first embodiment of the invention.
Fig. 2 is the circuit connection block diagram according to the bus type bar code decoding chip of second embodiment of the invention.
Fig. 3 is the circuit connection block diagram according to the bus type bar code decoding chip of third embodiment of the invention.
[embodiment]
Relevant feature of the present invention and technology contents please refer to following detailed description and accompanying drawing, and accompanying drawing only provides reference and explanation, is not to be used for the present invention is limited.
Fig. 1 is the circuit connection block diagram according to the bus type bar code decoding chip of first embodiment of the invention.As shown in Figure 1, this bus type bar code decoding chip comprises bus interface 109, registers group 103, master control logic module 101, bar code decoding pipeline 102, optical image sensor array 105, switch 107 and data-carrier store 104 is set.
In above-mentioned bus type bar code decoding chip, bar code decoding pipeline 102 comprises PDF417 bar code decoding pipeline, bar code decoded stream waterline and RSS (Reduced Space Symbology, dwindle space code) bar code decoding pipeline, dissimilar bar code decoding pipeline is used to handle the bar code image of different barcode standards, and it utilizes hardware logic to realize.
Optical image sensor array 105 can be known CCD (Charge Coupled Device, the Charge Coupled Device (CCD) imageing sensor) or CMOS (Complementary Metal OxideSemiconductor, complementary metal oxide semiconductor (CMOS)) optical image sensor array, be used to obtain bar code image, and the bar code image that is obtained is transferred in the data-carrier store 104.Data-carrier store 104 is used to store the bar code image that is obtained by optical image sensor array 105, and it specifically can utilize RAM (random access memory, random access memory) to realize.
Master control logic module 101 can trigger particular event according to particular command, can be by triggering switch 107 is set or obtains bus line command from bus interface 109 and choose required state of a control of being electrically connected with master control logic module 101, as obtaining bar code image, transmit it to bar code decoding pipeline 102 etc. from data-carrier store 104.Disclosed master control logic module 101 does not possess calculation function, but only triggers corresponding event according to certain condition, specifically can utilize known state machine to realize.
Be provided with registers group 103 between bus interface 109 and the master control logic module 101, registers group 103 comprises a series of self-defining registers, comprise status register, data register and command register etc., status register is used to show the duty of master control logic module 101, data register is used for temporal data, command register is used for temporary order, master control logic module 101 can be from the data register reading of data, from the order register read command, and make specific action according to particular command, wherein also can be to command register from bus interface 109 input commands (being bus line command).Registers group 103 is isolated bar code decoding pipeline 102 and external circuit with master control logic module 101, after can making things convenient for bar code decoding pipeline 102 is upgraded (as increasing the bar code decoding pipeline of handling the extended formatting type) more.
After optical image sensor array 105 obtains bar code image, this bar code image can store in the data-carrier store 104, master control logic module 101 receives in command register behind the processing command and bar code image can be transferred to the bar code decoding pipeline 102 from data-carrier store 104, carries out image pre-service, gray scale extraction, binaryzation, code word by 102 pairs of these bar code images of bar code decoding pipeline and reads, deciphers a series of bar code decoding such as processing and handle operation.
In addition, bar code image also can input in the data register of registers group 103 by bus interface 109, master control logic module 102 can be obtained bar code image from data register, and it is saved to data-carrier store 104, when master control logic module 102 when the command register of registers group 103 reads processing command, outside bar code image in the data-carrier store 104 can be transferred to bar code decoding pipeline 102 and handle, bar code decoding pipeline 102 can be carried out the image pre-service to this outside bar code image, gray scale is extracted, binaryzation, code word reads, a series of bar code decodings such as decoding processing are handled operation.
It should be noted that because bar code decoding pipeline 102 comprises multiple bar code decoding pipeline at different barcode types such as PDF417 bar code decoding pipeline, bar code decoded stream waterline and RSS bar code decoding pipeline.Therefore, after obtaining bar code image, for example be bar code, this bar code image can transfer to simultaneously in above three kinds of bar code decoding pipeline and carry out parallel processing so, and is exported the correct bar code information of this bar code image by the bar code decoded stream waterline compatible with its form.A kind of bar code decoding pipeline of or other multiple forms also can be set certainly, as required.
Because incompatible with the bar code picture format, PDF417 bar code decoding pipeline and RSS bar code decoding pipeline can't be carried out respective handling after receiving this bar code image, and can't export correct bar code information.Similarly, bar code decoding pipeline 102 also can be carried out above-mentioned processing to PDF417 bar code image, RSS bar code image.Certainly, master control logic module 102 also can be handled the input bar code image according to the bar code streamline that user's selection is only controlled in a plurality of bar code streamlines.
In addition, if successively obtain three bar code image A from optical image sensor array 105 or bus interface 109, B, C is to data-carrier store 104, three bar code image A, B, respectively corresponding three kinds of dissimilar barcode standards of C: PDF417 bar code, RSS bar code and bar code, these three bar code images can provide to bar code decoding pipeline 102 from data-carrier store 104 by the precedence of obtaining so, under the same time, the PDF417 bar code decoding pipeline, bar code decoded stream waterline and RSS bar code decoding pipeline be parallel processing bar code image A at first, the result is: the PDF417 bar code decoding pipeline can handle accordingly to bar code image A, and export correct bar code information, other two bar code decoding pipeline then can't be handled bar code image A.If in the processing procedure of PDF417 bar code decoding pipeline to bar code image A, bar code decoded stream waterline and RSS bar code decoding pipeline have been confirmed to handle A, then can attempt handling next bar code image B, wherein the RSS bar code decoding pipeline can be handled bar code image B, and exports correct bar code information.If in the process that PDF417 bar code decoding pipeline and RSS bar code decoding pipeline are handled bar code image A, B respectively, bar code decoded stream waterline has been confirmed to handle bar code image B, then can continue to attempt next bar code image C is handled, and because form correspondence, bar code decoded stream waterline can be handled C, and exports correct bar code information.
Just can handle second bar code image owing to waiting for that first bar code image finished dealing with, and need not wait for that second bar code image finished dealing with and just can handle the 3rd bar code and open image that therefore above parallel bar code image processing mode can greatly improve the speed of handling dissimilar bar code images.
The bar code information of bar code decoding pipeline 102 outputs can be stored to data-carrier store 104 by master control logic module 101, and is stored to data register from data-carrier store 104 again when needs are exported.Certainly, the bar code information of bar code decoding pipeline 102 outputs can directly be stored to data register by master control logic module 101.The bar code information that is stored to data register can transfer to the bus of common microprocessor through bus interface 109.
Working method that it should be noted that above bar code decoding pipeline 102 is applicable to arbitrary embodiment of the present invention.
In a preferred embodiment, bus interface 109 bus interface 309 that disclosed among Fig. 1 comprise following pin: I/O0-I/O7, CLE, ALE, CS, WE, RE, wherein each functions of pins such as following table 1.1 introduction:
Table 1.1
| Pin name | Pin function |
| I/O 0～I/O 7 | I/O 0～I/O 7/ basic input and output I/O 0～I/O 7Pin is used for input command (command), address (address), data (data), and when read operation (read) output data. |
| CLE | COMMAND LATCH ENABLE/ command latch enable |
| When CLE activated, the input data were order | |
| ALE | When ADDRESS LATCH ENABLE/ address latch enabled the ALE activation, the input data were the address. |
| Pin name | Pin function |
| CS | The choosing of CHIP SELECT/ sheet is worked as this input end in significant level, and chip just enters duty, realizes the input and output of data. |
| WE | WRITE ENABLE/ writes and enables WE the input of I/O end is controlled, and WE activates, and allows input, and order, address, data latching are at the rising edge or the negative edge of WE pulse. |
| RE | READ ENABLE/ reads to enable RE the input of I/O end is controlled, and WE activates, and allows to export to I/O. |
Generally speaking, when pin ALE was effective, bus interface 109 was from pin I/O
0～I/O
7Receive address date, when pin CLE was effective, bus interface 109 was from pin I/O
0～I/O
7Receive order, and will order and keep in to the command register of registers group 303, when the WE pin was effective, outside bar code image can be from the pin I/O of bus interface 109
0-I/O
7The data register of input register group 303, master control logic module 101 can be obtained outside bar code image from the data register of registers group 303 according to mentioned order, and transfers to data-carrier store 304.In addition, when master control logic module 101 when the command register of registers group 103 reads processing command, the bar code image in the data-carrier store 104 can be transferred to bar code decoding pipeline 302 and carry out decoding processing.
By above setting, disclosed bus type bar code decoding chip can be realized bar code decoding chip is linked to each other with the bus of common microprocessor, thereby alleviate research staff's burden, have more easy to use, decoding speed is faster, cost is lower, and can handle the function of the bar code image of multiple different coding type.
Fig. 2 is the circuit connection block diagram according to the bar code decoding system of second embodiment of the invention.Itself and embodiment shown in Figure 1 are basic identical, comprise bus interface 211, registers group 203, master control logic module 201, bar code decoding pipeline 202, second data-carrier store 204 and optical image sensor array 205 equally.Improvement is, has adopted exposure control module 208 among the embodiment of Fig. 2, and exposure control module 208 is passed through I
2The duty of the total line traffic control optical image sensor array 205 of C (Inter-Integrated Circuit, internal integrated circuit).
In addition, exposure control module 208 can be placed processing command in the command register of registers group 203 according to the duty of optical image sensor array 205, master control logic module 201 is obtained processing command from the command register of registers group 203 after, 202 pairs of optical image sensor array 205 bar code images that obtain of control bar code decoding pipeline are decoded.
In addition, exposure control module 208 can be obtained bus line command by bus interface 211, and it is stored in the command register of registers group 203, and exposure control module 208 can be obtained this bus line command, thus the duty of control optical image sensor array 205.
Fig. 2 further shows scanning switch 206, can send scan command to master control logic module 201 by starting scanning switch 206, master control logic module 201 is temporary to command register with scan command, and control exposure control module 208 startup optical image sensor arrays 205 are taken thus.
The resolution of optical image sensor array 205 can be selected 752X 480 or 640X 480 (the present invention does not limit this) for use, it can or be provided with switch 207 by bus line command and select different resolution, for example, by being set, switch 207 transmissions order is set to master control logic module 101, it is temporary to command register that master control logic module 201 will be provided with order, and exposure control module 208 is obtained and order is set so that the resolution of optical image sensor array 205 to be set.It should be noted that, switch 207 is set except the triggering master control logic module 201 described in having first embodiment with bar code image from data-carrier store 204 is transferred to the effect of bar code decoding pipeline 202, also have the function of the resolution that optical image sensor array 205 is set.
Switch 207 is set and scanning switch 206 can be provided with according to actual needs, can omits in case of necessity.
In addition, config memory 212 is electrically connected with registers group 203, the computing parameter when being used to store bar code decoding pipeline 202 work and the data of tabling look-up (as the required code table of decoding computing), bar code decoding pipeline 202 can be obtained above data from config memory 212 by master control logic module 201 and registers group 203, it must guarantee can obliterated data under the situation of outage, available known EEPROM (Electrically Erasable Programmable Read-Only Memory, EEPROM (Electrically Erasable Programmable Read Only Memo)) realizes, in some cases, config memory 212 can be set directly in the bar code decoding pipeline 202.
It should be noted that config memory 212 can be arranged among arbitrary embodiment of the present invention.
Fig. 3 is the circuit connection block diagram according to the bus type bar code decoding chip of third embodiment of the invention.The difference of the present embodiment and first embodiment shown in Figure 1 is, the optical sensing array is not set in the bus type bar code decoding chip of present embodiment.Bar code image is imported from the outside by bus interface.
Above with reference to description of drawings various preferred embodiments of the present invention, but only otherwise deviate from the spirit and scope of the invention, those skilled in the art can carry out modifications and changes on the various forms to it, all belongs to protection scope of the present invention.
Claims (8)
1. a bus type bar code decoding chip is characterized in that, comprising:
Data-carrier store is used to store bar code image;
Registers group comprises command register and data register, and described command register is used for temporary order, and described data register is used for temporal data;
Bar code decoding pipeline is used to handle described bar code image;
The master control logic module is obtained processing command from described command register, according to described processing command the described bar code image of storing in the described data-carrier store is transferred to described bar code decoding pipeline and decodes;
Bus interface receives described order to described command register from external bus.
2. bus type bar code decoding chip according to claim 1, it is characterized in that, described bus interface further receives described bar code image to described data register from described external bus, and described master control logic module transfers to described data-carrier store with described bar code image.
3. bus type bar code decoding chip according to claim 1, it is characterized in that, described bus type bar code decoding chip further comprises config memory, described config memory is electrically connected with described registers group, the computing parameter and the data of tabling look-up when being used to store described bar code decoding pipeline work, described bar code decoding pipeline is obtained described computing parameter and the described data of tabling look-up by described master control logic module and described registers group from described config memory.
4. bus type bar code decoding chip according to claim 1, it is characterized in that, described bus type bar code decoding chip further comprises config memory, described config memory is arranged on described bar code decoding pipeline inside, the computing parameter and the data of tabling look-up when being used to store described bar code decoding pipeline work.
5. bus type bar code decoding chip according to claim 1, it is characterized in that, described bus type bar code decoding chip comprises a plurality of described bar code decoding pipeline that is realized by hardware logic, and described a plurality of bar code decoding pipeline are carried out parallel processing to described bar code image.
6. bus type bar code decoding chip according to claim 1 is characterized in that, described bus interface comprises that basic input and output pin, command latch enable pin, address latch enable pin, sheet select pin, write enable pin and read enable pin.
7. bus type bar code decoding chip according to claim 1 is characterized in that described bus type bar code decoding chip further comprises the optical image sensor array that is used to obtain described bar code image.
8. bus type bar code decoding chip according to claim 1, it is characterized in that, described bus type bar code decoding chip further comprises the exposure control module, and described exposure control module produces in the temporary extremely described command register of described processing command according to the duty of described optical image sensor array.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103576838A (en) * | 2012-07-23 | 2014-02-12 | 信泰光学(深圳)有限公司 | Electronic device configuration setting management system and method |
| CN113988104A (en) * | 2021-12-27 | 2022-01-28 | 北京紫光青藤微系统有限公司 | Method and device for decoding bar code, scanning equipment and storage medium |
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| JP2005020727A (en) * | 2003-06-05 | 2005-01-20 | Ntt Docomo Inc | Method and apparatus for reading and decoding information embedded in two-dimensional bar code |
| US20070263109A1 (en) * | 2001-04-30 | 2007-11-15 | Carlson Bradley S | Imager integrated CMOS circuit chip and associated optical code reading systems |
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| JPH0256080A (en) * | 1988-08-22 | 1990-02-26 | Fuji Electric Co Ltd | Bar code reader |
| US20070263109A1 (en) * | 2001-04-30 | 2007-11-15 | Carlson Bradley S | Imager integrated CMOS circuit chip and associated optical code reading systems |
| US20030009608A1 (en) * | 2001-07-06 | 2003-01-09 | Bong-Chae Moon | Field bus interface board |
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| CN103576838A (en) * | 2012-07-23 | 2014-02-12 | 信泰光学(深圳)有限公司 | Electronic device configuration setting management system and method |
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| CN101882199B (en) | 2012-11-07 |
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