CN101882098B - Microprocessor integrated circuit and correlation debug method - Google Patents
Microprocessor integrated circuit and correlation debug method Download PDFInfo
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Abstract
The present invention provides a microprocessor integrate circuit, including a first processor and a second processor, an internal memory and a bus interface unit. The internal memory is accessed by the first processor and the second processor, and the bus interface unit is connected with an external bus outside the microprocessor to access an external memory outside the microprocessor. The bus interface unit, the external bus and the external memory may be accessed by the second processor and is not accessed by the first processor. The first processor writes the debug information into the internal memory. The first processor is used to detect an event and provide an event notification corresponding to the event to the second processor. The second processor is coupled to the bus interface unit and used to execute a microcode routine according to the event notification received from the first processor. The microcode routine reads the debug information from the internal memory and writes to the external memory through the bus interface unit and the external bus so as to debug the second processor.
Description
Technical field
The invention relates to the debug and the usefulness adjustment of microprocessor, particularly relevant for the debug and the usefulness adjustment of service processor.
Background technology
Processor comprises one group of microcode routine (microcode routine), and this group microcode routine can be in dormant state, (for example: the WRMSR instruction) start it writes instruction up to the software to the control working storage.This group microcode routine is called " tracing routine " (Tracer) at this, can be used as the instrument that processor is carried out debug (debug) and usefulness adjustment (tune).In case be activated; Tracing routine can be triggered by variety of event; Make its collecting and treating apparatus status information, and processor state information is write to the assigned address in the storer, the logic analyzer that processor state information can monitored ppu bus is obtained.Status information can comprise the working storage collection; Translation lookaside buffer (Translation-Lookaside Buffer, TLB); High-speed cache, for example data cache, branch's destination address high-speed cache, level 2 (level-2) high-speed cache; The private of processor (private) random-access memory (ram) or the like (please be common with reference to the United States Patent (USP) word the 12/034th that applies on February 20th, 2008; No. 503 application cases (CNTR.2349); And the right of priority case applies for all the elements in the 60/910th, No. 982 provisional application case of United States Patent (USP) word on April 10th, 2007).Status information and relevant out of Memory thereof are (for example: temporal information) be referred to as log-on message (log information) or abbreviate login as at this.These incidents also can trigger tracing routine and go to carry out other action; For example remove various states (for example: write back (write-back) invalid get, remove TLB, LRU array, branch prediction information soon); Or cause processor is to private system management mode (system management mode that tracing routine disposed; Hereinafter to be referred as SMM) address makes system management interrupt (system management interrupt is hereinafter to be referred as SMI).The example of this type of incident comprises: the execution of specific instruction (RDTSC (read time stamp counter for example; Time for reading marking counting), RDPMC (read performance monitoring counter; Read performance monitoring counting), XSTORE (storage random number), MOV to CR (moving), WRMSR (write tomode specific register to the control working storage; The specific working storage of the pattern that writes), RDMSR (read to modespecific register; The specific working storage of read mode), software interruption, SYSTENTER (systemcall enter gets into system calling)/SYSEXIT (system call exit leaves system calling)/SYSCALL (system call; System calling)/SYSRET (system return; System returns), CPUID (CPU identification, central processing unit identification), RSM (resume operation ofinterrupt program recovers interrupt routine), MWAIT (monitor wait; The monitoring wait), MONITOR (monitoring), VMLAUNCH (virtual machine launch; The virtual machine startup), VMRESUME (virtual machine resume, virtual machine recovers), IRET (instructionreturn, instruction is returned), IN (input), OUT (output) instruction); X86 exceptional cast (exception); SMI, INTR (interrupt interrupts), NMI (non-maskable interrupt, not maskable interrupts), STPCLK (stop clock stops clock), A20 interrupt; VM leaves condition; Hardware check; And read/write APIC working storage (advanced programmable interrupt controller, but advance the rank program interrupt controller).
Tracing routine is the very powerful instrument of kind of function, yet it has two main restrictions.At first, tracing routine is the micro-code instruction that is embodied as in the processor.Therefore, through carrying out tracing routine, the state-transition that the state of processor will not be activated and trigger from tracing routine is to another state.That is to say that tracing routine may destroy and just carry out the normal processor state that the program in debug or the adjustment is set up at present, therefore reduces the useful degree of tracing routine.For instance, but the tracing routine debug also possibly influence the usefulness of processor.Secondly, because tracing routine is one group of microcode routine, tracing routine only can be when processor be carried out the instruction that realizes with microcode, or when hardware interrupts cause processor execution microcode routine, carries out.Yet when some incident that debug or adjustment are had importance possibly betide the execution of instruction asynchronously, that is in the middle of instruction was carried out, the some of them instruction possibly need to carry out many clock period, and tracing routine can't be carried out during this period.For instance, processor voltage or bus clock ratio possibly change at any time, and no matter which kind of instruction processor is carrying out, and possibly take place at the point of any time in instruction or the instruction group implementation.
Summary of the invention
The embodiment of the invention provides a kind of microprocessor integrated circuit, comprises first processor in order to detecting an incident, and event notice and debugging information corresponding to incident are provided; Second processor is in order to receiving above-mentioned event notice, and carries out the microcode routine according to above-mentioned event notice; And internal storage is in order to storing above-mentioned debugging information, and can be by first processor and the access of second processor institute.Wherein first processor is more in order to writing to internal storage with debugging information, and the microcode routine can be in order to reading debugging information from internal storage, and debugging information is write to an external memory storage, so that second processor is carried out debug.
Another embodiment of the present invention provides a kind of debug method, in order to a microprocessor integrated circuit is carried out debug.Wherein, microprocessor integrated circuit comprises first processor, second processor and an internal storage, and internal storage can be by first processor and the access of second processor institute.The method of present embodiment comprises first processor debugging information is write to internal storage.Method also comprises event notice to the second processor that first processor detects an incident and incident is provided.Method also comprises second processor according to carrying out the microcode routine from the received event notice of first processor.Method also comprises the microcode routine and reads debugging information by internal storage, and debugging information is write to external memory storage, so that second processor is carried out debug.Wherein, The step that debugging information is write to external memory storage comprises causes the Bus Interface Unit that is coupled to second processor that the debugging information on the bus is externally write to external memory storage, and wherein Bus Interface Unit, external bus and external memory storage can not be by the accesses of first processor institute.
The embodiment of the invention also provides a kind of debug method, in order to a microprocessor integrated circuit is carried out debug.Wherein, above-mentioned microprocessor integrated circuit comprises the first processor and second processor.Method comprises the following steps.At first, first processor detects second processor when surpassing a set number of clock and not retiring from office arbitrary instruction, second processor of resetting accordingly.Then, second processor is carried out a microcode routine corresponding to the action of resetting.Afterwards, the microcode routine reads is taken at the debugging information of microprocessor integrated circuit, and is when performed, accordingly debugging information to be exported to the outside of microprocessor integrated circuit by first processor in detecting the action of resetting.
For making above and other objects of the present invention, characteristic and the advantage can be more obviously understandable, the hereinafter spy enumerates preferred embodiment, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Fig. 1 is the calcspar of the microprocessor integrated circuit of one embodiment of the invention.
Fig. 2 is the operational flowchart of the microprocessor of one embodiment of the invention.
Fig. 3 is the operational flowchart of the microprocessor of another embodiment of the present invention.
Fig. 4 is the calcspar of the computer system of one embodiment of the invention.
Fig. 5 is the operational flowchart of microprocessor of the computer system of one embodiment of the invention.
[main element label declaration]
100～microprocessor integrated circuit; 102～Main Processor Unit;
110～instruction cache; 104～MSR;
106～SPROC controls working storage; 108～SPROC state working storage;
112～instruction transfer interpreter; 114～tracing routine;
116～working storage alias table; 118～reservation station;
122～performance element; 124～retirement unit;
126～Bus Interface Unit; 128～chipset;
132～SPROC procedure code; 134～service processor (SPROC);
136～SPROC RAM; 138～serial port interface (SPI);
142～bus; 144～microcode unit;
146～data cache; 148～processor bus signal condition;
156～replacement routine; 192～processor bus;
194～system storage; 196～non-user's addressable storage unit;
198～instruction cache;
202,204,206,208,212～execution in step;
302,304,306,308,312,314,316～execution in step;
501,502,504,506,508,512,514,516,518,522～execution in step.
Embodiment
Referring to Fig. 1, be the calcspar that shows the microprocessor integrated circuit 100 of one embodiment of the invention.Microprocessor integrated circuit 100 comprises a Main Processor Unit 102 and a service processor (serviceprocessor is hereinafter to be referred as SPROC) 134." Main Processor Unit " or " processor " or " microprocessor " speech can be considered the part of non-service processor 134 in the microprocessor integrated circuit 100 here.In an embodiment, Main Processor Unit 102 is x86 structure (being also referred to as an IA-32) processor 102.Yet Main Processor Unit 102 also can adopt other processor structure.If a processor can correctly be carried out the major applications program that is designed for the x86 processor, this processor promptly is an x86 structure treatment device.If the execution result that application program can obtain expecting can claim that then this application program is correctly carried out.Special, Main Processor Unit 102 can be carried out the instruction of x86 instruction set, and comprises visible (user-visible) the working storage collection of x86 user.
The asynchronous event that some tracing routines 114 can't be dealt carefully with may take place; Yet; The control that SPROC 134 can receive Main Processor Unit 102 detects these incidents, and carries out action (referring to being discussed at down, for example setting up a login voluntarily) according to detected incident.SPROC 134 itself can provide log-on message to the user, and also can to require tracing routine 114 log-on message be provided with tracing routine 114 interactions, or requires tracing routine 114 to carry out other action, referring to being discussed at down.SPROC 134 can detected incident comprise:
1. Main Processor Unit 102 is in suspend (hang).That is to say that Main Processor Unit 102 has had any instruction of not retiring from office of several clock period, the length in this clock cycle can be by 104 programmings of MSR.In an embodiment, Main Processor Unit 102 comprises a counter, and when each Main Processor Unit 102 resignations one are instructed, counter will load the value of MSR 104; Otherwise counter increases counting in each clock period.If counter generation overflow (overflow), the hardware of Main Processor Unit 102 will set SPROC state working storage 108 (being discussed at down) certain represent Main Processor Unit 102 incident that suspends.It is particularly useful to carry out which instruction when this suspends for judgement Main Processor Unit 102.
3. the temperature of Main Processor Unit 102 changes.In an embodiment, this temperature variation is indicated by a temperature inductor of microprocessor integrated circuit 100 inside.
4. operating system call changes the bus clock ratio of Main Processor Unit 102, changes the internal clocking frequency of Main Processor Unit 102 accordingly, and/or requires to change the voltage level of Main Processor Unit 102.In an embodiment, the microcode routine of the requirement of service operations system will be set position corresponding in the SPROC state working storage 108.
5. Main Processor Unit 102 spontaneous voltage level and/or the bus clock ratios of changing for example, are the purpose of realization power saving or enhancing efficiency.
6. a timer internal of Main Processor Unit 102 stops.
7. get soon spy on (snoop) hit one upgrade get row soon, cause this to get row soon and be written back to storer.A kind of method that is used for Main Processor Unit 102 is carried out debug is the relatively log-on message of tracing routine 114 and the execution result of a software functionality model emulation device (simulator), and this software functionality model emulation device is in order to emulation Main Processor Unit 102.For simulate an external event when taking place (for example: chipset produced one get soon spy on requirements) operation of Main Processor Unit 102 correspondences, software functionality model emulation device must be apprised of this outside incident.Therefore; Software functionality model emulation device helps SPROC 134/ tracing routine 114 to detect and login this incident; And when this incident occurs in the practical operation of Main Processor Unit 102; Because but its activation debugger (debugger) is spied on the time of origin that hits to software functionality model emulation device to provide to get soon, and then help debug.
8. when the temperature of Main Processor Unit 102, voltage or bus clock ratio exceed the scope that MSR 104 programmed.
9. the user sees an outer triggering signal off in an external pins (pin) of microprocessor integrated circuit 100.
Because SPROC 134 performed SPROC procedure codes 132 are to be independent of Main Processor Unit 102, it does not have the restriction identical with tracing routine 114.Therefore, SPROC 134 can detect or is independent of Main Processor Unit 102 instructions by notice and carry out the incident on border, and can not destroy the state of Main Processor Unit 102.
As shown in Figure 1; SPROC 134 has SPROC procedure code 132, the SPROC RAS of itself carrying out (being called for short RAM) 136; In order to store log-on message and serial port interface (serialbus interface thereof; Be called for short SPI) 138, can log-on message be sent to an external device (ED) through serial port interface 138.SPROC 134 also can indicate Main Processor Unit 102 performed tracing routines 114 that log-on message is stored to system storage from SPROC RAM 136, sees being discussed at down for details.
SPROC 134 can carry out communication with bus 142 with Main Processor Unit 102 through SPROC state working storage 108 and SPROC control working storage 106, but the order that wherein transmits or receive between bus 142 activation SPROC 134 and the Main Processor Unit 102.SPROC state working storage 108 comprise can detected each incident corresponding to aforementioned SPROC 134 a position.In order to notify SPROC the generation of 134 certain incident, Main Processor Unit 102 can be set in the SPROC state working storages 108 position corresponding to this incident.The corresponding position of some incident is that the hardware by Main Processor Unit 102 sets, and to be microcode unit 144 by Main Processor Unit 102 set in the corresponding position of some incident.SPROC 134 reads SPROC state working storage 108 and judges event inventory.SPROC control working storage 106 comprises the position corresponding to action, and this action is for detecting wherein a time of the specified incident of SPROC state working storage 108 as SPROC 134, the action that SPROC 134 should corresponding execution.That is to say that there is the set position in each the possibility incident in the SPROC state working storage 108 in the SPROC control working storage 106.In an embodiment, each incident can have 16 act bits.In an embodiment, when Main Processor Unit 102 writes SPROC state working storage 108 and representes an incident, will make SPROC 134 be interrupted, and correspondence read SPROC state working storage 108 and judge which kind of incident of generation.Can reduce the demand of SPROC 134 polls (pool) SPROC state working storage 108 by this, and then reach purpose of power saving.User's program that SPROC state working storage 108 and SPROC control working storage 106 also can be performed RDMSR and WRMSR instruction reads and writes.
SPROC 134 is when detecting an incident, and executable action comprises:
1. log-on message is write among the SPROC RAM 136.As far as each login write activity, most act bits is with having only the particular subset of log-on message to close and be written into so that program designer (programmer) specifies.
2. log-on message is write to SPI 138 from SPROC RAM 136.
3. write to SPROC control working storage 106 so that tracing routine 114 is set an incident.That is to say that SPROC 134 can interrupt Main Processor Unit 102, and cause tracing routine 114 to be initiated, to carry out the relevant action group of incident therewith.These actions are to specify (through the WRMSR instruction) in advance by the user.In an embodiment,, will cause Main Processor Unit 102 to carry out a hardware check exceptional cast, and whether hardware check exception controller can audit trail routine 114 start when SPROC 134 writes SPROC control working storage 106 when setting above-mentioned incident.If hardware check exception controller shifts control to tracing routine 114.Tracing routine 114 reads SPROC control working storage 106, if during the incident of the incident person of the being to use activation in tracing routine 114 that is set in the SPROC control working storage 106, tracing routine 114 can be carried out the user and specify the action relevant with these incidents in advance.The process flow diagram of Fig. 2 signal SPROC 134 causes tracing routine 114 in response to the ability of carrying out respective action when the SPROC 134 detected incidents.
For instance, SPROC 134 can set the log-on message that an incident causes tracing routine 114 will be stored among the SPROCRAM 136 and write to system storage.When the log-on message quantity that stores when desire is big (the log-on message quantity that desire stores can be programmed through MSR 104 by the user), these characteristics are particularly useful, and can cover slower SPI 138.
More particularly, but have a control bit activation SPROC 134 to set a special event for tracing routine 114 in the SPROC control working storage 106, this special event representes that SPROC RAM 136 has been filled.In response to this, tracing routine 114 reads the content of SPROC RAM 136, and with its writing system storer, the tracing routine 114 corresponding words of carrying out aforementioned activities if the user programmes.The use that SPROC RAM 136 fills up incident can promote the usefulness of tracing routine 114, referring to following example.Suppose program deviser wants to login all changes on the temperature; The program designer can write SPROC control working storage 106 and carry out following operation to cause SPROC 134: when (1) takes place in each temperature variation incident; It is logined to SPROC RAM 136; And (2) each temperature variation incident is when taking place, and the incident of setting makes tracing routine 114 that the content of SPROC RAM 136 is write to system storage.Yet, be inefficent like this.Otherwise; The program designer can write SPROC control working storage 106 and carry out following operation to cause SPROC 134: when (1) takes place in each temperature variation incident; It is logined to SPROC RAM 136; And (2) have only when SPROC RAM 136 is filled, and the incident of setting makes tracing routine 114 that the content of SPROC RAM 136 is write to system storage.This will cause the less interruption of Main Processor Unit 102; And the performed practical programs of Main Processor Unit 102 are produced less destruction; But can simultaneously the program designer be provided efficiently the information about temperature variation, and information is fully identical with the former more inefficient method.
4. write to SPROC control working storage 106 so that the microcode unit 144 of Main Processor Unit 102 is branched off into the specified microcode address of SPROC 134.This microcode unit 144 at Main Processor Unit 102 is in an infinite circulation; Make when tracing routine 114 can't be carried out any significant action particularly useful; Main Processor Unit 102 still can be carried out and during instruction retired, that is to say that the Main Processor Unit incident of suspending will can not take place.
5. write to SPROC control working storage 106 so that Main Processor Unit 102 is reset.As aforementioned, SPROC134 can detect Main Processor Unit 102 and be in and suspend, that is at least through several programmable clock period do not retire from office any instruction thereby replacement Main Processor Unit 102.Whether microcode unit 144 inspections of Main Processor Unit 102 reset initial by SPROC 134, if when initialization Main Processor Unit 102, before removing log-on message, earlier it is write to system storage.These characteristics are particularly useful, because if not like this, the status information of Main Processor Unit 102 can be erased (wipe out) by microcode unit 144 performed initialize routines.In addition, if Main Processor Unit 102 (that is, when not executing instruction) when suspending, the instruction of expression tracing routine 114 is not carried out, so can't store log-on message.Therefore, the replacement characteristic of SPROC 134 provides at Main Processor Unit and has been in the mode that still can obtain log-on message when suspending.In addition, SPROC 134 can read the working storage of Main Processor Unit 102 and judges the state of various bus signals in the Main Processor Unit 102, and judges whether bus signals changes.Bus signals information can be contained in the log-on message, and this information is useful especially to the suspend situation of incident of Main Processor Unit, and details are referring to the process flow diagram of Fig. 3.
6. continuous log-in events.Under this pattern; Interrupted by an incident of Main Processor Unit 102 with its wait; SPROC 134 spin (spin) in the circulation of an inspection SPROC state working storage 108; And log-on message and optionally writes to SPI 138 with log-on message simultaneously to the SPROC RAM 136 relevant with this incident constantly.These characteristics also can be used in combination with the characteristics of SPROC 134, make tracing routine 114 when SPROC RAM 136 fills up, log-on message write to system storage from SPROC RAM 136.
See also Fig. 2, the operational flowchart of the microprocessor integrated circuit 100 of its signal one embodiment of the invention.Flow process starts from step 202.
In step 202, the programme MSR 104 of Fig. 1 of user can trigger tracing routine 114 and the action group relevant with each incident to set.Follow execution in step 204.
In step 204, user's SPROC control working storage 106 of programming makes SPROC 134 carry out corresponding action according to detecting incident.For example SPROC RAM 136 all fills up the degree of a specific door (or be filled up to), and the SPROC that programmes control working storage 106 causes SPROC 134 to obtain set.Special, user's wherein action that lets SPROC control working storage 106 carry out able to programme is to set a tracing routine incident, as previously mentioned.Follow execution in step 206.
In step 206, SPROC 134 detects a wherein incident of programming in step 204.SPROC 134 writes to SPROC control working storage 106 accordingly, so that tracing routine 114 is set an incident.Thus, will on Main Processor Unit 102, produce a hardware check exceptional cast.Follow execution in step 208.
In step 208, in response in the hardware check exceptional cast that step 206 produced, Main Processor Unit 102 causes microcode unit 144, to judge that whether the hardware check exceptional cast is by 134 generations of SPROC.Microcode unit 144 and the corresponding tracing routine 114 that causes.Follow execution in step 212.
In step 212, whether the incident that tracing routine 114 inspection SPROC 134 set is not used person's activation.If the specified relevant action of setting with SPROC 134 of incident of user for example writes to log-on message the system storage from SPROC RAM 136 in 114 execution in step 202 of tracing routine.Flow process ends at step 212 afterwards.
Referring to Fig. 3, the operational flowchart of the microprocessor integrated circuit 100 of Fig. 1 of demonstration one embodiment of the invention.Flow process starts from step 302.
In step 302, SPROC 134 detects Main Processor Unit 102 and has suspended, that is as aforementioned Main Processor Unit 102 through any instruction of not retiring from office yet of the clock period of one section specific quantity.Flow process is followed execution in step 304.
In step 304, in step 302 if when detecting Main Processor Unit 102 and having suspended, SPROC 134 replacement Main Processor Units 102, as previously mentioned.Flow process is followed execution in step 306.
In step 306, corresponding to replacement action performed in the step 304, Main Processor Unit 102 begins to extract and carry out the replacement routine of microcode unit 144.Flow process is followed execution in step 308.
In step 308, the replacement routine of microcode unit 144 is judged the type of the replacement that is taken place.Flow process is then carried out determining step 312.
In step 312, (for example move) when judging the replacement type for normal the replacement by outside replacement pin (pin) or by the replacement that a boot-strap reset is produced as if the replacement routine of microcode unit 144, then flow process is followed execution in step 316; Otherwise, be a SPROC when resetting if the replacement routine of microcode unit 144 is judged the replacement type, for example performed replacement action in step 304, then flow process is followed execution in step 314.
In step 314, the replacement routine of microcode unit 144 writes to storer with log-on message.As previously mentioned; Log-on message can comprise the state of Main Processor Unit 102, the state of processor bus signal; And/or about the log-on message of Main Processor Unit 102 previous institutes event; These incidents comprise; For instance, the loading that processor suspends, can not get soon, temperature variation, stop, get temperature, voltage or the clock ratio that spying on of row hit, surpassed programmable range soon upgrading from the usefulness state variation that the usefulness state variation requires, the oneself is initial, the timer internal of operating system, and the transmission of outer triggering signal.Flow process is followed execution in step 316.
In step 316, the replacement routine of microcode unit 144 continues its function of initializing with initialization Main Processor Unit 102, makes Main Processor Unit 102 can begin the instruction of from storer, extracting and carrying out user's program.Flow process ends at step 316.
Seeing also Fig. 4, is the calcspar of a computer system 188 of signal one embodiment of the invention.Computer system 188 comprises microprocessor chip 100, or microprocessor integrated circuit 100, and it is coupled to system storage 194 through chipset 128, and wherein chipset 128 is coupled to microprocessor chip 100 through processor bus 192.In an embodiment, processor bus 192 is the x86 processor bus.
The microprocessor chip 100 here is similar to the microprocessor integrated circuit 100 of Fig. 1.Yet the embodiment of Fig. 4 shows the replacement routine 156 in the microcode ROM (read-only memory) (ROM) of microcode unit 144 clearly.The detailed description of the associative operation of tracing routine 114 and replacement routine 156 sees also the description of Fig. 5.In addition, the embodiment of Fig. 4 has shown the data cache 146 that is coupled to performance element 122 in the Main Processor Unit 102 clearly.Moreover Main Processor Unit 102 also comprises non-user's addressable storage unit 196, in order to store flag.According to one embodiment of the invention, non-user's addressable storage unit 196 can not removed by the replacement of the step 506 of Fig. 5 action, and this will be discussed at down.Person more so, non-user's addressable storage unit 196 can be removed by the action of the boot-strap reset of microprocessor chip 100, but not influenced by the non-boot-strap reset action institute of microprocessor chip 100.The action of non-boot-strap reset comprises, for instance, through one reset see off on the input pin signal to microprocessor chip 100 or through an oneself reset initial replacement action.At last, SPROC RAM 136 can store processor bus signal condition 148, sees the description of Fig. 2 for details.As aforementioned, spi bus 138 is the external bus of microprocessor chip 100, and SPROC 134 spi bus 138 capable of using transmit information, i.e. debugging information with microprocessor chip 100 outside external device (ED)s.More very important is that when debugging information can't be written into system storage 194, SPROC 134 spi bus 138 capable of using transmitted the external device (ED) that debugging information is given microprocessor chip 100 outsides.
Known like institute, there is the design mistake of numerous species can cause the processor bus 192 between microprocessor chip 100 and chipset 128 to suspend, make tracing routine 114 can't processor state be write to system storage 194.Yet, if can learn that the processor state when processor bus 192 suspends is still quite useful.Similarly, learn that at processor bus 192 Shi Ruoke that suspended the state of bus 192 will be extremely helpful also.
In order to reach aforementioned advantages; When SPROC 134 detects Main Processor Unit 102 conditions that suspend; And it possibly be when suspending bus 192 conditions, and SPROC 134 is stored to itself internal storage 136 and replacement Main Processor Unit 102 with the signal condition of processor bus 192.After Main Processor Unit 102 is reset completion; Its replacement routine 156 can write the state of Main Processor Unit 102 and the signal condition of bus 192 is stored to system storage 194 or spi bus 138 according to the programmable setting of a user, and details are referring to the explanation of Fig. 5.
Referring to Fig. 5, an embodiment of the operating process of the computer system 188 of demonstration Fig. 4 of the present invention.Flow process starts from step 501.
In step 501, the user specifies where Main Processor Unit state and processor bus state is write to, and promptly writes to spi bus 138 or to system storage 194.In an embodiment, the user can be through writing a certain the destination of coming designated state information to write of MSR 104.In addition, the user can specify the Main Processor Unit state that what need write.For instance, the user can specify the state of a minimum number, for example has only the working storage collection of Main Processor Unit 102, or the state of a maximum quantity, for example the state of all high-speed caches and working storage collection in the Main Processor Unit 102.Flow process is followed execution in step 502.
In step 502, SPROC 134 judges whether Main Processor Unit 102 suspends.Special, SPROC134 judges that Main Processor Unit 102 is whether above a set number of clock any instruction of not retiring from office.In an embodiment, SPROC 134 can whether overflow be judged through detecting a counter.This counter increases counting in each clock period of Main Processor Unit 102, and when each Main Processor Unit 102 resignations one are instructed, resets to less than its peaked set value.Main Processor Unit 102 can surpass a set number of clock any instruction of not retiring from office and have o lot of reasons.One of them reason is the design mistake of Main Processor Unit 102; Make Main Processor Unit 102 and chipset 128 be in the situation that processor bus 192 suspends; That is both are all waiting for that the other side carries out action on processor bus 192 Main Processor Unit 102 and chipset 128.Flow process is followed execution in step 504.
In step 504, when the situation that suspends of the processor bus that detects step 502 192, SPROC134 is stored to SPROC RAM 136 with processor bus signal condition 148.Or rather, SPROC 134 reads a working storage in the Bus Interface Unit (BIU) 126 with decision processor bus signals state 148.The BIU 126 because replacement Main Processor Unit 102 will be reset simultaneously, it possibly cause the loss of processor bus signal condition 148, and therefore, SPROC 134 stored processor bus signal condition 148 (in step 506) earlier before replacement Main Processor Unit 102.The processor bus signal condition 148 that is stored in SPROC RAM 136 can be waited a moment and is written into system storage 194 and/or spi bus 138 to be used for debug.Note that SPROC RAM 136 can not be by the access of user's program institute.That is to say to have only the routine of SPROC 134 and microcode unit 144 to carry out access to SPROC RAM 136.Therefore, can prevent that processor bus signal condition 148 person's of the being used programs in SPROC RAM 136 from overriding.Follow execution in step 506.
In step 506, SPROC 134 replacement Main Processor Units 102, and set the flag in non-user's addressable storage unit 196.It is noted that the replacement of Main Processor Unit 102 action not necessarily can return to the non-state that suspends with processor bus 192 in the step 506.Person very; The replacement of Main Processor Unit 102 can not cause the replacement of chipset 128; Chipset 128 still may be obscured by the state before the Main Processor Unit 102, thereby can not accept any data trade of Main Processor Unit 102 on processor bus 192.Therefore, replacement routine 156 optionally writes to spi bus 138 with the state and the processor bus signal condition 148 of Main Processor Unit 102, but not writes to system storage 194.Flow process is followed execution in step 508.
In step 508, because having reset in step 506, accomplishes Main Processor Unit 102, replacement routine 156 begins to carry out, with initialization Main Processor Unit 102.Flow process is followed execution in step 512.
In step 512, in the part of initialization sequence, the flag that replacement routine 156 detects non-user's addressable storage unit 196 is set.Flow process is followed execution in step 514.
In step 514; When the flag that in step 512, detects non-user's addressable storage unit 196 has been set; The MSR104 position that is write in the replacement routine 156 inspection steps 501 writes to state system storage 194 or writes to spi bus 138 with decision.If the MSR104 position is illustrated as system storage 194, flow process is followed execution in step 516; If the MSR104 position is illustrated as spi bus 138, then flow process is followed execution in step 518.
In step 516, replacement routine 156 writes to system storage 194 with the state of Main Processor Unit 102.In addition, replacement routine 156 writes to system storage 194 with processor bus signal condition 148 from SPROC RAM 136.In an embodiment, replacement routine 156 writes to the ad-hoc location in the system storage 194 with state, and this ad-hoc location is to be specified among the MSR 104 by the user.In addition, replacement routine 156 is also removed the flag of non-user's addressable storage unit 196.Flow process is followed execution in step 522.
In step 518, replacement routine 156 writes to spi bus 138 with the state of Main Processor Unit 102.In addition, replacement routine 156 will stored processor bus signal condition 148 write to spi bus 138 from SPROC RAM 136 in step 504.Its advantage is, obtains the another kind of mode of status information under the situation that can provide the debug personnel can't be written into system storage 194 at state.In addition, replacement routine 156 is also removed the flag of non-user's addressable storage unit 196.Flow process is followed execution in step 522.
In step 522, replacement routine 156 is accomplished the initialization of Main Processor Unit 102.It is noted that the value (as aforementioned) that writes MSR 104 in the step 501 can be able to keep because of the action (as aforementioned) through SPROC 134 replacement Main Processor Units 102 in the step 506.Special, replacement routine 156 can't be carried out initialization to MSR 104 before the operation of execution in step 512 to 518.Flow process ends at step 522.
What must remind is that though previous embodiment is based on the microprocessor of x86 structure, those skilled in the art should understand the microprocessor with different instruction structure set and also be applicable to the present invention.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Any those skilled in the art; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.For example, but the software activation, for example, function, manufacturing, modelling, emulation, description and/or test device of the present invention and method.Above-mentioned through using general procedure language (for example: C, C++), hardware description language (HDL) to comprise that Verilog HDL, VHDL or the like realize.This type of software can be placed in any known computer-usable medium with the kenel of procedure code, for example a tape, semiconductor, disk, floppy disk, hard disk or discs (for example: CD-ROM, DVD-ROM or the like), a network, wired line, wireless or other communication medium.Wherein, when procedure code by machine, like computer loads and when carrying out, this machine can become the device in order to embodiment of the present invention.Device of the present invention and method can be contained in semiconductor intelligence wealth core, a microcontroller core (being embedded in HDL) for example, and convert the hardware product of integrated circuit to.In addition, described device of the embodiment of the invention and method can comprise the physical embodiment of the combination with hardware and software.Therefore protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.Special, the present invention can be implemented in the micro processor, apparatus, and is used in the general purposes processor.At last, any those skilled in the art can not break away from the spirit and scope of the present invention based on notion and the specific embodiment that the present invention disclosed, and can do a little change and retouch to reach identical purpose of the present invention.
Claims (20)
1. microprocessor integrated circuit comprises:
One first processor in order to detecting an incident, and provides an event notice and debugging information corresponding to above-mentioned incident;
One second processor in order to receiving above-mentioned event notice, and is carried out a microcode routine according to above-mentioned event notice; And
One internal storage, in order to storing above-mentioned debugging information, and can be by above-mentioned first processor and the access of above-mentioned second processor institute;
Wherein above-mentioned first processor is also in order to write to above-mentioned internal storage with above-mentioned debugging information;
Wherein above-mentioned microcode routine is in order to reading above-mentioned debugging information from above-mentioned internal storage, and above-mentioned debugging information is write to an external memory storage, so that above-mentioned second processor is carried out debug.
2. microprocessor integrated circuit according to claim 1 also comprises:
One Bus Interface Unit; Connect the above-mentioned first processor and second processor to an external bus; In order to the access to the said external storer to be provided; Wherein above-mentioned Bus Interface Unit, said external bus and said external storer can be by the accesses of above-mentioned second processor institute, but can not be by the access of above-mentioned first processor institute.
3. microprocessor integrated circuit according to claim 1, the above-mentioned incident that wherein above-mentioned first processor detected comprises:
Above-mentioned internal storage is full of both above-mentioned debugging information of determined number at least; And
Above-mentioned second processor surpasses a given time arbitrary instruction of not retiring from office.
4. microprocessor integrated circuit according to claim 1, wherein above-mentioned internal storage can not be by the performed user's program access of above-mentioned second processor.
5. microprocessor integrated circuit according to claim 1, wherein above-mentioned incident can be through a performed program person of the being used programming of above-mentioned second processor.
6. microprocessor integrated circuit according to claim 1; Wherein above-mentioned first processor and above-mentioned second processor are structural asymmetric; Wherein above-mentioned second processor can be carried out user's program and above-mentioned microcode routine; Above-mentioned first processor only can be carried out the program that manufacturer developed of above-mentioned microprocessor integrated circuit, and can be interrupted by the above-mentioned incident of the instruction executing state that is independent of above-mentioned second processor.
7. microprocessor integrated circuit according to claim 1; Wherein above-mentioned microcode routine writes to above-mentioned debugging information an external bus that is coupled to above-mentioned first processor in order to selectivity; In order to above-mentioned second processor is carried out debug; Wherein said external bus and above-mentioned second processor are different structure, and the said external bus is different from a configuration bus of above-mentioned second processor.
8. microprocessor integrated circuit according to claim 1; Wherein above-mentioned first processor reads a state working storage to detect above-mentioned incident; And write one control working storage above-mentioned event notice is provided; Above-mentioned state working storage comprises corresponding to above-mentioned incident, and above-mentioned control working storage comprises the action group corresponding to above-mentioned incident, and above-mentioned microcode routine is carried out according to above-mentioned action group.
9. debug method; In order to a microprocessor integrated circuit is carried out debug; Wherein above-mentioned microprocessor integrated circuit comprises a first processor, one second processor and an internal storage; Above-mentioned internal storage can be by above-mentioned first processor and the access of above-mentioned second processor institute, and said method comprises the following steps:
Above-mentioned first processor writes to above-mentioned internal storage with debugging information;
Above-mentioned first processor detects an incident and an event notice to above-mentioned second processor of above-mentioned incident is provided;
Above-mentioned second processor is according to carrying out a microcode routine from the received above-mentioned event notice of above-mentioned first processor; And
Read above-mentioned debugging information and above-mentioned debugging information is write to an external memory storage from above-mentioned internal storage; So that above-mentioned second processor is carried out debug, wherein above-mentionedly read above-mentioned debugging information and the above-mentioned step that above-mentioned debugging information is write to the said external storer is performed by above-mentioned microcode routine from above-mentioned internal storage.
10. debug method according to claim 9; Wherein above-mentioned microprocessor integrated circuit is coupled to the said external storer through an external bus; The above-mentioned step that above-mentioned debugging information is write to the said external storer comprises causes the Bus Interface Unit that is coupled to above-mentioned second processor that the above-mentioned debugging information of said external bus is write to the said external storer, and wherein above-mentioned Bus Interface Unit, said external bus and said external storer can not be by the accesses of above-mentioned first processor institute.
11. it is one of following that debug method according to claim 9, the step that wherein above-mentioned first processor detects above-mentioned incident comprise:
Above-mentioned first processor detects above-mentioned internal storage and is full of both above-mentioned debugging information of determined number at least;
Above-mentioned first processor detects above-mentioned second processor and surpasses a given time arbitrary instruction of not retiring from office.
12. debug method according to claim 9, wherein above-mentioned internal storage can not be by user's program institute access of on above-mentioned second processor, carrying out.
13. debug method according to claim 9, wherein above-mentioned incident can be programmed through the program cause user that above-mentioned second processor is carried out.
14. debug method according to claim 9 also comprises:
Above-mentioned microcode routine optionally writes to an external bus that is coupled to above-mentioned first processor with above-mentioned debugging information; In order to above-mentioned second processor is carried out debug; Wherein said external bus and above-mentioned second processor are different structure, and the said external bus is different from a configuration bus of above-mentioned second processor.
15. a debug method, in order to a microprocessor integrated circuit is carried out debug, wherein above-mentioned microprocessor integrated circuit comprises a first processor and one second processor, and said method comprises the following steps:
When above-mentioned first processor is not retired from office an instruction in above-mentioned second processor of detection above a set number of clock, corresponding above-mentioned second processor of resetting;
Above-mentioned second processor is carried out a microcode routine corresponding to above-mentioned replacement action; And
Above-mentioned microcode routine reads the debugging information of above-mentioned microprocessor integrated circuit, and is when performed, above-mentioned debugging information to be exported to the outside of above-mentioned microprocessor integrated circuit by above-mentioned first processor corresponding to detecting above-mentioned replacement action.
16. debug method according to claim 15; The step that wherein above-mentioned microcode routine reads the above-mentioned debugging information of above-mentioned microprocessor integrated circuit is included in above-mentioned first processor and resets before above-mentioned second processor; Read above-mentioned debugging information from an internal storage, above-mentioned debugging information is that above-mentioned first processor is stored to above-mentioned internal storage.
17. debug method according to claim 15 also comprises:
Above-mentioned second processor of above-mentioned microcode routine initializes, wherein above-mentioned microcode routine was carried out the above-mentioned step that above-mentioned debugging information is exported to the outside of above-mentioned microprocessor integrated circuit before above-mentioned second processor of initialization.
18. debug method according to claim 15; The wherein above-mentioned step that exports above-mentioned debugging information the outside of above-mentioned microprocessor integrated circuit to comprises that above-mentioned microcode routine is according to a flag; Optionally export above-mentioned debugging information to one first external bus or one second external bus; Wherein above-mentioned first external bus is a configuration bus of above-mentioned second processor, and the said structure bus is coupled to an external memory storage, and wherein above-mentioned second external bus is coupled to above-mentioned first processor; With above-mentioned second processor be different structure, and be different from the said structure bus of above-mentioned second processor.
19. debug method according to claim 18, wherein above-mentioned flag is that the user is programmable.
20. debug method according to claim 15, wherein above-mentioned debugging information comprise with next person or combination:
The incident login of above-mentioned second processor before above-mentioned replacement action;
The configuration state of above-mentioned second processor before above-mentioned replacement action; And
The signal condition of one configuration bus of above-mentioned second processor before above-mentioned replacement action.
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| US61/297,513 | 2010-01-22 | ||
| US12/748,753 US8443175B2 (en) | 2009-07-10 | 2010-03-29 | Microprocessor with first processor for debugging second processor |
| US12/748,753 | 2010-03-29 | ||
| US12/748,846 US8464032B2 (en) | 2009-07-10 | 2010-03-29 | Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit |
| US12/748,846 | 2010-03-29 |
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| CN1495611A (en) * | 2002-07-12 | 2004-05-12 | �ձ�������ʽ���� | Fault-tderant computer system and its resynchronization method and program |
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