CN101877242A

CN101877242A - SRAM (Static Random Access Memory) compatible embedded DRAM (Dynamic Random Access Memory) device with hiding and updating capacity and double-port capacity

Info

Publication number: CN101877242A
Application number: CN2009101359398A
Authority: CN
Inventors: 王思闵
Original assignee: XUYAO SCIENCE AND TECHNOLOGY Co Ltd
Current assignee: XUYAO SCIENCE AND TECHNOLOGY Co Ltd; FocalTech Systems Co Ltd
Priority date: 2009-04-30
Filing date: 2009-04-30
Publication date: 2010-11-03
Anticipated expiration: 2029-04-30
Also published as: CN101877242B

Abstract

The invention provides an SRAM (Static Random Access Memory) compatible embedded DRAM (Dynamic Random Access Memory) device with hiding and updating capacity and double-port capacity, comprising an internal memory array, a first port access unit, a second port access unit and an access arbitrator, wherein the internal memory array comprises a plurality of double-port internal memory cell cases; the first port access unit is connected to the internal memory array to access the internal memory cell cases in the internal memory array; the second port access unit is connected to the internal memory array to access the internal memory cell cases in the internal memory array; and the access arbitrator is connected to the first port access unit and the second port access unit to arbitrate the access requirement of a first access port, the access requirement of a second access port and a hiding and updating requirement.

Description

Tool is hidden the compatible embedded DRAM device of SRAM of renewal and dual-port ability

Technical field

The present invention relates to the technical field of embedded memory, refer to the compatible embedded DRAM device of SRAM of hiding renewal of a kind of tool and dual-port ability especially.

Background technology

For system-on-a-chip (SoC) was used, it need be integrated into many mac function among one single IC for both.The block of normal use comprises the logical blocks of processor, controller, memory block and multiple difference in functionality, and all blocks are manufactured all on the same chip.This memory block can comprise volatility static random access memory SRAM, non-voltile memory and/or register basic internal memory (Register based memory, RBM).This is registered basic internal memory and in general uses when needs store in a small amount at a high speed, for example, in this system-on-a-chip by employed login file of one or more functional logic blocks and/or small form.

In general also need bigger volatility or non-voltile memory block in system-on-a-chip, for cost consideration, the deviser dwindles the configuration area of these memory blocks as much as possible.When if this memory block is a kind of volatile memory that must be updated, general a kind of six transistor static random access memories (6-T SRAM) cell element that uses of this memory block is made.

In order to save cost, a kind of method is formed so-called one-transistor static random access memory (1T SRAM) system for use a plurality of DRAM (Dynamic Random Access Memory) (DRAM) cell element adds static random access memory (SRAM) interface.This kind mode needs to automatically perform renewal DRAM (Dynamic Random Access Memory) (DRAM) cell element in this one-transistor static random access memory (1T SRAM) internal system, loses to prevent data stream.

U.S. US6 in 075, No. 740 patent case bulletin, use one-transistor static random access memory (1T SRAM) system with the saving cost, yet it is the memory system of single-port, causes the bottleneck of access easily.

Because in system-on-a-chip (SoC), many aggressive devices (master) meeting access embedded memory device is arranged, the memory system of single-port causes the access bottleneck easily.So disclose in US2008/0005492 number in early days in U.S. Patent application, as shown in Figure 1, add moderator (arbiter) 505, multiplexer 502, update controller 530 and interface circuit 510,520 to allow the memory array 501 of a port carry out work as the static random access memory (SRAM) of two ports.

Yet, disclosing in early days in US2008/0005492 number at U.S. Patent application, it uses the static random access memory (SRAM) of memory array 501 emulation two ports of a port.But along with the access sequential of system-on-a-chip (SoC) improves, this kind memory system can cause the access bottleneck of system-on-a-chip, and makes the sequential of system-on-a-chip (SoC) to promote effectively.Hence one can see that, and prior art still has many shortcomings and necessity of being improved is arranged.

Summary of the invention

The compatible embedded DRAM device of the SRAM that provides a kind of tool to hide renewal and dual-port ability mainly is provided purpose of the present invention, to solve the problem of DRAM device access efficiency in the prior art, solve the problem that the sequential of system-on-a-chip in the prior art (SoC) can't effectively promote simultaneously.

According to a characteristic of the present invention, the present invention proposes the compatible embedded DRAM device of SRAM that a kind of tool is hidden renewal and dual-port ability, and it comprises memory array, first port access unit, second port access unit and accessing arbitrator.This memory array comprises a plurality of dual port memories cell lattice.This first port access unit is connected to this memory array, with the internal memory cell lattice in this memory array of access.This second port access unit is connected to this memory array, with the internal memory cell lattice in this memory array of access.This accessing arbitrator is connected to this first port access unit and this second port access unit, to arbitrate the first access port access requirement, the second access port access requirement and to hide more new demand.

According to another characteristic of the present invention, the present invention proposes a kind of LCD system that makes the compatible embedded DRAM device of SRAM of hiding renewal of apparatus and dual-port ability, and it comprises the embedded DRAM device and the LCD interface of the SRAM compatibility of processor interface, the hiding renewal of tool and dual-port ability.The read-write of this processor interface receiving processor.The embedded DRAM device that this kind tool is hidden the SRAM compatibility of renewal and dual-port ability is connected to this processor interface, and this embedded DRAM device comprises memory array, first port access unit, second port access unit and accessing arbitrator.This memory array comprises a plurality of dual port memories cell lattice.This first port access unit is connected to this memory array, with the internal memory cell lattice in this memory array of access.This second port access unit is connected to this memory array, with the internal memory cell lattice in this memory array of access.This accessing arbitrator is connected to this first port access unit and this second port access unit, to arbitrate the first access port access requirement, the second access port access requirement and to hide more new demand.This LCD interface is connected to this embedded DRAM device, is used for presenting the data in this embedded DRAM device.

Description of drawings

Fig. 1 is the synoptic diagram of static random access memory of memory array emulation two ports of use one port of prior art.

Fig. 2 hides the calcspar of the compatible embedded DRAM device of SRAM of renewal and dual-port ability for tool of the present invention.

Fig. 3 is the calcspar of accessing arbitrator of the present invention.

Fig. 4 is the calcspar of port controlling of the present invention and address latch unit.

Fig. 5 is the calcspar of storage control unit of the present invention.

Fig. 6 is the calcspar of the present invention's first port access unit and this second port access unit.

The sequential chart of access data when Fig. 7 does not compete for the present invention.

The compatible embedded DRAM device of SRAM that Fig. 8 makes apparatus hide renewal and dual-port ability for the present invention applies to the synoptic diagram of LCD system.

Sequential chart when Fig. 9 is applied to the LCD system for the present invention.

The synoptic diagram of two stages arbitration when Figure 10 is applied to the LCD system for the present invention.

Two stages were arbitrated the synoptic diagram of another embodiment when Figure 11 was applied to the LCD system for the present invention.

The sequential chart of another embodiment when Figure 12 is applied to the LCD system for the present invention.

The primary clustering symbol description

Moderator 505 multiplexers 502

Update controller 530 interface circuits 510,520

Memory array 501

Compatible embedded DRAM device 200 memory array 210

First port access unit, 220 second port access unit 230

Accessing arbitrator 240 row decoding word set drives 250

Port controlling and address latch unit 310 storage control units 320

Port controlling unit 410 first order moderators 420

Data and address latch 430 upgrade timing unit 440

Address-generation unit 450

Second level moderator 550 first port controlling unit 560

The second port controlling unit, 570 row control modules 580

The first column decoding unit, 610 first line buffers 620

First sensing amplifier, 630 data latches 640

Secondary series decoding unit 650 second line buffers 660

Second sensing amplifier 670

Processor interface 810 LCD interfaces 820

Embodiment

Fig. 2 is the calcspar that a kind of tool of the present invention is hidden the compatible embedded DRAM device of SRAM of renewal and dual-port ability.Compatible embedded DRAM device 200 comprises memory array 210, first port access unit 220, second port access unit 230, accessing arbitrator 240 and row (row) decoding word set drive 250.

Memory array 210 comprises a plurality of dual port memories cell lattice, and wherein, these a plurality of dual port memories cell lattice are preferably by one-transistor DRAM (Dynamic Random Access Memory) (1T DRAM) to be formed.

First port access unit 220 is connected to memory array 210, with the internal memory cell lattice in the access memory array 210.Second port access unit 230 is connected to memory array 210, with the internal memory cell lattice in the access memory array 210.This first port access is the read/write access port, and this second port access is for only writing access port.

Accessing arbitrator 240 is connected to first port access unit 220 and second port access unit 230, in order to arbitrate the first access port access requirement, the second access port access requirement and to hide more new demand.

Row decoding word set drive 250 is connected to accessing arbitrator 240 and memory array 210, in order to produce a word group line address WL[479:0], and then this memory array of addressing.

Fig. 3 is the calcspar of accessing arbitrator 240 of the present invention.Accessing arbitrator 240 comprises port controlling and address latch unit (port control ﹠amp; Address latch) 310 and storage control unit (access control) 320.

Control signal and address (CLKA that port controlling and address latch unit 310 receive at the first port access, CENA#, WEN#, ADDRA[18:0], DINA[23:0]) and at the control signal and the address (CLKB of the second port access, CENB#, ADDRB[10:0]), and produce access requirement signal (REQEX), more new demand signal (REQREF), the first port status signal (STATEA) and the second port status signal (STATEB) respectively.Port controlling and address latch unit 310 also produce first internal address signal (EXAA[8:0]), second internal address signal (EXYA[9:0]), read-write mode signals (RWMode), input data signal (DATA[23:0]), and scheduler signal (REFXA[8:0]).

Storage control unit (access control) 320 is connected to port controlling and address latch unit 310, require signal (REQEX) with more new demand signal (REQREF), the first port status signal (STATEA) and the second port status signal (STATEB) according to access, and then produce the first port access control signal and the second port access control signal.

Fig. 4 is the calcspar of port controlling of the present invention and address latch unit 310.This port controlling and address latch unit 310 comprise port controlling unit (port control) 410, first order moderator 420, data and address latch (data and address latch) 430, upgrade timing unit (Refresh timer) 440 and address-generation unit (Address Generator) 450.

Port controlling unit (port control) 410 receives to the clock signal (CLKA) of first port access unit and enable signal (CENA#), to clock signal (CLKB) and the enable signal (CENB#) and the write signal (WEN#) of second port access unit, to produce the first port status signal (STATEA), the second port status signal (STATEB) and read-write mode signals (RWMode).Uncompleted access can be followed the trail of by the first port status signal (STATEA) and the second port status signal (STATEB) in port controlling unit (port control) 410.

First order moderator 420 is connected to port controlling unit 410, receive the first port status signal and the second port status signal, producing the first port requirement signal and the second port requirement signal, and require the signal and second port to require signal, produce access and require signal according to first port.Wherein, and first order moderator 420 uses service earlier first (First Come Fisrt Service, FCFS), to produce this first port requirement signal and this second port requirement signal.When first port required signal to be noble potential, representative can produce the control signal about the first port memory access 220; When second port required signal to be noble potential, representative can produce the control signal about the second port memory access 230, and wherein, the same time, this first port requires signal and this second port to require signal to have only a signal to can be noble potential at most.

This first port require signal and this second port require signal via or door 421 to produce this access requirement signal.

Data and address latch (data and address latch) 430 is connected to this first order moderator 420, require signal and this second port to require signal according to this first port, latch the first port address signal (ADDRA[18:0]), the first port address signal (ADDRB[10:0]) and first port and write data-signal (DINA[23:0]), and then produce first internal address signal (EXAA[8:0]), second internal address signal (EXYA[9:0]) and input data signal (DATA[23:0]).

Upgrade timing unit (Refresh timer) 440 and trigger clock signal (Trig_CLK) to produce according to Preset Time interval (interval).

Address-generation unit (Address Generator) 450 is connected to this renewal timing unit, produce more new demand signal (REQREF) and scheduler signal (REFXA[8:0]) according to triggering clock signal (Trig_CLK), wherein, more new demand signal (REQREF) is transferred into the cell lattice of storage control unit 320 with delegation (row) in the updating memory array 210.

Upgrade timing unit (Refresh timer) 440 and follow the trail of the charge retention time of the cell lattice in the memory array 210, and periodically produce this triggering clock signal, to drive the cell lattice of delegation in the address-generation unit 450 updating memory arrays 210.When address-generation unit 450 is received this triggering clock signal, scheduler signal (REFXA[8:0]) is added 1 and produce more new demand signal (REQREF), so the present invention carrying out when upgrading operation, need not the external signal and the address of newline (row) more.

Fig. 5 is the calcspar of storage control unit of the present invention (access control), and storage control unit 320 comprises second level moderator 550, the first port controlling unit (CTRLA) 560, the second port controlling unit (CTRLB) 570 and row control module (ROW_CTRL) 580.

Second level moderator 550 is connected to port controlling unit (port control) 410 and first order moderator 420, receive access and require signal (REQEX), more new demand signal (REQREF), the first port status signal (STATEA) and the second port status signal (STATEB), and use service earlier first to produce the first port enable signal (ACTA), the second port enable signal (ACTB) and upgrade enable signal (ACTREF).

The first port controlling unit (CTRLA) 560 is connected to port controlling unit (portcontrol) 410, data and address latch (data and address latch) 430 and second level moderator 550, according to read-write mode signals (RWMode), the first port enable signal (ACTA), upgrade enable signal (ACTREF) and second internal address signal (EXYA[9:0]), to produce read-write (R/W), the first sensing amplifier enable signal (SAENA) and first row (column) address signal (YAA[9:0]).

The second port controlling unit (CTRLB) 570 is connected to data and address latch 430 and second level moderator 550, according to the second port enable signal (ACTB) and second internal address signal (EXYA[9:0]), to produce the second sensing amplifier enable signal (SAENB) and secondary series address signal (YAB[1:0]).

Row control module (ROW_CTRL) 580 is connected to second level moderator 550 and data and address latch (data and address latch) 430, according to the first port enable signal, the second port enable signal, upgrade enable signal (ACTREF) and first internal address signal (EXAA[8:0]), can signal (EN_Trig) to produce line position signal (XA[8:0]) and to exercise.

When accessing arbitrator 240 receives by the first port requirement signal, the second port requirement signal, when more the memory access that transmits of new demand signal requires, second level moderator 550 can decision requires (REQEX) by external memory accesses or more new demand (REQREF) obtains higher right of priority.Because first order moderator 420 has determined the first port access requirement or the second port access requirement to have higher-priority earlier, so first port requires the signal (REQA) or second port to require signal (REQB) only to have one of them to be enabled, so second level moderator 550 still is two wires moderator (two-way arbiter), and only need consider that access requirement signal (REQEX) reaches more new demand signal (REQREF).So the same time, only have a signal to be triggered in the first port enable signal (ACTA), the second port enable signal (ACTB) and the renewal enable signal (ACTREF).

When wanting first port of access memory array 210, the first port enable signal (ACTA) can make the first port controlling unit (CTRLA) 560 transmit the first correct column address signal (YAA[9:0]) and the first sensing amplifier enable signal (SAENA) to this first port memory access 220, and make the first port controlling unit (CTRLA) 560 transmit read-writes (R/W), so that to indicate the first existing port operation be reading of data or write data.

When wanting second port of access memory array 210, the second port enable signal (ACTB) can make the second port controlling unit (CTRLB) 570 transmit correct secondary series address signal (YAB[1:0]) and the second sensing amplifier enable signal (SAENB) to the second port memory access 230.

If when carrying out memory refreshing, read and again write-back (read-and-write-back) can carry out via first port, therefore when the execution read operation, the read-write (R/W) and the first sensing amplifier enable signal (SAENA) can be enabled.At this moment, owing to need not output data to outside, thus this first column address signal (YAA[9:0]) can't be transmitted.

No matter be to want access first port, access second port or memory refreshing, and row control module (ROW_CTRL) 580 meeting output line position signals (XA[8:0]) and exercise energy signal (EN_Trig) to row decoding word set drive 250.Reset signal (RST) can be back to capable control module (ROW_CTRL) 580 and second level moderator 550 by memory array 210 simultaneously.Second level moderator 550 produces first reset signal (RSTA) and second reset signal (RSTB) respectively according to reset signal (RST), and is sent to storage control unit 320.

Fig. 6 is the calcspar of the present invention's first port access unit 220 and second port access unit 230.This first port access unit comprises first row (column) decoding unit 610, first line buffer 620, first sensing amplifier 630, data latches 640.

The first column decoding unit 610 is connected to these data and address latch (data and addresslatch) the 430 and first port controlling unit (CTRLA) 560, carry out column decoding according to first column address signal (YAA[9:0]), and accept input data signal (DATA[23:0]);

First line buffer 620 is connected to the first column decoding unit 610 and the first port controlling unit (CTRLA) 560, and (R/W) flows to determination data according to read-write.It can receive the data of being read by memory array 210 and transfer to the first column decoding unit 610, or receives the data that sent by the first column decoding unit 610, and via first sensing amplifier 630 write memory array 210.

First sensing amplifier 630 is connected to first line buffer 620, first port controlling unit (CTRLA) 560 and the memory array 210, receive the first sensing amplifier enable signal (SAENA), carry out amplification with the data that memory array 210 is read, and transfer to first line buffer 620.

Data latches 640 is connected to the first column decoding unit 610, receives the first column decoding unit, 610 output datas, and is sent to the outside.

The first column decoding unit 610 can be read and write by the position of selecting a pixel in first line buffer 620.

As shown in Figure 6, second port access unit 230 comprises secondary series decoding unit 650, second line buffer 660, reaches second sensing amplifier 670.

Secondary series decoding unit 650 is connected to the second port controlling unit (CTRLB) 570, carries out column decoding according to secondary series address signal (YAB[1:0]).Secondary series decoding unit 650 can be by selecting the part position to read in second line buffer 660.

Second line buffer 660 is connected to secondary series decoding unit 650, with output data to secondary series decoding unit 650.

Second sensing amplifier 670 is connected to second line buffer 660, second port controlling unit (CTRLB) 570 and the memory array 210, receive the second sensing amplifier enable signal (SAENB), carry out amplification with the data that memory array 210 is read, and transfer to second line buffer 660.

Because accessing arbitrator 240 has determined can via which port access memory array 210, so in the same time, have only a meeting to be enabled in first sensing amplifier 630 and second sensing amplifier 670.First sensing amplifier 630, second sensing amplifier 670, first line buffer 620 and second line buffer 660 are with behavior access unit.And the first column decoding unit 610 can be read and write by the position of selecting a pixel in first line buffer 620.Simultaneously, secondary series decoding unit 650 can be by selecting the part position to read in second line buffer 660.

250 decodings of row decoding word set drive produce word group line address WL[479:0], and when receiving row enable signal (EN_Trig), a word group line is drawn high (enabling).When read-write or upgrade finish after, memory array 210 produces reset signals (RST), so that this word group line is closed (forbidden energy).

The sequential chart of access data when Fig. 7 does not compete for the present invention.As shown in Figure 7, in time interval T1, for there not being the memory access of competition.It produces reading order, produces write command again first port of memory array 210 earlier, at last second port is produced reading order.When the first port status signal (STATEA) and the second port status signal (STATEB) were noble potential, expression was carried out access to first port and second port.As shown in Figure 7, the first port status signal (STATEA) and the second port status signal (STATEB) can't overlap for enabling (noble potential).When first reset signal (RSTA) is noble potential, the first port status signal (STATEA) is reset to electronegative potential.

In time interval T2, it is competitive memory access, and this competitive situations is to be solved by first order moderator 420.As shown in Figure 7, it is by driving the first port status signal (STATEA) and the second port status signal (STATEB) for noble potential, to represent approximately simultaneously first port and second port to be carried out access.420 decisions of first order moderator have right of priority to the access of first port, so first port of output noble potential requires signal (REQA).After finishing the first port access, when first reset signal (RSTA) is noble potential, the first port status signal (STATEA) is reset to electronegative potential.Afterwards, second port of output noble potential requires signal (REQB), to carry out the second port access.After finishing the second port access, when second reset signal (RSTB) is noble potential, the second port status signal (STATEB) is reset to electronegative potential.

In time interval T3, it is the memory access that competition is arranged and upgrade.In this example, the access of first port obtains the highest right of priority.After the access of first port finishes, the access right of memory array 210 is obtained by new demand signal (REQREF) more, it mainly is a bit of time after the access of first port finishes, second level moderator 550 is only seen more new demand signal (REQREF), and do not see access requirement signal (REQEX), so second level moderator 550 will be assigned to more new demand signal (REQREF) to the access right of memory array 210, and continue to allow more new demand signal (REQREF) wait for.

Three-way arbitration (3-way arbitration) is finished via being connected in series first order moderator 420 and second level moderator 550, first order moderator 420 and second level moderator 550 are two wires arbitration (2-way arbitration), and all use and serve (FCFS) arbitration mechanism first earlier, plant three-way arbitration by this, even more new demand signal (REQREF) is slightly later to the first port status signal (STATEA) and the second port status signal (STATEB), more new demand signal (REQREF) also can not be lowest priority.

The compatible embedded DRAM device of SRAM that Fig. 8 makes apparatus hide renewal and dual-port ability for the present invention applies to the synoptic diagram of LCD system.It comprises the embedded DRAM device 200 and the LCD interface 820 of the SRAM compatibility of processor interface 810, the hiding renewal of tool and dual-port ability.

The read-write of processor interface 810 receiving processors.The embedded DRAM device 200 that tool is hidden the SRAM compatibility of renewal and dual-port ability is connected to processor interface 810, and this embedded DRAM device 200 comprises memory array 210, first port access unit 220, second port access unit 230, accessing arbitrator 240 and row decoding word set drive 250.LCD interface 820 is connected to embedded DRAM device 200, in order to present the data in this embedded DRAM device, wherein, processor interface 810 is for being connected to first port of this embedded DRAM device 200, LCD interface 820 is for being connected to second port of embedded DRAM device 200, that is processor interface 810 can carry out read/write operation, and LCD interface 820 only carries out read operation.

When the LCD system applies, processor interface 810 frequencies of access far faster than the more new demand frequency of LCD interface 820 frequencies of access and memory array 210, are added the store access cycle (tREF) of more new demand so the store access cycle (tCYCA) of processor interface 810 minimums can not add the store access cycle (tB) of second port less than the store access cycle (tA) of first port.

Sequential chart when Fig. 9 is applied to the LCD system for the present invention.Shown in the sequential chart of Fig. 9 left side, when the store access cycle (tCYCA) of processor interface 810 minimums adds that greater than the store access cycle (tA) of first port store access cycle (tB) of second port is added the store access cycle (tREF) of more new demand, but this processor interface normal running.Shown in the sequential chart of Fig. 9 the right, when the store access cycle (tCYCA) of these processor interface 810 minimums adds that less than the store access cycle (tA) of first port store access cycle (tB) of second port is added the store access cycle (tREF) of more new demand, the accessing operation second time of processor interface 810 can be left in the basket, as shown in Figure 9, the operating frequency of processor interface 810 is limited.

The synoptic diagram of two stages arbitration when Figure 10 is applied to the LCD system for the present invention.As shown in figure 10, the access of first port and second port requires that (victor arbitrates with new demand signal (REQREF) more again for STATEA, STATEB) arbitration earlier.In this, this framework hint (imply) more new demand signal (REQREF) has higher right of priority.

Two stages were arbitrated the synoptic diagram of another embodiment when Figure 11 was applied to the LCD system for the present invention.As shown in figure 11, the access of second port requires (STATEB) and new demand signal (STATER) more to arbitrate earlier, and the victor requires (STATEA) to arbitrate with the access of first port again.The sequential chart of another embodiment when Figure 12 is applied to the LCD system for the present invention.As shown in Figure 12, the store access cycle (tCYCA) of processor interface 810 minimums can not add that this processor interface got final product normal running when the store access cycle (tCYCA) of the store access cycle (tB) of second port or this processor interface 810 minimums can not add the store access cycle (tREF) of more new demand less than the store access cycle (tA) of first port less than the store access cycle (tA) of first port.Can improve the operating frequency of processor interface 810 by this.

By above stated specification as can be known, existing embedded DRAM device is only considered the situation of single-port access, does not also consider the situation in the system-on-a-chip (SoC).And the present invention utilizes first order moderator 420 and second level moderator 550 to form three-way arbitration, can improve the access efficiency of memory array 210 effectively, utilize the dual-port characteristic of memory array 210 simultaneously, can be on one side first port of this memory array 210 be carried out access, second port to this memory array 210 reads on one side, and then can improve the sequential of system-on-a-chip.

From the above, no matter the present invention has all shown it totally different in the feature of prior art with regard to purpose, means and effect, has practical value.Only it should be noted that above-mentioned many embodiment only give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion with claims, but not only limits to the foregoing description.

Claims

1. a tool is hidden and is upgraded and the compatible embedded DRAM device of SRAM of dual-port ability, and it comprises:

Memory array, it comprises a plurality of dual port memories cell lattice;

First port access unit, it is connected to this memory array, in order to the internal memory cell lattice in this memory array of access;

Second port access unit, it is connected to this memory array, in order to the internal memory cell lattice in this memory array of access; And

Accessing arbitrator, it is connected to this first port access unit and this second port access unit, in order to arbitrate the first access port access requirement, the second access port access requirement and to hide more new demand.

2. device as claimed in claim 1, it also comprises:

Row decoding word set drive, it is connected to this accessing arbitrator and this memory array, in order to producing a word group line address, and then this memory array of addressing.

3. device as claimed in claim 2, wherein, this accessing arbitrator comprises:

Port controlling and address latch unit, it receives to the control signal of this first port access unit and address, to the control signal and the address of second port access unit, and produces access requirement signal, more new demand signal, the first port status signal and the second port status signal respectively; And

Storage control unit, be connected to this port controlling and address latch unit, require signal, this more new demand signal, this first port status signal and this second port status signal according to this access, and then produce the first port access control signal and the second port access control signal.

4. device as claimed in claim 3, wherein, this port controlling and address latch unit comprise:

The port controlling unit, it receives to the clock signal of this first port access unit and enable signal, to clock signal and the enable signal and the write signal of this second port access unit, in order to produce this first port status signal, this second port status signal and read-write mode signals;

First order moderator, it is connected to this port controlling unit, receive this first port status signal and this second port status signal, in order to produce the first port requirement signal and the second port requirement signal, and according to this first port requirement signal and this second port requirement signal, and then produce this access requirement signal; And

Data and address latch, it is connected to this first order moderator, require signal and this second port to require signal according to this first port, write data-signal in order to latch the first port address signal, the first port address signal and first port, and then produce first internal address signal, second internal address signal and input data signal.

5. device as claimed in claim 4, wherein, this port controlling and address latch unit comprise:

Upgrade timing unit, it is according to the Preset Time interval, and then generation triggers clock signal; And

Address-generation unit, it is connected to this renewal timing unit, produces this more new demand signal and scheduler signal according to this triggering clock signal.

6. device as claimed in claim 5, wherein, this storage control unit comprises:

Second level moderator, it is connected to this port controlling unit and this first order moderator, receive this access requirement signal, this more new demand signal, this first port status signal and this second port status signal, in order to produce the first port enable signal, the second port enable signal and to upgrade enable signal;

The first port controlling unit, it is connected to this port controlling unit, data and address latch and this second level moderator, according to this read-write mode signals, this first port enable signal, this renewal enable signal and this second internal address signal, to produce read-write, the first sensing amplifier enable signal and first column address signal;

The second port controlling unit, it is connected to these data and address latch and this second level moderator, according to this second port enable signal and this second internal address signal, in order to produce the second sensing amplifier enable signal and secondary series address signal.

7. device as claimed in claim 6, wherein, this storage control unit comprises:

The row control module, it is connected to this second level moderator and this data and address latch, according to this first port enable signal, this second port enable signal, this renewal enable signal and first internal address signal, can signal to produce the line position signal and to exercise.

8. device as claimed in claim 7, wherein, this first port access unit is the read/write access port, this second port access unit is for only writing access port.

9. device as claimed in claim 8, wherein, this first port access unit comprises:

The first column decoding unit, it is connected to these data and address latch and this first port controlling unit, carries out column decoding according to this first column address signal, and accepts this input data signal;

First line buffer, be connected to this first column decoding unit and this first port controlling unit, flow to determination data according to this read-write, it receives the data of being read by this memory array and transfers to this first column decoding unit, or receive the data that send by this first column decoding unit, and write this memory array; And

First sensing amplifier is connected to this first line buffer, this first port controlling unit and this memory array, receives this first sensing amplifier enable signal, carries out with the data that this memory array is read and amplifies, and then transfer to this first line buffer.

10. device as claimed in claim 9, wherein, this first column decoding unit can be read and write by the position of selecting a pixel in this first line buffer.

11. device as claimed in claim 8, wherein, this second port access unit comprises:

The secondary series decoding unit is connected to this second port controlling unit, carries out column decoding according to this secondary series address signal;

Second line buffer is connected to this secondary series decoding unit, in order to output data to this secondary series decoding unit; And

Second sensing amplifier is connected to this second line buffer, this second port controlling unit and this memory array, receives this second sensing amplifier enable signal, carries out with the data that this memory array is read and amplifies, and then transfer to this second line buffer.

12. device as claimed in claim 11, wherein, this secondary series decoding unit can be by selecting the part position to read in this second line buffer.

13. device as claimed in claim 11, wherein, this first order moderator uses first service earlier, in order to produce this first port requirement signal and this second port requirement signal.

14. device as claimed in claim 13, wherein, this second level moderator uses first service earlier, to produce this first port enable signal, this second port enable signal and this renewal enable signal.

15. device as claimed in claim 1, it is applicable to the LCD system, and this LCD system comprises:

Processor interface, the read-write of its receiving processor, and be connected to this embedded DRAM device; And

The LCD interface is connected to this embedded DRAM device, in order to present the data in this embedded DRAM device.

16. device as claimed in claim 15, wherein, this accessing arbitrator is the two-stage accessing arbitrator, wherein, this first port access unit access requires and hides more new demand and carry out the access arbitration in the phase one, and the victor requires to carry out the access arbitration in subordinate phase and this second port access unit access again.

17. device as claimed in claim 16, wherein, this processor interface is by this first port access unit, and in order to this memory array of access, this LCD interface is by this second port access unit, in order to this memory array of access.