CN101873125B - Reset circuit - Google Patents
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- CN101873125B CN101873125B CN2009100820758A CN200910082075A CN101873125B CN 101873125 B CN101873125 B CN 101873125B CN 2009100820758 A CN2009100820758 A CN 2009100820758A CN 200910082075 A CN200910082075 A CN 200910082075A CN 101873125 B CN101873125 B CN 101873125B
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- 239000004065 semiconductor Substances 0.000 claims description 45
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- 238000011946 reduction process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 17
- 230000007423 decrease Effects 0.000 description 8
- 230000005684 electric field Effects 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Abstract
The invention discloses a reset circuit, which comprises an MOS tube branch which is connected between a power supply and the ground and an inverter branch which is connected with the MOS tube branch through a partial pressure connection point, wherein the inverter branch comprises an inverter which is used for triggering voltage signal lower than the overturn voltage thereof and generating a reset signal; and the reset circuit further comprises an impedance component which is connected with the MOS tube branch and is used for reducing the voltage of the partial pressure connection point to be lower than the overturn voltage of the inverter when the voltage of the power supply is reduced to a first preset voltage, wherein the first preset voltage is higher than the threshold voltage of the MOS tube branch. Under the premise of saving power consumption and cost, the invention can prevent error condition from being generated during the voltage reduction process of the power supply.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of reset circuit.
Background technology
In the prior art; Reset circuit (Power on reset; POR) typically refer to electrify restoration circuit, it is primarily aimed at the error condition that logical circuit very easily occurs in power up, reach the operate as normal level of circuit at supply voltage after; Produce reset signal logical circuit is carried out initialization, to guarantee the correctness of Digital Logic.
For reaching the purpose of saving power consumption and cost, comparatively general por circuit will be closed after powering at present.Yet, also there is the error condition that occurs in many supply voltage decline processes in the reality, as when supply voltage is very low (near threshold voltage), the chip internal circuit all is in off state, and a lot of memory cell will obliterated data; Or as, when operate as normal, big fluctuation appears suddenly in power supply, and transient voltage is lower than threshold voltage, then can obliterated data, and when power supply was got back to normal condition, mistake will appear.
Therefore, need the urgent technical problem that solves of those skilled in the art to be exactly at present: how can propose a kind of reset circuit with innovating,, to avoid the error condition that occurs in the supply voltage decline process in order under the prerequisite of saving power consumption and cost.
Summary of the invention
Technical problem to be solved by this invention provides a kind of reset circuit, in order under the prerequisite of saving power consumption and cost, avoids the error condition that occurs in the supply voltage decline process.
In order to solve the problems of the technologies described above, the embodiment of the invention discloses a kind of reset circuit, comprise the metal-oxide-semiconductor branch road that is connected between power supply and the ground, and, the inverter branch road that is connected with said metal-oxide-semiconductor branch road through the dividing potential drop tie point; Said inverter branch road comprises inverter, and the voltage signal that is used to be lower than its turnover voltage triggers, and produces reset signal; Said reset circuit also comprises:
With the impedance device that said metal-oxide-semiconductor branch road is connected, be used for when supply voltage drops to first predeterminated voltage, make the voltage of said dividing potential drop tie point be lower than the turnover voltage of inverter; Wherein, said first predeterminated voltage is higher than the threshold voltage of metal-oxide-semiconductor branch road.
Said metal-oxide-semiconductor branch road comprises the PMOS pipe MP0 and the MP1 of two series connection, and said impedance device is a resistance R 0, and the source electrode of said PMOS pipe MP0 connects power supply, and grid connects bias voltage or ground connection; The end of the grid connecting resistance R0 of MP1, the other end ground connection of resistance R 0; Said dividing potential drop tie point comprises electric dividing potential drop tie point down, manages at said PMOS between the grid and resistance R 0 of MP1, and inserts the input of said inverter branch road.
Said reset circuit also comprises:
The NMOS pipe MN0 that is connected with said metal-oxide-semiconductor branch road, the source ground of said NMOS pipe MN0, grid connects the output of said inverter branch road, and drain electrode links to each other with the drain electrode of MP1.
Preferably, said dividing potential drop tie point also comprises the dividing potential drop tie point that powers on, and manages between the drain electrode of MN0 at drain electrode and the NMOS of said PMOS pipe MP1; The voltage signal that said inverter branch road also is used to be higher than its turnover voltage triggers, and produces the end signal that resets;
Said PMOS pipe MP0, MP1 and NMOS pipe MN0 are used for when supply voltage rises to second predeterminated voltage, and the voltage that makes the said dividing potential drop tie point that powers on is no-voltage; And, when supply voltage rises to the 3rd predeterminated voltage, make the said voltage that powers on the dividing potential drop tie point be higher than the turnover voltage of inverter; Wherein, said second predeterminated voltage is less than or equal to the threshold voltage of metal-oxide-semiconductor branch road, and said the 3rd predeterminated voltage is a circuit voltage.
Preferably, said inverter branch road comprises the odd number inverter.
Preferably, the output of said inverter branch road is the output of 2N+1 inverter, and said N is more than or equal to 0.
Preferably, said inverter branch road also comprises:
Capacitor element is used for the said end signal that resets is postponed to be passed to output.
Preferably, said resistance R 0 is the resistance greater than 1M Europe.
Preferably, said first predeterminated voltage is confirmed through adjustment PMOS pipe MP0, the size of MP1 and the size of resistance R 0.
Preferably, said the 3rd predeterminated voltage is confirmed through the size of adjustment PMOS pipe MP0, MP1 and NMOS pipe MN0.
Preferably, said reset circuit is used for chip.
Compared with prior art, the present invention has the following advantages:
The present invention is on the metal-oxide-semiconductor branch road that is connected between power supply and the ground; Increase impedance device with further dividing potential drop; Make when supply voltage drops near the threshold voltage of metal-oxide-semiconductor but not arrives the threshold voltage of metal-oxide-semiconductor, will the triggering for generating reset signal, the technological means that the present invention has adopted those skilled in the art to give up owing to technological prejudice; Under the prerequisite that consumes less power consumption and cost, effectively avoided the error situation in the various supply voltage decline processes with simple mode.
The present invention can also through further increase NMOS pipe realized a kind of power on and following electric process in all can produce the circuit of reset signal; The voltage control by inverter branch road output POR is opened and turn-offed to this NMOS pipe; Make the inverter branch road in power up, can selecting from power on, the dividing potential drop tie point obtains voltage; In following electric process; Can select to obtain voltage from following electric dividing potential drop tie point; Thereby under the prerequisite that satisfies less cost and power consumption, the state of supply voltage in power up that can be reflected according to this dividing potential drop tie point that powers on respectively, and; The state of the supply voltage that the electric dividing potential drop tie point of this time is reflected in following electric process produces or the end reset signal.
Description of drawings
Fig. 1 is a structure chart of using a kind of reset circuit of the embodiment of the invention 1;
Fig. 2 is the waveform sketch map of supply voltage VDD and resetting voltage POR;
Fig. 3 is a structure chart of using a kind of reset circuit of the embodiment of the invention 2.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing and embodiment the present invention done further detailed explanation.
In the prior art, por circuit will be closed after powering on, and does not all reply the function of position usually down by cable.Its reason is that following electric Implementation for Reset Function need increase power detection circuit down, and this will cause the increase of area; And this following power detection circuit is just understood the triggering for generating reset signal when supply voltage drops to the threshold voltage of metal-oxide-semiconductor; And in reality; When supply voltage was reduced to the threshold voltage of metal-oxide-semiconductor, some internal circuits played pendulum, and it is little that produce sense reset signal this moment.
For these reasons; Those skilled in the art's many research for a long time and innovation all concentrate in the improvement of electrify restoration circuit; Promptly, reach and save power consumption and cost based on electrify restoration circuit, and; Avoid the purpose of various error conditions appearance, can't go to consider the possibility of others.
Yet; The inventor herein notices, has the error condition that occurs in many supply voltage decline processes in the reality, as when supply voltage is very low (near threshold voltage); The chip internal circuit all is in off state, and a lot of memory cell will obliterated data; Or as, when operate as normal, big fluctuation appears suddenly in power supply, and transient voltage is lower than threshold voltage, then can obliterated data, and when power supply was got back to normal condition, mistake will appear.Obviously, existing electrify restoration circuit can't be tackled this situation fully.
To this; The inventor herein has proposed an a kind of following circuit implementing scheme of replying by cable of innovation, and one of core idea of this scheme is, on the metal-oxide-semiconductor branch road that is connected between power supply and the ground; Increase impedance device with further dividing potential drop; Make when supply voltage drops near the threshold voltage of metal-oxide-semiconductor but not arrives the threshold voltage of metal-oxide-semiconductor, will the triggering for generating reset signal, the technological means that the present invention has adopted those skilled in the art to give up owing to technological prejudice; Under the prerequisite that consumes less power consumption and cost, effectively avoided the error situation in the various supply voltage decline processes with simple mode.
In a kind of preferred embodiment 1 of the present invention, said reset circuit can comprise:
Be connected on the metal-oxide-semiconductor branch road between power supply and the ground;
The inverter branch road that is connected with said metal-oxide-semiconductor branch road through the dividing potential drop tie point; Said inverter branch road comprises inverter, and the voltage signal that is used to be lower than its turnover voltage triggers, and produces reset signal;
And,
With the impedance device that said metal-oxide-semiconductor branch road is connected, be used for when supply voltage drops to first predeterminated voltage, make the voltage of said dividing potential drop tie point be lower than the turnover voltage of inverter; Wherein, said first predeterminated voltage is higher than the threshold voltage of metal-oxide-semiconductor branch road.
Be well known that; Metal-oxide-semiconductor (MOSFET; The metal oxide film insulating gate type field effect tube); Grid G ate, source S ource and drain D rain are arranged, produce electric field through giving the Gate making alive, the channel electrons (hole density or channel width) between the control Source/Drain changes the impedance between the Source/Drain.That is to say whether the decision metal-oxide-semiconductor is opened and what open size of current is electric field and the threshold voltage of metal-oxide-semiconductor that is added on the raceway groove.In general, electric field strength is big more, and maximum current can be big more, and the ability that drives load is just strong more, and this voltage that just requires to be added on the grid is strong as far as possible.In addition, the ratio of input voltage and threshold voltage is big more, and just short more from starting voltage to the threshold voltage time, the formation time of raceway groove also can be shorter, and transistorized reaction speed is just fast more.
A kind of reset circuit structure of present embodiment in reality can be with reference to figure 1; In concrete the realization, said metal-oxide-semiconductor branch road can comprise the PMOS pipe MP0 and the MP1 of two series connection, wherein; The source electrode of MP0 meets power vd D; Grid can connect bias voltage or ground connection, and drain electrode links to each other with the source electrode of MP1, and the drain electrode of MP1 inserts the input of an inverter I0; Said impedance device can be resistance R 0, and the grid of MP1 can insert an end of resistance R 0, the other end ground connection of this resistance R 0.Said dividing potential drop tie point can be used as down electric dividing potential drop tie point A, places between the grid and resistance R 0 of said PMOS pipe MP1, and inserts the input of said inverter branch road.Preferably, the power consumption when reducing operate as normal, resistance R 0 can be chosen the resistance greater than 1M Europe.
With reference to supply voltage VDD shown in Figure 2 and the oscillogram of resetting voltage POR; In supply voltage VDD decline process, the voltage of following electric dividing potential drop tie point A is produced by MP0, MP1 and R0 dividing potential drop, when supply voltage drops to the first predeterminated voltage V1 (threshold voltage that is higher than the metal-oxide-semiconductor branch road); The A point voltage is lower than the turnover voltage of inverter I0; Make the output voltage upset of I0, thereby the magnitude of voltage that makes POR becomes VDD from 0, replies the position down by cable and starts.
In the circuit working process, the state MP0 of reflection supply voltage VDD, this DC channel of MP1 and R0 can exist always, and in reality, they only produce the current power dissipation less than 1uA; The magnitude of voltage of V1 can be through adjustment MP0, and the size of MP1 and the size of R0 are confirmed as one and be higher than metal-oxide-semiconductor branch road threshold voltage according value, and to this, corresponding adjustment setting gets final product those skilled in the art according to actual conditions.
Certainly, also only as example, it all is feasible that those skilled in the art adopt arbitrary corresponding construction according to the actual requirements to the structure of above-mentioned metal-oxide-semiconductor branch road, impedance device and inverter branch road, and the present invention need not this to limit.
In a kind of preferred embodiment 2 of the present invention, said reset circuit can comprise:
Be connected on the metal-oxide-semiconductor branch road between power supply and the ground;
The inverter branch road that is connected with said metal-oxide-semiconductor branch road through the dividing potential drop tie point; Said inverter branch road comprises inverter, and the voltage signal that is used to be lower than its turnover voltage triggers, and produces reset signal; And the voltage signal that is higher than its turnover voltage triggers, and produces the end signal that resets;
With the impedance device that said metal-oxide-semiconductor branch road is connected, be used for when supply voltage drops to first predeterminated voltage, make the voltage of said dividing potential drop tie point be lower than the turnover voltage of inverter; Wherein, said first predeterminated voltage is higher than the threshold voltage of metal-oxide-semiconductor branch road;
And,
The NMOS pipe MN0 that is connected with said metal-oxide-semiconductor branch road, the source ground of said NMOS pipe MN0, grid connects the output of said inverter branch road.
In the present embodiment, said dividing potential drop tie point can comprise the electric dividing potential drop tie point and the dividing potential drop tie point that powers on down, and said electric dividing potential drop tie point down is between said PMOS pipe MP1 and resistance R 0; The said dividing potential drop tie point that powers on is between said PMOS pipe MP1 and NMOS pipe MN0; Said PMOS pipe MP0, MP1 and NMOS pipe MN0 are used for when supply voltage rises to second predeterminated voltage, and the voltage that makes the said dividing potential drop tie point that powers on is no-voltage; And, when supply voltage rises to the 3rd predeterminated voltage, make the said voltage that powers on the dividing potential drop tie point be higher than the turnover voltage of inverter; Wherein, said second predeterminated voltage is less than or equal to the threshold voltage of metal-oxide-semiconductor branch road, and said the 3rd predeterminated voltage is higher than the threshold voltage of metal-oxide-semiconductor branch road.
The embodiment of the invention 2 is with the difference of embodiment 1; Embodiment 2 provides a kind of reset circuit that when powering on and descend electricity, all can produce reset signal; On the basis of embodiment 1 increase impedance device, further increased the NMOS pipe; The voltage control by inverter output POR is opened and turn-offed to this NMOS pipe, makes the inverter branch road in power up, and can selecting from power on, the dividing potential drop tie point obtains voltage; In following electric process; Can select to obtain voltage from following electric dividing potential drop tie point; Thereby under the prerequisite that satisfies less cost and power consumption, the state of supply voltage in power up that can be reflected according to this dividing potential drop tie point that powers on respectively, and; The state of the supply voltage that the electric dividing potential drop tie point of this time is reflected in following electric process produces or the end reset signal.
A kind of reset circuit structure of present embodiment in reality can be with reference to figure 3, and in concrete the realization, said metal-oxide-semiconductor branch road can comprise the PMOS pipe MP0 and the MP1 of two series connection; Wherein, The source electrode of MP0 meets power vd D, and grid can connect bias voltage or ground connection, and drain electrode links to each other with the source electrode of MP1; The drain electrode of MP1 connects the drain electrode of NMOS pipe MN0, and grid inserts an end of resistance R 0, the other end ground connection of this resistance R 0; The source ground of MN0, grid connect the output of inverter.
Be well known that when the grid of NMOS pipe did not have voltage (or ground level), source region and drain region were across double P-N knot depletion layer, electric current can't pass through, and the NMOS pipe is in the state that ends.When connecing small size positive voltage on the grid, the positive charge of P type semiconductor " hole " can be ostracised under the gate oxide, is close to gate oxide and will forms one deck depletion layer.When the voltage on the grid continues to raise above behind the specific voltage (threshold voltage); Electric field between grid and substrate is powerful in attracting a large amount of electronics from other place; This piece zone will form the very thin inversion layer of one deck; Because inversion layer has a large amount of charge carrier---electronics identical with leakage with the source, just formed the conductive channel of a connection source and leakage, nmos pass transistor is just open-minded.It almost is identical that the PMOS pipe is made principle with the NMOS plumber, and different is that the charge carrier of raceway groove was the hole during PMOS managed, and the polarity of gate voltage is also just the opposite to the formation role of raceway groove.
With reference to supply voltage VDD shown in Figure 2 and the oscillogram of resetting voltage POR, in the process that powers on, when supply voltage VDD is increased to the second predeterminated voltage V2 (threshold voltage that is less than or equal to the metal-oxide-semiconductor branch road); Said PMOS pipe MP0, MP1 fail conducting simultaneously; NMOS pipe MN0 is an off state, and in this case, the voltage of the dividing potential drop tie point B that powers between said PMOS pipe MP1 and NMOS pipe MN0 still is 0 (owing to the B point is 0; So R0 is inoperative this moment); This moment, level inverter in back was started working, and made the output voltage of inverter I0 overturn, thereby made the magnitude of voltage of inverter output POR become VDD from 0.
When supply voltage VDD continues to rise to the 3rd predeterminated voltage V3 (circuit voltage), said PMOS pipe MP0, MP1 and NMOS pipe MN0 conducting, the voltage of the dividing potential drop that powers on tie point B is because MP0; The dividing potential drop effect of MP1 and MN0 (this moment, the dividing potential drop influence of R0 was minimum greater than MN0 because of impedance); Rise to higher than the turnover voltage of inverter I0, in this case, the output voltage of inverter I0 upset; Thereby make the magnitude of voltage of output POR become 0 from VDD, electrification reset finishes.
In reality, said the 3rd predeterminated voltage V3 can confirm through the size of adjustment PMOS pipe MP0, MP1 and NMOS pipe MN0.
As another embodiment; Said inverter branch road can also comprise a capacitor element C0, a termination VDD of this capacitor C 0, the output of a termination inverter; Be used for the said end signal that resets is postponed to be passed to output, thus prevent that power supply electrifying is too fast and cause reset insufficient.
In electric down process, because inverter output POR is 0, NMOS pipe MN0 is an off state; The voltage of electric dividing potential drop tie point A is produced by MP0, MP1 and R0 dividing potential drop down; When supply voltage dropped to the first predeterminated voltage V1 (threshold voltage that is higher than the metal-oxide-semiconductor branch road), the A point voltage was lower than the turnover voltage of inverter I0, made the output voltage of I0 overturn; Thereby the magnitude of voltage that makes POR becomes VDD from 0, replies the position down by cable and starts.
Preferably, the power consumption when reducing operate as normal, resistance R 0 can be chosen the resistance greater than 1M Europe.In the circuit working process, the state MP0 of reflection supply voltage VDD, this DC channel of MP1 and R0 can exist always, and in reality, they only produce the current power dissipation less than 1uA; The magnitude of voltage of V1 can be through adjustment MP0, and the size of MP1 and the size of R0 are confirmed as one and be higher than metal-oxide-semiconductor branch road threshold voltage according value.
In a kind of preferred embodiment of the present invention; Said inverter branch road can comprise the odd number inverter, 5 inverter I0, I1, I2, I3 and I4 as shown in Figure 3, and the output of said inverter branch road can be the output of 2N+1 inverter; Wherein, Said N is more than or equal to 0, and promptly for Fig. 3, the output of inverter I0, I2 or I4 all can act on the output of current inverter branch road; The grid of said NMOS pipe MN0 also can insert the output of said inverter I0 or 14 except that the output of access inverter I2 as shown in Figure 3.
In concrete the realization, said reset circuit can be used for chip, for example, is used in the memory chip, is not lost in supply voltage decline process with the data in the protection memory cell.Certainly, being used in also is feasible in other single-chip microcomputer or the microcomputer, and the present invention only provides a kind of applying examples at this.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
More than a kind of reset circuit provided by the present invention has been carried out detailed introduction; Used concrete example among this paper principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (9)
1. a reset circuit is characterized in that, comprises the metal-oxide-semiconductor branch road that is connected between power supply and the ground, and, the inverter branch road that is connected with said metal-oxide-semiconductor branch road through the dividing potential drop tie point; Said inverter branch road comprises inverter, and the voltage signal that is used to be lower than its turnover voltage triggers, and produces reset signal; Said reset circuit also comprises:
With the impedance device that said metal-oxide-semiconductor branch road is connected, be used for when supply voltage drops to first predeterminated voltage, make the voltage of said dividing potential drop tie point be lower than the turnover voltage of inverter; Wherein, said first predeterminated voltage is higher than the threshold voltage of metal-oxide-semiconductor branch road;
Wherein, said metal-oxide-semiconductor branch road comprises the PMOS pipe MP0 and the MP1 of two series connection, and said impedance device is a resistance R 0, and the source electrode of said PMOS pipe MP0 connects power supply, and grid connects bias voltage or ground connection; The end of the grid connecting resistance R0 of MP1, the other end ground connection of resistance R 0; Said dividing potential drop tie point comprises electric dividing potential drop tie point down, manages at said PMOS between the grid and resistance R 0 of MP1, and inserts the input of said inverter branch road;
Said reset circuit also comprises:
The NMOS pipe MN0 that is connected with said metal-oxide-semiconductor branch road, the source ground of said NMOS pipe MN0, grid connects the output of said inverter branch road, and drain electrode links to each other with the drain electrode of MP1.
2. reset circuit as claimed in claim 1 is characterized in that, said dividing potential drop tie point also comprises the dividing potential drop tie point that powers on, and manages between the drain electrode of MN0 at drain electrode and the NMOS of said PMOS pipe MP1; The voltage signal that said inverter branch road also is used to be higher than its turnover voltage triggers, and produces the end signal that resets;
Said PMOS pipe MP0, MP1 and NMOS pipe MN0 are used for when supply voltage rises to second predeterminated voltage, and the voltage that makes the said dividing potential drop tie point that powers on is no-voltage; And, when supply voltage rises to the 3rd predeterminated voltage, make the said voltage that powers on the dividing potential drop tie point be higher than the turnover voltage of inverter; Wherein, said second predeterminated voltage is less than or equal to the threshold voltage of metal-oxide-semiconductor branch road, and said the 3rd predeterminated voltage is a circuit voltage.
3. reset circuit as claimed in claim 2 is characterized in that, said inverter branch road comprises the odd number inverter.
4. reset circuit as claimed in claim 3 is characterized in that, the output of said inverter branch road is the output of 2N+1 inverter, and said N is more than or equal to 0.
5. reset circuit as claimed in claim 4 is characterized in that, said inverter branch road also comprises:
Capacitor element is used for the said end signal that resets is postponed to be passed to output.
6. reset circuit as claimed in claim 1 is characterized in that, said resistance R 0 is the resistance greater than 1M Europe.
7. reset circuit as claimed in claim 1 is characterized in that, said first predeterminated voltage is confirmed through adjustment PMOS pipe MP0, the size of MP1 and the size of resistance R 0.
8. reset circuit as claimed in claim 2 is characterized in that, said the 3rd predeterminated voltage is confirmed through the size of adjustment PMOS pipe MP0, MP1 and NMOS pipe MN0.
9. reset circuit as claimed in claim 1 is characterized in that said reset circuit is used for chip.
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|---|---|---|---|
| CN2009100820758A CN101873125B (en) | 2009-04-22 | 2009-04-22 | Reset circuit |
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| CN2009100820758A CN101873125B (en) | 2009-04-22 | 2009-04-22 | Reset circuit |
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| CN101873125B true CN101873125B (en) | 2012-06-13 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006039B (en) * | 2010-12-14 | 2012-10-03 | 苏州华芯微电子股份有限公司 | Reset circuit |
| CN102270979B (en) * | 2011-04-12 | 2013-03-20 | 建荣集成电路科技(珠海)有限公司 | Power-on resetting circuit |
| TWI545541B (en) * | 2015-06-02 | 2016-08-11 | 瑞鼎科技股份有限公司 | Power on reset circuit applied to gate driver of display apparatus |
| CN106059550A (en) * | 2016-06-03 | 2016-10-26 | 乐视控股（北京）有限公司 | System reset circuit and electronic device |
| CN107342758B (en) * | 2017-07-20 | 2020-11-27 | 苏州精诚智造智能科技有限公司 | Closed-loop control reset circuit based on RC reset module |
| CN109257035B (en) * | 2018-08-30 | 2022-04-05 | 龙迅半导体（合肥）股份有限公司 | Power-on reset circuit |
| CN111510122A (en) * | 2020-04-15 | 2020-08-07 | 华南理工大学 | Power-on reset device of multi-power system |
| CN113746460A (en) * | 2021-08-19 | 2021-12-03 | 北京中科胜芯科技有限公司 | Multi-power-supply power-on reset circuit |
| CN116700458B (en) * | 2023-08-09 | 2024-01-26 | 深圳奥简科技有限公司 | Voltage monitoring reset circuit and electronic equipment |
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| CN1637945A (en) * | 2003-12-30 | 2005-07-13 | 海力士半导体有限公司 | Power-up circuit semiconductor memory device |
| CN101009485A (en) * | 2006-01-05 | 2007-08-01 | 三星电子株式会社 | Reset signal generator in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1637945A (en) * | 2003-12-30 | 2005-07-13 | 海力士半导体有限公司 | Power-up circuit semiconductor memory device |
| CN101009485A (en) * | 2006-01-05 | 2007-08-01 | 三星电子株式会社 | Reset signal generator in semiconductor device |
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| Title |
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| JP特开2006-74210A 2006.03.16 |
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