CN101854541B - Video compression circuit and method thereof - Google Patents
Video compression circuit and method thereof Download PDFInfo
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Abstract
The invention discloses a video compression circuit and a method thereof. The video compression circuit comprises a video preprocessor, a macro block data storage unit and a video processor. When input videos fully fill the video processor, the video preprocessor transforms the arrangement manner of the input videos to generate macro block data; the macro block data storage unit temporarily stores the macro block data generated by the video preprocessor in an alternating manner; and the video processor reads the macro block data stored in the macro block data storage unit in an alternating manner and compresses the macro block which is taken out so as to generate an input video.
Description
Technical field
The invention relates to a kind of video compression circuit and method thereof, and particularly relevant for a kind of video compression circuit and method thereof that reduces circuit cost and reduce processing delay time.
Background technology
Along with network is popularized, audio-visual Video Streaming more and more widely is applied on the consumer products.People also come high to the requirement of video quality, so, better video compression technology (Video Compression) like MPEG4, H.264 wait and arise at the historic moment, so that handle (compression/de-compression) more high-resolution image quality.When carrying out video compression, store input video (that is original video) and rebuild later video (that is compression rear video) in memory.
With present, (external SDRAM ESM) can be used as the storage area to the external dynamic random access memory, to store input video and to rebuild video later.When storing input video, need use two input video memories (input video memory), a block storage space is used to write input video, and another block storage space is used to read input video.With present, the size of these two input video memories all is the size of a picture data usually.Likewise, when storing the reconstruction rear video, also need use two reconstruction video memories (reconstruct video memory), a block storage space is used to write the reconstruction rear video, and another block storage space is used to read the reconstruction rear video.With present, these two sizes of rebuilding the rear video memory at least all are the sizes of a picture data.
Yet, along with video resolution is high more, uses more jumbo memory and store video, make cost that memory accounts for video compression circuit than regular meeting along with increase.So, will cause the cost of video compression chip to increase.
In addition, in the prior art, to wait until that usually an input video memory fills up back (the complete input of picture back just) fully; Could begin to compress, so, its time of delay long (that is; The time that is about a picture time of delay), cause the reduction of compression speed.
So, how effectively to lower memory span and reduce time of delay, become the good corrupt key of video compression circuit.
Summary of the invention
The invention relates to a kind of video compression circuit and method thereof, it can significantly reduce the time of delay of input video.
The invention relates to a kind of video compression circuit and method thereof, it can significantly reduce required reconstruction video memory, lets cost of hardware design reduce.
According to an aspect of the present invention, propose a kind of video compression circuit, comprising: video pre-processor; This video pre-processor is kept in input video; When this video pre-processor was filled, the arrangement mode of this this input video of video pre-processor conversion was to produce macro block data; The macro block data storage element is coupled to this video pre-processor, with temporary this macro block data; And video processor, be coupled to this macro block data storage element, in order to compress this macro block data that is taken out from this macro block data storage element, to produce output video.
According to a further aspect in the invention, propose a kind of video-frequency compression method, comprising: receive and temporary input video; The arrangement mode of changing this input video is to produce macro block data; Alternative expression is kept in this macro block data; And alternative expression reads this macro block data of being kept in, and this macro block data that compression keep in is with the generation output video.
Description of drawings
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows:
Fig. 1 shows the block schematic diagram of video compression circuit according to an embodiment of the invention.
How Fig. 2 shows data are arranged by level in regular turn and converts macro block to and arrange.
Fig. 3 shows life cycle how to estimate each macro block.
Fig. 4 shows the calcspar according to the video processor of the embodiment of the invention.
Fig. 5 shows in embodiments of the present invention, the sketch map that the circulation of rebuilding picture buffering memory 133 is write and reads.
The primary clustering symbol description
100: video compression circuit
110: video pre-processor
111: the input video buffer storage
112: level is arranged in regular turn changes the macro block arrangement units
120: the macro block data storage element
121,122: the macro block data buffer storage
130: video processor
131: the video compression unit
132: Memory Controller
133: the reconstruct buffer storage
IN: input video
OUT: output video
201,202: macro block data
310: last picture
320: present picture
311,321: macro block data
312: reference macroblock
313: one row's macro block datas
410: compressed core,
411:AHB master's device
412:AHB servant's device
430: read buffer memory
440: write buffering memory
450:AHB servant's device
RP: read index
WP: write index
RD: reconstruct data
IS: information signal
Embodiment
In embodiments of the present invention, can significantly reduce the desired volume of input video memory and reconstruction video memory, so can effectively reduce the hardware cost of video compression circuit.In addition, after the some that receives an input picture, just can begin to carry out contractive pressure, so it can significantly reduce the time of delay of input video.
Please refer to Fig. 1, it shows the block schematic diagram of video compression circuit 100 according to an embodiment of the invention at present.As shown in Figure 1, video compression circuit 100 comprises at least: video pre-processor 110, macro block data storage element 120 and video processor 130.Video pre-processor 110 comprises at least: input video buffer storage 111 is arranged the arrangement of commentaries on classics macro block in regular turn with level, and (raster to block, RTB) unit 112.A plurality of (such as two) macro block datas (macroblock) buffer storage (MB) 121 and 122 that macro block data storage element 120 comprises at least.Video processor 130 comprises at least: video compression unit 131, Memory Controller 132 and reconstruct buffer storage 133.
Video pre-processor 110 is in order to temporary input video IN, and it is carried out the conversion of arrangement mode, to export to macro block data storage element 120.In more detail, input video IN can be temporary in the input video buffer storage 111 in the video pre-processor 110.Input video buffer storage 111 is such as comprising 16 line buffer storage (line buffer).With the size of the picture of input video IN be 352*288 (that is; A picture has 288 lines; Each bar line has 352 pixel datas) be example, per 1 the line buffer storage in the input video buffer storage 111 can store a picture data in the picture.Input video IN inputs in the input video buffer storage 111 with horizontal mode (raster scan).
After input video buffer storage 111 was filled, RTB unit 112 can be arranged the data in the input video buffer storage 111 in regular turn by level and convert the macro block arrangement mode to.Please refer to Fig. 2, how it show the data in the input video buffer storage 111 are arranged by level in regular turn and convert macro block to and arrange at present.As shown in Figure 2, after input video buffer storage 111 was filled for the first time, 16 pixel datas in the foremost of each bar line buffer storage can be taken out by RTB unit 112, to treat as macro block data (macroblock data) 201.Then, the 17th～the 32nd pixel data of each bar line buffer storage can be taken out by RTB unit 112, to treat as macro block data 202.Mode according to this, RTB unit 112 can take out the data in the input video buffer storage 111, and is arranged in the macro block arrangement mode.The macro block data that is taken out can be input in the macro block data storage element 120.
After a macro block data was removed from input video buffer storage 111, video pre-processor 110 just can continue to receive input video IN again, and it is override in the storage location that is removed data.Mode according to this, in embodiments of the present invention, can be reduced to the time of 16 lines the time of delay of Video processing by an image time of prior art.Size with the picture of input video IN is that 352*288 is an example; In the prior art, be the time of a picture (288 bar line) time of delay of Video processing, and in the present embodiment; Be the time of 16 lines the time of delay of Video processing; So, can know, be reduced to the 16/288=1/18 of prior art the time of delay of Video processing.
Macro block data storage element 120 is in order to the temporary macro block data that is taken out by RTB unit 112, and macro block data is exported to the video processor 130 of rear end.That is the macro block data that is taken out by RTB unit 112 can alternately be written into two the macro block buffer storage 121 and 122 in the macro block data storage element 120.Such as, the first stroke macro block data that is taken out is stored in macro block buffer storage 121 earlier.Then, second macro block data that is taken out then is stored in macro block buffer storage 122.Afterwards, the 3rd macro block data that is taken out then is stored in macro block buffer storage 121.
Macro block buffer storage 121 and 122 is alternately write and reads by RTB unit 112 and video processor 130.When RTB unit 112 write macro block data in one of macro block buffer storage 121 and 122, another that then video processor 130 can be from macro block buffer storage 121 and 122 read out macro block data, to carry out video compression.So alternative expression read-write macro block data storage element 120 can be avoided data to write and read clashing.
The macro block data that video processor 130 is taken out from macro block data storage element 120 in order to compression is to produce output video OUT.When carrying out video compression, can be with reference to last Zhang Chongjian rear video, improve compression ratio (just let the size of output video OUT as far as possible little).In embodiments of the present invention, be the use avoid that the reading and writing data conflict takes place and to reduce memory, estimate with the data life period (data life cycle) of memory management technique and the required minimized memory space of reconstruct buffer storage 133.In video compression algorithm, minimal data unit is macro block (macroblock).So, calculate the life cycle of each macro block, just can calculate required minimized memory space.When calculating the life cycle of each macro block, move and estimate that (motion estimation search range, size MESR) can have influence on the life cycle of macro block to search area.
Please refer to Fig. 3, it shows life cycle how to estimate each macro block.In Fig. 3, last picture of 310 representatives, and the present picture of 320 representatives, 311 and 321 represent macro block data, and 312 represent reference macroblock.Wherein, macro block data 311 is same as the position of macro block data 321 at present picture 320 in the position of last picture 310.In the present embodiment, with move to estimate search area be 16 and macroblock size be that 16*16 does explanation, but those skilled in the art will appreciate that the present invention is not limited to this.The setting of reference macroblock 312 is according to macro block data (311 or 321) and mobile estimation search area.With Fig. 3 is example, and the direction that the scope of reference macroblock 312 is macro block datas 311 about up and down respectively adds 16 points (a bit representing a pixel information), so, be example with Fig. 3, the size of reference macroblock 312 is 48*48.
When rebuilding the present macro block data 321 of present picture 320, can be with reference to the reference macroblock 312 of last picture 310, and find out the similar macro blocks data (it is similar in appearance to present macro block data 321) in the reference macroblock 312, rebuild macro block data 321 according to this.The mode of finding out similar macro blocks data can not limit it especially at this.When finding out similar macro blocks data, can obtain another parameter: dynamic vector (motionvector), it represents the relative position (with respect to the position of macro block data 311 or 321) of these similar macro blocks data.
Please refer again to Fig. 3; When all macro block datas that are positioned at same row with the present macro block data 321 of present picture 320 all behind the below one row's macro block data 313 with reference to the macro block data 311 of intact last picture 310, this row's macro block data 313 of last picture 310 just can be written.The life cycle of hence one can see that each macro block is that an image time adds row's macro block data time.So if write the some position of the data of a certain macro block in memory sometime, this of that memory position needs to add that at an image time row's macro block data just can be written after the time.Minimum storage area required when therefore wanting reconstruct adds that for (1) stores a required size of picture (2) store the required size of row's macro block data.Following with formulate:
MS＝FS+MESR*RN/X
Wherein, MS represents the size of reconstruct buffer storage 133, and the FS representative stores the storage space that picture is required, and the estimation search area is moved in the MESR representative, and RN represents the size of row's macro block data, and X then is the height of macro block data.
Please refer to table 1 to illustrate further the effect of present embodiment.Table 1 is under different mobile estimation search areas (MESR), the comparison of the reconstruct buffer storage that present embodiment and prior art are required.Can find out that by table 1 in embodiments of the present invention, the required capacity of reconstruct buffer storage greatly reduces.
Table 1
| MESR | Prior art (byte) | Present embodiment (byte) | Save |
| 16 | 2764800 | 1413120 | 49％ |
| 32 | 2764800 | 1443840 | 48％ |
| 64 | 2764800 | 1474560 | 47％ |
Please refer to Fig. 4, it shows the calcspar according to the video processor 130 of the embodiment of the invention at present.As shown in Figure 4; Video compression unit 131 in the video processor 130 comprises at least: compressed core 410, AHB (advanced high performance bridge; High-effect bridge) main device 411, AHB servant's device 412, read buffer memory (read buffer; RB) 430 with write buffering memory (writebuffer, WB) 440.Memory Controller 132 also comprises AHB servant's device 450.
Because the capacity of reconstruct buffer storage 133 is quite big and its frequency of operation is slow; Can't be the same fast with compressed core 410; So; Often wait for that for avoiding compressed core 410 to need the reading and writing data of reconstruct buffer storage 133 badly influences execution efficient (performance), at present embodiment, meeting is read-write (pre-fetch) reconstruct buffer storage 133 in advance.Can be stored in earlier in the read buffer memory 430 by 133 data of reading in advance of reconstruct buffer storage, just deliver to compressed core 410 afterwards.Likewise, the data that compressed core 410 will be written into reconstruct buffer storage 133 then are stored in write buffering memory 440 in advance, just deliver to reconstruct buffer storage 133 afterwards.
For reading and writing reconstruct buffer storage 133 in advance, Memory Controller 132 receives the information signal IS that is seen off by compressed core 410, and on behalf of compressed core 410, it handle the relevant information of (read/write) macro block data at present.In the present embodiment, information signal IS for example is but is not limited to, dynamic vector, macro block data numbering etc.
Carrying out data when reading; After Memory Controller 132 is received information signal IS; Memory Controller 132 can be calculated compressed core 410 needed next record data (a just last reconstruct) and read position (that is reading pointer RP) in reconstruct buffer storage 133; And these data are read in advance and load in the read buffer memory 430, afterwards with these data as reconstruct data RD and deliver to compressed core 410.
Likewise; Write fashionable carrying out data; After Memory Controller 132 is received information signal IS; Memory Controller 132 can be calculated the writing position (that is write index WP) of present data after 410 compressions of compressed core (just rebuilding the back picture at present) in reconstruct buffer storage 133, and these data (the reconstruct data RD that is seen off by compressed core 410) are write to write buffering memory 440 earlier, just delivers to reconstruct buffer storage 133 afterwards.If reconstruct buffer storage 133 is the buffer storage at single port, then write activity with read action and will in regular turn and stagger and carry out.Certainly, reconstruct buffer storage 133 can be the buffer storage at two ports, so, write activity with read action and can carry out simultaneously.
AHB servant's device 450 of Memory Controller 132 can receive/transmit data in compressed core 410.The compressed core that meets ahb bus (AHB bus) definition all can be as the compressed core 410 of present embodiment.
Fig. 5 shows in embodiments of the present invention, the sketch map that the circulation of rebuilding picture buffering memory 133 is write and reads.When circulation write and read reconstruct buffer storage 133, Memory Controller 132 can be changed the read/write address that compressed core 410 is seen off, produced read-write indication RP and WP according to this.That is to say that in the present embodiment, reconstruct buffer storage 133 is buffer storage (ringbuffer) circlewise.When reading, be according to reading index RP, read picture behind the last Zhang Chongjian in the reconstruct buffer storage 133, giving compressed core, as with reference to using.And write fashionablely, picture after the present reconstruction is loaded in the reconstruct buffer storage 133 by write buffering memory 440 according to writing index WP.
In sum, the disclosed video compression circuit of the above embodiment of the present invention has multiple advantages, below just lists and lifts the explanation of part advantage as follows:
1. reduce the temporary required memory of input video.
2. picture is shortened to the time of 16 lines time of delay by an image time.
3. reduce the capacity of reconstruct buffer storage, utilize good storage management, the capacity of the reconstruct buffer storage that present embodiment is used is about the half the of prior art.
In sum, though the present invention describes as above with embodiment, it is not in order to limit the present invention.Person of ordinary skill in the field of the present invention is not breaking away from the spirit and scope of the present invention, can do various changes and retouching.Therefore, protection scope of the present invention should be as the criterion with the scope that accompanying Claim was defined.
Claims (6)
1. video compression circuit comprises:
Video pre-processor, the temporary input of this video pre-processor image, when this video pre-processor was filled, the arrangement mode of this this input image of video pre-processor conversion was to produce macro block data;
The macro block data storage element is coupled to this video pre-processor, with temporary this macro block data; And
Video processor is coupled to this macro block data storage element, in order to compress this macro block data that is taken out from this macro block data storage element, and with the generation image output,
Wherein, when the unit of this input image is a picture, when compressing, this video processor with reference to the last Zhang Chongjian of this input image after image, rebuild image after the present reconstruction of this input image,
Wherein, Rebuild this input image should rebuild first macro block data in the image of back at present the time; This video processor with reference to this last Zhang Chongjian of this input image after reference macroblock in the image; The setting of this reference macroblock is the position data and mobile estimation search area parameter according to this first macro block data
Wherein, When rebuilding, this video processor with reference to this last Zhang Chongjian of this input image after this reference macroblock in the image, and find out the interior similar macro blocks data of this reference macroblock; That rebuilds this input image according to this should rebuild this first macro block data in the image of back at present
When finding out the similar macro blocks data of in this reference macroblock this, this video processor obtains the dynamic vector parameter, and it represents the relative position of these similar macro blocks data,
This video processor comprises at least:
The video compression unit, this macro block data that reception and compression are taken out from this macro block data storage element;
Memory Controller is coupled to this video compression unit; And
The reconstruct buffer storage is coupled to this Memory Controller and this video compression unit,
Wherein, Under the control of this Memory Controller; Image behind this last Zhang Chongjian of this input image is read in this video compression unit from this reconstruct buffer storage, and should the rebuilding back image at present and write to this reconstruct buffer storage of this input image after will compressing
Wherein, this video compression unit comprises at least:
Compressed core, this macro block data that reception and compression are taken out from this macro block data storage element;
High-effect bridge master's device; Interface is in this Memory Controller; Wherein, The reconstruct data that this compressed core will write to this reconstruct buffer storage are to deliver to this Memory Controller through this high-effect bridge master's device, and these reconstruct data of being read by this reconstruct buffer storage are to deliver to this compressed core through this high-effect bridge master's device;
High-effect bridge servant's device, through this high-effect bridge servant's device, this compressed core receives by the setup parameter that the external world imported, to set this compressed core;
Read buffer memory, these reconstruct data of being read in advance from this reconstruct buffer storage can be stored in earlier in this read buffer memory, just deliver to this compressed core afterwards; And
These reconstruct data that write buffering memory, this compressed core will be written into this reconstruct buffer storage then are stored in this write buffering memory in advance, just deliver to this reconstruct buffer storage afterwards.
2. video compression circuit as claimed in claim 1; Wherein, for reading and writing this reconstruct buffer storage in advance, this Memory Controller receives the information signal of being seen off by this compressed core; This information signal is represented the relevant information of this first macro block data that this compressed core handling at present
Wherein, this information signal comprises the number information of this dynamic vector parameter, this first macro block data.
3. video compression circuit as claimed in claim 1; Wherein, When reading; After this Memory Controller was received this information signal, image was in the position of reading of this reconstruct buffer storage after this Memory Controller was calculated this last Zhang Chongjian of needed this input image of this compressed core, and image is read in advance and load in this read buffer memory after will importing this last Zhang Chongjian of image; To import behind this last Zhang Chongjian of image image afterwards as these reconstruct data and deliver to this compressed core
Wherein, Write fashionable carrying out data; After this Memory Controller is received this information signal; What this Memory Controller can be calculated this input image after this compressed core compresses should rebuild the writing position of back image in this reconstruct buffer storage at present, and image write to this write buffering memory earlier after will import the reconstruction at present of image, just delivered to this reconstruct buffer storage afterwards.
4. video compression circuit as claimed in claim 1, wherein this video pre-processor comprises:
Input image buffer storage; The temporary input image that is somebody's turn to do; When the unit of this input image was a picture, capacity of this input image buffer storage was less than a picture, and this input image is arranged in regular turn with level and is stored in this input image buffer storage.
5. video compression circuit as claimed in claim 1, wherein this video pre-processor also comprises:
The arrangement mode converting unit; Be coupled to this input image buffer storage; When this input image fills up this input image buffer storage; This arrangement mode converting unit is read this input image from this input image buffer storage, and the arrangement mode that will import image arranged in regular turn by level and convert macro block to and arrange, to produce this macro block data.
6. video compression circuit as claimed in claim 1, wherein this macro block data storage element comprises:
First and second macro block data buffer storage stores this macro block data that this video pre-processor transmitted in order to alternative expression, and this first is alternately write and read by this arrangement mode converting unit and this video processor with this second macro block data buffer storage.
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