CN101848081A - S box and construction method thereof - Google Patents

Abstract

The invention discloses an S box and a construction method thereof, which belong to the technical field of communication. The method comprises the following steps: (1) selecting an integer m and three n-in-n-out conversion units P1, P2 and P3, wherein P2 is a replacement unit, and n is an integer being not less than 2; (2) marking the high n bit of input 2n bit information x as x1 and the low n bit thereof as x2; (3) converting x2 by P1 and then carrying out exclusive or with x1, outputting and recording as t1; (4) converting t1 by P2 and then carrying out exclusive or with x2, outputting and recording as t2; (5) converting t2 by P3 and then carrying out exclusive or with t1, outputting and recording as t3; (6) connecting t3 as the high n bit with t2 as the low n bit to form 2n-bit information, and recording as t; and (7) circularly shifting the information t to left for m bits and then outputting. The S box comprises three exclusive or units A, B and C, the three conversion units P1, P2 and P3 and one line sequence replacement unit. Compared with the prior art, the S box method is easy to realize, and the constructed S box has good cryptology characteristic and high running efficiency.

Description

A kind of S box building method and S box

Technical field

The present invention relates to the method for a kind of message transmission and processing, relate in particular to a kind of S box building method and S box, belong to communication technical field.

Background technology

Cryptographic technique is with a long history, is used for the military and diplomatic correspondence safety of protection at first.But along with popularizing of communication network and computer network, the application of contemporary cryptology no longer is confined to politics, military affairs and diplomatic, and its commercial value and social value have obtained approval widely.Maintaining secrecy is cryptographic core, is the utility that acquired information is maintained secrecy and encrypt.

Cryptographic algorithm is divided into public key algorithm and private key cryptographic algorithm.The private key cryptographic algorithm is divided into block cipher and stream cipher algorithm again.Block cipher generally carries out block encryption to message, and a bigger message blocks is once encrypted in the algorithm operation.Stream cipher algorithm generally with the key of a weak point, with specific key stream generating algorithm, generates and the suitable key stream sequence of message-length that will encrypt, key stream sequence and plaintext step-by-step XOR is reached the purpose of encryption.And deciphering side generates same key stream sequence, with the ciphertext XOR, can obtain expressly.

Design safety, cryptographic algorithm efficiently are the focuses that various countries fall over each other to study always.In existing many block ciphers and stream cipher algorithm, the S box non-linear component that is absolutely necessary.As the AES block cipher in U.S.'s encryption standard, in the SNOW 3G stream cipher algorithm in the ETS, the S box provides the major part of whole algorithm non-linearity.Therefore, the S box that designs is the basis of a cryptographic algorithm of design.Simultaneously, the hardware-efficient of S box is realized, and is most important for the realization of cryptographic algorithm.Especially for hardware resource limited add, decryption device, require the hardware of S box to realize that the door number is few as much as possible.

The design of S box, generally based on the computing of certain structure, for example the S box of AES is based on the inversion operation on the finite field.Because the computing on the finite field will consume a large amount of resources, so realize this S box, realizes by tabling look-up usually.Advance the 8 S boxes that go out for 8, generally need 500 circuit scale.

For this reason, we have proposed a method based on structure construction S box, and this structure utilization simply is easy to hard-wired displacement and non-displacement transformation, the S box that structure has good cryptography character.Simultaneously we based on this structure construction a kind of box of S efficiently hardware module, its hardware size be table look-up realize 1/5.

Summary of the invention

The purpose of technical scheme of the present invention is to provide a kind of S box building method and S box, and this method is a kind of method based on structure construction S box, utilizes three 4 and advances 4 conversion that go out, and structure 8 advances the 8 displacement S boxes that go out.This S box is easy to software and hardware and realizes and can provide cryptography character such as good algebraically, difference, non-linearity, and important effect is all arranged in the design of block cipher and stream cipher algorithm, is indispensable assembly.Another object of the present invention is to provide a kind of S box hardware module, the general S cartridge module of this module scale is little.

Technical scheme of the present invention is:

A kind of S box building method the steps include:

1) a selected integer m and three n advance the converter unit that n goes out: P ₁, P ₂, P ₃P wherein ₂Be permute unit, n is the integer number more than or equal to 2;

2) the 2n bit information x with input is divided into two parts, is designated as x ₁, x ₂, wherein, x ₁High n position, x for input information ₂Low n position for input information;

3) with x ₂Through P ₁After the conversion with x ₁XOR, output result note is made t ₁

4) with t ₁Through P ₂After the conversion with x ₂XOR, output result note is made t ₂

5) with t ₂Through P ₃After the conversion with t ₁XOR, output result note is made t ₃

6) with t ₃As high n position, t ₂Be connected to become the information of a 2n bit as low n position, note is made t;

7) information t ring shift left m position is exported.

Further, the value of described integer m is 1～2n-1; Described P ₁, P ₃For n advances the mapping that n goes out; Described n is the integer more than or equal to 2.

Further, adopt a line preface permute unit that information t ring shift left m position is exported.

Further, the conversion described step 3)～5) adopts combinational logic circuit to realize; Wherein the critical path of combinational logic circuit is: x ₂→ P ₁→ XOR → P ₂→ XOR → P ₃→ XOR.

Further, the conversion described step 3)～5) adopts sequence circuit to realize.

Further, described employing sequence circuit realizes that the method for conversion is:

1) with P ₁, P ₂, P ₃In information be stored in respectively in the memory;

2) according to P ₁The base address, with x ₂Read the P that stores in the described memory for offset address ₁Information is with itself and x ₁Carry out being updated among the n bit register L behind the XOR;

3) according to P ₂The base address, as offset address, read the P that stores in the described register with the output of this register L ₂Information is with itself and x ₂Carry out being updated among the n bit register R behind the XOR;

4) according to P ₃The base address, as offset address, read the P that stores in the described register with the output of this register R ₃

Information is carried out XOR with itself and this register L.

A kind of S box is characterized in that comprising three XOR unit A, B, C, three converter unit P ₁, P ₂, P ₃, a line preface permute unit; Wherein two inputs of XOR unit A respectively with a n bit information data terminal and converter unit P ₁Output connect, the output of XOR unit A respectively with converter unit P ₂Input and the input of XOR unit C be connected; Another n bit information data terminal respectively with converter unit P ₁Input and the input of XOR unit B be connected; Another input of XOR unit B and converter unit P ₂Output connect; The output of XOR unit B respectively with the input and the converter unit P of described line preface permute unit ₃Input connect; The output of XOR unit C is connected with the input of described line preface permute unit; Converter unit P ₃Output be connected with the input of XOR unit C; P wherein ₂Be permute unit, n is a natural number.

Further, the S box is 8 bit input interfaces and 8 bit output interfaces; Described n value is 4; Described P ₁, P ₃Be 4 to advance 4 conversion that go out.

A kind of S box is characterized in that comprising three XOR unit A, B, C, three converter unit P ₁, P ₂, P ₃, a line preface permute unit, two register L, R, a memory; Converter unit P wherein ₁, P ₂, P ₃Be connected with described memory by base I/O addressI/O respectively; Two inputs of XOR unit A respectively with a n bit information data terminal and converter unit P ₁Output connect, and its output is connected with the input of described register L; Another n bit information data terminal respectively with converter unit P ₁Input and the input of XOR unit B be connected; Another input of XOR unit B and converter unit P ₂Output connect, and its output is connected with the input of described register R; The output of described register R respectively with converter unit P ₃Input and the input of described line preface permute unit be connected; The output of described register L respectively with input and the converter unit P of XOR unit C ₂Input connect; Another input of XOR unit C and converter unit P ₃Output connect, and its output is connected with the input of described line preface permute unit, wherein P ₂Be permute unit, n is a natural number.

Further, the S box is 8 bit input interfaces and 8 bit output interfaces; Described n value is 4; Described P ₁, P ₃Be 4 to advance 4 conversion that go out.

Concrete, be directed to 8 and advance the 8 concrete building methods of S box that go out and be:

A. selected 4 advance the 4 conversion P that go out ₁, P ₂, P ₃, P wherein ₂Be displacement;

B. selected integer m.

For any 8 given bit informations

Information y=S (x) computational process after the conversion of S box is as follows:

1) get x high 4 for x ₁, low 4 is x ₂, x ₁, x ₂As next step input;

2) make x ₂Through P ₁After the conversion with x ₁XOR, result's note is made t ₁, output t ₁, x ₂As next step input;

3) make t ₁Through P ₂After the conversion with x ₂XOR, result's note is made t ₂, output t ₁, t ₂As next step input;

4) make t ₂Through P ₃After the conversion with t ₁XOR, result's note is made t ₃, output t ₃, t ₂As next step input;

5) with t ₃As high 4, t ₂Be t as low 4 the information notes that are connected to become one 8 bit; T ring shift left m position is exported.

Described S box structure is divided into three layers, and 8 bit branches of input are done two parts, successively two parts value is upgraded in three layers.In the step in the end, with two parts value combination back output.

Among the described step a, the conversion of choosing should be by being easy to computer realization, hard-wired basic operation structure.

Among the described step a, P ₂Be displacement, P ₁, P ₃Can be displacement, also can be non-displacement.

Among the described step b, the span of m is the integer between 1 to 7.

Among the described step 2-4, the output of step is upgraded one in the value of two inputs as input before receiving.

Among the described step 2-4, update method is advanced on the numerical value that XOR is updated to needs behind 4 change actions that go out the original numerical value of value replacement that obtains for the numerical value that will need not upgrade through 4.

In the described step 5, with output two parts value combination back output of previous step.

The method for designing of S box has a variety of, and for example the S box of AES is to utilize finite field On multinomial

Structure.

If the standby finite field operations was realized when the S box of this method construct was hard-wired, efficient is very low, so realize with the method for tabling look-up usually, generally needs 500 gate circuits.

And the inventive method structure 8 advance the 8 S boxes that go out, by realizing that the less small-scale conversion multiple layer combination of cost forms, only need about 100 gate circuits to get final product.Use the S box construction algorithm of the inventive method structure, not only can provide good cryptography character, and the hardware implementation efficiency is higher than other method.

Another object of the present invention is a kind of box of S efficiently hardware module, and interface is input of 8 bits and the output of 8 bits.Comprise 3 layers of computing and a line preface permute unit, wherein each layer comprises that one 4 bit is to the conversion of 4 bits and the step-by-step XOR of two 4 bit numbers.Its hardware implementation structure is divided into two kinds:

For mode 1) pure combinational logic circuit implementation, comprise three XOR unit and three lookup unit (promptly 4 bits are to the converter unit of 4 bits) P in the module ₁, P ₂, P ₃With a line preface permute unit＜＜＜m.

Two input XORs of 4 bits are finished in described XOR unit, and the circuit of XOR unit is realized simple, is the basic module of hardware designs, is not the content that the present invention emphasized.

Described lookup unit is finished the computing of tabling look-up of 4 bits, is equivalent to 4 bit index values are retrieved.For example 2 not gates (logical not component) can be realized a kind of tabling look-up to 2 bit informations, are output as when promptly being input as binary system " 00 " " 11 "; Be output as when being input as binary system " 01 " " 10 "; Be output as when being input as binary system " 10 " " 01 "; Be output as when being input as binary system " 11 " " 00 ".This computing of tabling look-up can be expressed as binary form successively:

$S=\left\{\begin{array}{cc}11& 10\\ 01& 00\end{array}\right\}$

Corresponding decimal system form is:

$S=\left\{\begin{array}{cc}3& 2\\ 1& 0\end{array}\right\}$

Tabling look-up for 4 bits can the rest may be inferred.In fact, current hardware circuit design generally adopts hardware description language, as Verilog or VHDL etc., and after only need defining to output, as:

Case(input)

00：out＜＝11；

01：out＜＝10；

10：out＜＝01；

11：out＜＝00；

Endcase

Can further obtain the actual logic structure and obtain P by synthesis tool ₁, P ₂, P ₃Circuit structure.

When hardware was realized, the important indicator whether circuit satisfies temporal constraint was exactly the longest combinational logic path delay of time, is also referred to as critical path.This mode critical path is: x ₂→ P ₁→ XOR → P ₂→ XOR → P ₃→ XOR.The time delay of a common gate is much smaller than the ns level.So, for mode 1) and the realization of pure combinational logic circuit, can guarantee that in the time of a clock cycle all gate circuits upsets finish, thereby finish the whole process of tabling look-up.

For mode 2) the sequence circuit implementation, then need to design finite state machine and finish with a plurality of clock cycle and table look-up.Comprise storage P in the module ₁, P ₂, P ₃The memory of content, the register resources that is used to store results of intermediate calculations (is at least 81 bits, if be the n bit, and can be divided exactly (n, q are natural number) by q, then can be defined as any n/q q bit register during hardware description, in any case divide, must guarantee that when work the n/2 bit register upgrades simultaneously), three XOR unit and register upgrade control logic.The described step of tabling look-up is divided into three clock cycle at least.

If be input as x, high 4 is x ₁, low 4 is x ₂, establishing register resources is 8 bits, is divided into the L of one 4 bit and the R of one 4 bit and defines respectively, the treatment step of then tabling look-up is:

1) establishes P ₁The base address that content exists is P _{1_}Base is with x ₂Offset address is read the content in the appropriate address, with x ₁Carry out being updated among the 4 bit register L behind the XOR;

2) with the output of register L as offset address, choose P ₂(base address is P to middle content corresponding _{2_}Base), after the sense data with x ₂Carry out being updated among the 4 bit register R behind the XOR;

3) with the output of register R as offset address, choose P ₃(base address is P to middle content corresponding _{3_}Base), data of reading and 4 bit register L carry out behind the XOR being spliced into T with the output of R, T is carried out the line preface by left cyclic shift m arrange, output y.

According to dependence of each operation input in the above-mentioned steps, output, mode 2 as can be known) realization need 3 clock cycle at least.Because adopt register-stored intermediate object program between each step, so circuit is realized about 80 of cost, critical path is compared mode 1) shorter, but the time of implementation is much longer relatively, is not suitable for the realization of High Speed occasion.

Compared with prior art, the good effect that has of the present invention is:

This structure utilization simply is easy to hard-wired displacement and non-displacement transformation, the S box that structure has good cryptography character.Simultaneously based on this structure construction a kind of box of S efficiently hardware module, its hardware size is 1/5 of the implementation method of tabling look-up usually.

Description of drawings

Fig. 1, S box structure chart of the present invention;

Fig. 2, implementation 1) electrical block diagram;

Fig. 3, implementation 2) electrical block diagram;

Fig. 4, implementation 2) each step realize electrical block diagram;

(a) mode 2) the realization data path of step 1,

(b) mode 2) the realization data path of step 2,

(c) mode 2) the realization data path of step 3.

Embodiment

Now in conjunction with the accompanying drawings, advancing the 8 displacement S boxes that go out with 8 is example, and the present invention is explained in further detail:

The S box concrete structure that the present invention is based on structural design as shown in Figure 1.S box structure is divided into three layers, and 8 bit branches of input are done two parts, successively two parts value is upgraded in three layers.At last with two parts value combination back output.

Utilize S box structure construction S box of the present invention, at first will select 34 and advance the 4 conversion P that go out ₁, P ₂, P ₃, P wherein ₂Be displacement.3 conversion all adopt the basic computing compound structure of computer to get final product.The second, selected integer value m.

Behind selected above-mentioned parameter, for being input as x, it is as follows then to export the concrete computational process of y=S (X):

x＝x ₁‖x ₂

t ₁＝x ₁⊕P ₁(x ₂)

t ₂＝x ₂⊕P ₂(t ₁)

t ₃＝t ₁⊕P ₃(t ₂)

y＝(t ₃‖t ₂)＜＜＜m

Wherein ‖ represents the attended operation of Bit String, x ₁Be high 4 bits of x, x ₂Low 4 bits for x.

Below, provide a specific embodiment and analyze its hardware implementation efficiency and cryptography character.

1. selection of parameter

Make m=5.

Non-displacement P ₁For input x=(x ₃, x ₂, x ₁, x ₀), output y=(y ₃, y ₂, y ₁, y ₀) algebraic expression be:

y ₃＝x ₃x ₁+x ₁x ₀+x ₃+x ₁+1；

y ₂＝x ₂x ₁+x ₂x ₀+x ₀+x ₂；

y ₁＝x ₃x ₀+x ₂x ₀+x ₀+x ₂；

y ₀＝x ₃x ₁+x ₃x ₂+x ₃+x ₁+1。

Be P ₁=9,15,0,14,15,15,2,10,0,4,0,12,7,5,3,9}.

Displacement P ₂For input x=(x ₃, x ₂, x ₁, x ₀), output y=(y ₃, y ₂, y ₁, y ₀) algebraic expression be:

y ₃＝x ₂x ₁x ₀+x ₃x ₁x ₀+x ₃x ₀+x ₃x ₁+x ₃x ₂+x ₂+x ₁+1；

y ₂＝x ₃x ₂x ₀+x ₃x ₂x ₁+x ₃x ₀+x ₁x ₀+x ₂x ₁+x ₀+x ₁+x ₂；

y ₁＝x ₃x ₂x ₁+x ₁x ₀+x ₂x ₀+x ₃x ₀+x ₃x ₁+x ₃x ₂+x ₁+x ₂+x ₃；

y ₀＝x ₂x ₁x ₀+x ₂x ₁+x ₃x ₁+x ₃x ₀+x ₃x ₂+x ₀+x ₂+x ₃；

Be P ₂=8,13,6,5,7,0,12,4,11,1,14,10,15,3,9,2}.

Non-displacement P ₃For input x=(x ₃, x ₂, x ₁, x ₀), output y=(y ₃, y ₂, y ₁, y ₀) algebraic expression be:

y ₃＝x ₁x ₀+x ₂x ₀+x ₁；

y ₂＝x ₃x ₀+x ₃x ₁+x ₀；

y ₁＝x ₂x ₁+x ₃x ₁+x ₂+1；

y ₀＝x ₂x ₀+x ₃x ₂+x ₃；

Be P ₃=2,6,10,6,0,13,10,15,3,3,13,5,0,9,12,13}.

2.S box form

Behind selected above-mentioned conversion and the m, for all

High 4 with x is row number, and low 4 are row number, can calculate S

Box output and structure table 1:

Table 1, S box output table

	??0	??1	??2	??3	??4	??5	??6	??7	??8	??9	??A	??B	??C	??D	??E	??F
																	??0	??3E	??72	??5B	??47	??CA	??E0	??00	??33	??04	??D1	??54	??98	??09	??B9	??6D	??CB
??1	??7B	??1B	??F9	??32	??AF	??9D	??6A	??A5	??B8	??2D	??FC	??1D	??08	??53	??03	??90
																	??2	??4D	??4E	??84	??99	??E4	??CE	??D9	??91	??DD	??B6	??85	??48	??8B	??29	??6E	??AC
??3	??CD	??C1	??F8	??1E	??73	??43	??69	??C6	??B5	??BD	??FD	??39	??63	??20	??D4	??38
																	??4	??76	??7D	??B2	??A7	??CF	??ED	??57	??C5	??F3	??2C	??BB	??14	??21	??06	??55	??9B
??5	??E3	??EF	??5E	??31	??4F	??7F	??5A	??A4	??0D	??82	??51	??49	??5F	??BA	??58	??1C
																	??6	??4A	??16	??D5	??17	??A8	??92	??24	??1F	??8C	??FF	??D8	??AE	??2E	??01	??D3	??AD
??7	??3B	??4B	??DA	??46	??EB	??C9	??DE	??9A	??8F	??87	??D7	??3A	??80	??6F	??2F	??C8
																	??8	??B1	??B4	??37	??F7	??0A	??22	??13	??28	??7C	??CC	??3C	??89	??C7	??C3	??96	??56
??9	??07	??BF	??7E	??F0	??0B	??2B	??97	??52	??35	??41	??79	??61	??A6	??4C	??10	??FE
																	??A	??BC	??26	??95	??88	??8A	??B0	??A3	??FB	??C0	??18	??94	??F2	??E1	??E5	??E9	??5D
??B	??D0	??DC	??11	??66	??64	??5C	??EC	??59	??42	??75	??12	??F5	??74	??9C	??AA	??23
																	??C	??0E	??86	??AB	??BE	??2A	??02	??E7	??67	??E6	??44	??A2	??6C	??C2	??93	??9F	??F1
??D	??F6	??FA	??36	??D2	??50	??68	??9E	??62	??71	??15	??3D	??D6	??40	??C4	??E2	??0F
																	??E	??8E	??83	??77	??6B	??25	??05	??3F	??0C	??30	??EA	??70	??B7	??A1	??E8	??A9	??65

	??0	??1	??2	??3	??4	??5	??6	??7	??8	??9	??A	??B	??C	??D	??E	??F
																	??F	??8D	??27	??1A	??DB	??81	??B3	??A0	??F4	??45	??7A	??19	??DF	??EE	??78	??34	??60

Numeral adopts 16 systems to represent in the form.

3.S the every cryptography index of box

Every cryptography index of above-mentioned S box is: the difference uniformity is 8, and nonlinearity is 96, and algebraically immunity degree is 2.

For input x=(x ₇, x ₆, x ₅, x ₄, x ₃, x ₂, x ₁, x ₀), output y=(y ₇, y ₆, y ₅, y ₄, y ₃, y ₂, y ₁, y ₀), each component of output about the expression formula of all input components is:

y ₇＝x ₄x ₃x ₂x ₁x ₀+x ₅x ₃x ₂x ₁x ₀+x ₄x ₃x ₂x ₀+x ₄x ₃x ₁x ₀+x ₄x ₃x ₂x ₁+x ₅x ₃x ₁x ₀

+x ₅x ₃x ₂x ₀+x ₅x ₃x ₂x ₁+x ₆x ₂x ₁x ₀+x ₆x ₃x ₂x ₀+x ₆x ₃x ₂x ₁+x ₆x ₄x ₃x ₁

+x ₆x ₄x ₁x ₀+x ₆x ₅x ₁x ₀+x ₆x ₅x ₃x ₁+x ₇x ₂x ₁x ₀+x ₇x ₃x ₁x ₀+x ₇x ₃x ₂x ₀

+x ₇x ₄x ₂x ₀+x ₇x ₄x ₂x ₁+x ₇x ₅x ₂x ₀+x ₇x ₅x ₂x ₁+x ₇x ₆x ₂x ₀+x ₇x ₆x ₃x ₀

+x ₇x ₆x ₃x ₁+x ₇x ₆x ₃x ₂+x ₃x ₂x ₁+x ₄x ₁x ₀+x ₄x ₂x ₁+x ₄x ₃x ₂+x ₄x ₃x ₁

+x ₅x ₃x ₀+x ₅x ₃x ₁+x ₆x ₂x ₁+x ₆x ₃x ₂+x ₆x ₃x ₁+x ₆x ₄x ₃+x ₆x ₄x ₁+x ₆x ₅x ₁

+x ₆x ₅x ₃+x ₇x ₆x ₂+x ₇x ₄x ₂+x ₇x ₃x ₁+x ₇x ₁x ₀+x ₇x ₃x ₂+x ₇x ₄x ₀+x ₇x ₅x ₀

+x ₇x ₅x ₂+x ₇x ₆x ₀+x ₇x ₆x ₁+x ₇x ₆x ₃+x ₇x ₆x ₄+x ₇x ₆x ₅+x ₃x ₂+x ₂x ₁

+x ₃x ₀+x ₄x ₁+x ₄x ₃+x ₅x ₁+x ₅x ₃+x ₅x ₄+x ₆x ₁+x ₆x ₃+x ₆x ₄

+x ₇x ₄+x ₇x ₆+x ₇x ₃+x ₇x ₁+x ₂+x ₇

y ₆＝x ₅x ₃x ₂x ₁x ₀+x ₆x ₃x ₂x ₁x ₀+x ₇x ₃x ₂x ₁x ₀+x ₃x ₂x ₁x ₀+x ₇x ₅x ₂x ₀+x ₇x ₅x ₂x ₁

+x ₅x ₃x ₂x ₀+x ₅x ₃x ₁x ₀+x ₅x ₃x ₂x ₁+x ₇x ₆x ₂x ₀+x ₆x ₂x ₁x ₀+x ₆x ₃x ₂x ₀

+x ₆x ₃x ₂x ₁+x ₆x ₅x ₁x ₀+x ₆x ₅x ₃x ₁+x ₇x ₆x ₃x ₀+x ₂x ₁x ₀+x ₇x ₂x ₀+x ₃x ₁x ₀

+x ₄x ₃x ₀+x ₄x ₁x ₀+x ₄x ₂x ₁+x ₄x ₃x ₁+x ₅x ₁x ₀+x ₇x ₅x ₀+x ₇x ₅x ₂+x ₅x ₂x ₀

+x ₅x ₂x ₁+x ₅x ₃x ₀+x ₆x ₁x ₀+x ₇x ₆x ₀+x ₇x ₆x ₂+x ₆x ₂x ₀+x ₆x ₂x ₁+x ₆x ₃x ₀

+x ₇x ₆x ₅+x ₆x ₅x ₃+x ₆x ₅x ₁+x ₇x ₃x ₁+x ₇x ₃x ₂+x ₇x ₀+x ₇x ₁+x ₁x ₀

+x ₃x ₂+x ₇x ₂+x ₂x ₀+x ₇x ₄+x ₄x ₃+x ₄x ₁+x ₇x ₅+x ₅x ₀+x ₅x ₂

+x ₅x ₄+x ₇x ₆+x ₆x ₀+x ₆x ₂+x ₆x ₄+x ₆x ₅+x ₇x ₃+x ₀+x ₁+x ₂+x ₄+x ₅+x ₆

y ₅＝x ₄x ₃x ₂x ₁x ₀+x ₅x ₃x ₂x ₁x ₀+x ₆x ₃x ₂x ₁x ₀+x ₅x ₂x ₁x ₀+x ₅x ₃x ₁x ₀+x ₅x ₃x ₂x ₀

+x ₅x ₄x ₂x ₀+x ₅x ₄x ₂x ₁+x ₆x ₂x ₁x ₀+x ₆x ₃x ₁x ₀+x ₆x ₅x ₃x ₁+x ₆x ₃x ₂x ₁

+x ₆x ₄x ₃x ₀+x ₆x ₄x ₂x ₀+x ₆x ₅x ₃x ₂+x ₅x ₃x ₁+x ₅x ₄x ₀+x ₄x ₁x ₀+x ₄x ₂x ₀

+x ₄x ₂x ₁+x ₄x ₃x ₀+x ₄x ₃x ₁+x ₅x ₃x ₀+x ₅x ₄x ₂+x ₆x ₅x ₁+x ₆x ₂x ₁+x ₆x ₅x ₃

+x ₆x ₃x ₁+x ₆x ₄x ₂+x ₆x ₄x ₀+x ₆x ₅x ₄+x ₇x ₂x ₁+x ₇x ₃x ₀+x ₇x ₃x ₂+x ₇x ₃x ₁

+x ₃x ₂+x ₅x ₃+x ₃x ₁+x ₅x ₁+x ₂x ₁+x ₂x ₀+x ₄x ₀+x ₄x ₁+x ₄x ₂

+x ₄x ₃+x ₆x ₁+x ₆x ₃+x ₇x ₄+x ₇x ₆+x ₇x ₁+x ₇x ₃+x ₇x ₅+x ₂+x ₅+x ₃+x ₁+1

y ₄＝x ₅x ₃x ₂x ₁x ₀+x ₅x ₄x ₂x ₁x ₀+x ₆x ₃x ₂x ₁x ₀+x ₆x ₄x ₂x ₁x ₀+x ₆x ₄x ₃x ₂x ₀+x ₇x ₃x ₂x ₁x ₀

+x ₇x ₄x ₂x ₁x ₀+x ₇x ₆x ₃x ₁x ₀+x ₇x ₆x ₃x ₂x ₀+x ₄x ₂x ₁x ₀+x ₄x ₃x ₂x ₁+x ₄x ₃x ₁x ₀

+x ₄x ₃x ₂x ₀+x ₅x ₂x ₁x ₀+x ₅x ₃x ₂x ₁+x ₅x ₃x ₁x ₀+x ₅x ₄x ₂x ₁+x ₅x ₄x ₃x ₁

+x ₆x ₄x ₃x ₀+x ₆x ₃x ₂x ₀+x ₆x ₃x ₂x ₁+x ₆x ₄x ₂x ₁+x ₆x ₄x ₃x ₁+x ₆x ₅x ₂x ₁

+x ₆x ₅x ₄x ₂+x ₆x ₅x ₄x ₁+x ₇x ₂x ₁x ₀+x ₇x ₆x ₃x ₀+x ₇x ₃x ₂x ₀+x ₇x ₆x ₃x ₂

+x ₇x ₆x ₃x ₁+x ₇x ₃x ₂x ₁+x ₇x ₄x ₂x ₁+x ₇x ₄x ₃x ₀+x ₇x ₅x ₃x ₂+x ₇x ₅x ₃x ₁

+x ₇x ₆x ₁x ₀+x ₇x ₆x ₄x ₀+x ₃x ₂x ₁+x ₄x ₁x ₀+x ₄x ₂x ₀+x ₄x ₃x ₂+x ₄x ₃x ₁

+x ₅x ₂x ₁+x ₅x ₃x ₀+x ₅x ₄x ₁+x ₅x ₄x ₂+x ₅x ₄x ₃+x ₆x ₄x ₂+x ₆x ₂x ₁+x ₆x ₃x ₂

+x ₆x ₄x ₃+x ₆x ₃x ₁+x ₆x ₄x ₁+x ₆x ₅x ₀+x ₆x ₅x ₁+x ₇x ₆x ₂+x ₇x ₄x ₁+x ₇x ₁x ₀

+x ₇x ₂x ₁+x ₇x ₃x ₂+x ₇x ₆x ₃+x ₇x ₃x ₁+x ₇x ₄x ₀+x ₇x ₄x ₁+x ₇x ₅x ₀+x ₇x ₅x ₂

+x ₇x ₅x ₃+x ₇x ₅x ₄+x ₇x ₆x ₄+x ₃x ₂+x ₅x ₂+x ₁x ₀+x ₃x ₀+x ₃x ₁+x ₄x ₃

+x ₆x ₄+x ₆x ₃+x ₇x ₄+x ₇x ₆+x ₇x ₃+x ₇x ₅+x ₂+x ₅+x ₃+1

y ₃＝x ₄x ₃x ₂x ₁x ₀+x ₅x ₃x ₂x ₁x ₀+x ₅x ₄x ₃x ₂x ₀+x ₅x ₄x ₃x ₁x ₁+x ₅x ₄x ₃x ₁x ₀+x ₆x ₄x ₂x ₁x ₀

+x ₆x ₄x ₃x ₁x ₀+x ₆x ₄x ₃x ₂x ₀+x ₆x ₅x ₃x ₂x ₀+x ₆x ₅x ₃x ₂x ₁+x ₇x ₄x ₂x ₁x ₀+x ₇x ₄x ₃x ₁x ₀

+x ₇x ₅x ₃x ₁x ₀+x ₇x ₆x ₃x ₂x ₀+x ₄x ₂x ₁x ₀+x ₄x ₃x ₂x ₀+x ₅x ₄x ₃x ₂+x ₅x ₄x ₁x ₀

+x ₅x ₄x ₃x ₁+x ₆x ₃x ₂x ₁+x ₆x ₄x ₂x ₁+x ₆x ₄x ₃x ₀+x ₆x ₄x ₃x ₁+x ₆x ₄x ₃x ₂

+x ₆x ₅x ₁x ₀+x ₆x ₅x ₃x ₀+x ₆x ₅x ₃x ₂+x ₆x ₅x ₄x ₀+x ₆x ₅x ₄x ₁+x ₆x ₅x ₄x ₃

+x ₇x ₂x ₁x ₀+x ₇x ₃x ₂x ₀+x ₇x ₃x ₁x ₀+x ₇x ₄x ₁x ₀+x ₇x ₅x ₃x ₁+x ₇x ₅x ₄x ₁

+x ₇x ₅x ₁x ₀+x ₇x ₅x ₄x ₀+x ₇x ₆x ₃x ₁+x ₇x ₆x ₅x ₃+x ₂x ₁x ₀+x ₃x ₁x ₀+x ₃x ₂x ₁

+x ₄x ₁x ₀+x ₄x ₂x ₁+x ₄x ₃x ₀+x ₄x ₃x ₂+x ₅x ₁x ₀+x ₅x ₂x ₀+x ₅x ₂x ₁+x ₅x ₄x ₁

+x ₆x ₁x ₀+x ₆x ₂x ₀+x ₆x ₃x ₀+x ₆x ₃x ₁+x ₆x ₄x ₀+x ₆x ₄x ₁+x ₆x ₅x ₀+x ₆x ₅x ₃

+x ₇x ₂x ₀+x ₇x ₃x ₂+x ₇x ₃x ₀+x ₇x ₄x ₁+x ₇x ₅x ₄+x ₇x ₅x ₃+x ₇x ₆x ₀+x ₇x ₆x ₄

+x ₇x ₆x ₃+x ₃x ₀+x ₇x ₀+x ₆x ₃+x ₂x ₁+x ₃x ₂+x ₄x ₀+x ₄x ₃+x ₅x ₂

+x ₅x ₁+x ₅x ₀+x ₅x ₃+x ₆x ₂+x ₆x ₅+x ₇x ₂+x ₇x ₅+x ₀+x ₆+x ₇+x ₃+1

y ₂＝x ₄x ₃x ₂x ₁x ₀+x ₅x ₃x ₂x ₁x ₀+x ₅x ₄x ₂x ₁x ₀+x ₆x ₄x ₂x ₁x ₀+x ₆x ₄x ₃x ₁x ₀+x ₆x ₅x ₂x ₁x ₀

+x ₆x ₅x ₃x ₁x ₀+x ₇x ₄x ₃x ₁x ₀+x ₇x ₅x ₂x ₁x ₀+x ₇x ₅x ₃x ₂x ₀+x ₇x ₆x ₂x ₁x ₀+x ₇x ₆x ₃x ₁x ₀

+x ₇x ₆x ₃x ₂x ₁+x ₃x ₂x ₁x ₀+x ₄x ₂x ₁x ₀+x ₄x ₃x ₂x ₀+x ₄x ₃x ₁x ₀+x ₅x ₂x ₁x ₀

+x ₅x ₄x ₁x ₀+x ₅x ₄x ₃x ₁+x ₆x ₂x ₁x ₀+x ₆x ₃x ₁x ₀+x ₆x ₄x ₁x ₀+x ₆x ₄x ₂x ₁

+x ₆x ₄x ₃x ₁+x ₆x ₅x ₄x ₁+x ₆x ₅x ₁x ₀+x ₆x ₅x ₂x ₁+x ₆x ₅x ₃x ₂+x ₇x ₂x ₁x ₀

+x ₇x ₃x ₂x ₁+x ₇x ₄x ₃x ₀+x ₇x ₅x ₃x ₀+x ₇x ₅x ₁x ₀+x ₇x ₅x ₄x ₁+x ₇x ₅x ₂x ₁

+x ₇x ₅x ₃x ₁+x ₇x ₆x ₁x ₀+x ₇x ₆x ₂x ₁+x ₇x ₆x ₃x ₁+x ₇x ₆x ₄x ₁+x ₇x ₆x ₅x ₃

+x ₇x ₆x ₅x ₁+x ₇x ₆x ₅x ₂+x ₄x ₃x ₂+x ₄x ₂x ₀+x ₄x ₃x ₀+x ₅x ₁x ₀+x ₅x ₂x ₀

+x ₅x ₃x ₂+x ₅x ₃x ₁+x ₅x ₄x ₂+x ₆x ₁x ₀+x ₆x ₅x ₂+x ₆x ₂x ₀+x ₆x ₃x ₀+x ₆x ₄x ₁

+x ₆x ₄x ₂+x ₆x ₅x ₁+x ₇x ₁x ₀+x ₇x ₃x ₀+x ₇x ₄x ₂+x ₇x ₄x ₃+x ₇x ₅x ₄+x ₇x ₆x ₄

+x ₄x ₀+x ₂x ₀+x ₇x ₂+x ₄x ₁+x ₂x ₁+x ₃x ₁+x ₅x ₀+x ₅x ₁+x ₅x ₂+x ₅x ₄+x ₆x ₅

+x ₆x ₃+x ₆x ₀+x ₆x ₂+x ₇x ₃+x ₇x ₅+x ₇x ₆+x ₀+x ₂+x ₄+x ₇+x ₁+1

y ₁＝x ₅x ₄x ₂x ₁x ₀+x ₅x ₄x ₃x ₂x ₁+x ₇x ₄x ₂x ₁x ₀+x ₇x ₄x ₃x ₂x ₁+x ₇x ₅x ₃x ₂x ₀+x ₇x ₅x ₂x ₁x ₀

+x ₇x ₆x ₃x ₁x ₀+x ₃x ₂x ₁x ₀+x ₅x ₄x ₃x ₁+x ₄x ₃x ₁x ₀+x ₄x ₂x ₁x ₀+x ₄x ₃x ₂x ₀

+x ₄x ₃x ₂x ₁+x ₅x ₃x ₂x ₀+x ₅x ₃x ₂x ₁+x ₅x ₄x ₁x ₀+x ₅x ₄x ₂x ₁+x ₅x ₄x ₃x ₂

+x ₆x ₂x ₁x ₀+x ₆x ₃x ₁x ₀+x ₆x ₃x ₂x ₁+x ₆x ₃x ₂x ₀+x ₆x ₄x ₁x ₀+x ₆x ₄x ₃x ₁

+x ₆x ₄x ₃x ₀+x ₆x ₅x ₃x ₁+x ₆x ₅x ₁x ₀+x ₆x ₅x ₃x ₀+x ₇x ₅x ₃x ₁+x ₇x ₂x ₁x ₀

+x ₇x ₃x ₂x ₀+x ₇x ₄x ₂x ₁+x ₇x ₄x ₃x ₂+x ₇x ₅x ₃x ₀+x ₇x ₅x ₂x ₀+x ₇x ₅x ₄x ₂

+x ₇x ₆x ₁x ₀+x ₇x ₆x ₂x ₀+x ₇x ₆x ₃x ₀+x ₇x ₆x ₃x ₁+x ₇x ₆x ₃x ₂+x ₇x ₆x ₄x ₃

+x ₇x ₆x ₄x ₀+x ₇x ₆x ₅x ₃+x ₇x ₆x ₅x ₀+x ₇x ₅x ₃+x ₃x ₂x ₀+x ₅x ₂x ₁+x ₃x ₂x ₁

+x ₄x ₃x ₁+x ₅x ₄x ₁+x ₄x ₁x ₀+x ₅x ₁x ₀+x ₅x ₄x ₀+x ₅x ₂x ₀+x ₅x ₃x ₂+x ₅x ₄x ₂

+x ₆x ₁x ₀+x ₆x ₂x ₀+x ₆x ₂x ₁+x ₆x ₃x ₂+x ₆x ₄x ₃+x ₆x ₄x ₀+x ₆x ₄x ₁+x ₆x ₅x ₂

+x ₆x ₅x ₁+x ₇x ₃x ₁+x ₇x ₅x ₁+x ₇x ₂x ₀+x ₇x ₅x ₄+x ₇x ₄x ₃+x ₇x ₄x ₂+x ₇x ₆x ₀

+x ₇x ₆x ₁+x ₇x ₆x ₂+x ₇x ₆x ₃+x ₇x ₆x ₄+x ₇x ₆x ₅+x ₇x ₅+x ₅x ₃+x ₇x ₃

+x ₂x ₀+x ₂x ₁+x ₄x ₁+x ₅x ₀+x ₆x ₀+x ₆x ₃+x ₆x ₅+x ₇x ₁+x ₇x ₂

+x ₇x ₄+x ₇x ₆+x ₇+x ₅+x ₃+1

y ₀＝x ₆x ₃x ₂x ₁x ₀+x ₇x ₃x ₂x ₁x ₀+x ₇x ₂x ₁x ₀+x ₄x ₃x ₂x ₀+x ₄x ₃x ₂x ₁+x ₅x ₂x ₁x ₀

+x ₅x ₃x ₁x ₀+x ₅x ₃x ₂x ₀+x ₅x ₄x ₁x ₀+x ₅x ₄x ₂x ₀+x ₅x ₄x ₂x ₁+x ₅x ₄x ₃x ₁

+x ₆x ₂x ₁x ₀+x ₆x ₃x ₁x ₀+x ₆x ₅x ₃x ₂+x ₆x ₃x ₂x ₁+x ₆x ₄x ₂x ₀+x ₆x ₄x ₃x ₀

+x ₆x ₅x ₃x ₁+x ₇x ₂x ₁x ₀+x ₇x ₃x ₁x ₀+x ₇x ₃x ₂x ₁+x ₇x ₄x ₂x ₀+x ₇x ₄x ₃x ₀

+x ₇x ₅x ₃x ₁+x ₇x ₅x ₃x ₂+x ₂x ₁x ₀+x ₃x ₁x ₀+x ₃x ₂x ₀+x ₃x ₂x ₁+x ₄x ₁x ₀

+x ₄x ₃x ₁+x ₄x ₃x ₂+x ₅x ₂x ₀+x ₅x ₂x ₁+x ₅x ₃x ₀+x ₅x ₄x ₁+x ₅x ₄x ₀+x ₅x ₄x ₂

+x ₅x ₄x ₃+x ₆x ₂x ₀+x ₆x ₂x ₁+x ₆x ₃x ₀+x ₆x ₅x ₃+x ₆x ₃x ₁+x ₆x ₄x ₀+x ₆x ₄x ₂

+x ₆x ₅x ₁+x ₆x ₅x ₄+x ₇x ₂x ₀+x ₇x ₅x ₃+x ₇x ₃x ₁+x ₇x ₁x ₀+x ₇x ₃x ₂+x ₇x ₅x ₄

+x ₇x ₄x ₀+x ₇x ₄x ₂+x ₇x ₅x ₁+x ₃x ₁+x ₆x ₁+x ₂x ₁+x ₃x ₀+x ₃x ₂+x ₄x ₃

+x ₄x ₁+x ₅x ₀+x ₅x ₂+x ₆x ₅+x ₅x ₄+x ₆x ₀+x ₆x ₂+x ₆x ₃+x ₇x ₀

+x ₇x ₂+x ₇x ₆+x ₇x ₃+x ₇x ₁+x ₇x ₄+x ₁+x ₄+x ₅+x ₇

Table 2 has provided number and the mathematical expectation that the item of each number of times occurs in each component function of S box.

The item of each number of times occurs in each component function of table 2, S box number and mathematical expectation table

The number of times of item number	??8	??7	??6	??5	??4	??3	??2	??1	??0
										??y 7	??0	??0	??0	??2	??24	??27	??15	??2	??0
??y 6	??0	??0	??0	??3	??13	??24	??19	??6	??0
										??y 5	??0	??0	??0	??3	??12	??20	??17	??4	??1
??y 4	??0	??0	??0	??9	??29	??32	??12	??3	??1
										??y 3	??0	??0	??0	??14	??26	??28	??15	??4	??1
??y 2	??0	??0	??0	??13	??31	??21	??17	??5	??1
										??y 1	??0	??0	??0	??7	??38	??33	??14	??3	??1

The number of times of item number	??8	??7	??6	??5	??4	??3	??2	??1	??0
										??y 0	??0	??0	??0	??2	??24	??32	??20	??4	??0
Desired value	??1/2	??4	??14	??28	??35	??28	??14	??4	??1/2

4.S box hardware implementation efficiency is analyzed

The described a kind of box of S efficiently hardware module can adopt dual mode to realize:

1) pure combinational logic circuit implementation;

2) sequence circuit implementation.

For implementation 1), described interface is input of 8 bits and the output of 8 bits, comprises three XOR unit A, B, C and three lookup unit P in the module ₁, P ₂, P ₃With a line preface permute unit "＜＜＜m ".As shown in Figure 2.

When hardware was realized, the important indicator whether circuit satisfies temporal constraint was exactly the longest combinational logic path delay of time, is also referred to as critical path.This mode critical path is: x ₂→ P ₁→ XOR → P ₂→ XOR → P ₃→ XOR.The time delay of a common gate is much smaller than the ns level.So, for mode 1) and the realization of pure combinational logic circuit, can guarantee that in the time of a clock cycle all gate circuits upsets finish, thereby finish the whole process of tabling look-up.

The time of tabling look-up of this circuit, if output was deposited at once in each clock cycle, then under the 80MHz clock, the realization throughput was 640Mbps (8*80MHz) less than a clock cycle, realized about 100 of area, and the process of tabling look-up is all adopted and is the combinational logic realization.

For mode 2) P ₁, P ₂, P ₃The sequence circuit implementation of content stores in memory then needs to design finite state machine and finishes with a plurality of clock cycle and table look-up.If be input as x, high 4 is x ₁, low 4 is x ₂, the processing procedure of then tabling look-up needs to deposit for three times as shown in Figure 3 at least, needs a clock cycle upgrade relevant register at every turn, and concrete operating circuit is as shown in Figure 4.

As a kind of embodiment, as P ₁, P ₂, P ₃Content leaves in the RAM medium, and then treatment step is as follows:

1) Fig. 4 (a) establishes P ₁The base address that content exists is P _{1_}Base is with x ₂Offset address is read the content in the appropriate address, with x ₁Carry out being updated among the 4 bit register L behind the XOR;

2) Fig. 4 (b) establishes P ₂The base address that content exists is P _{2_}Base is that offset address is read the content in the appropriate address with the content of L, with x ₂Carry out being updated among the 4 bit register R behind the XOR;

3) Fig. 4 (c) as offset address, chooses P with the output of register R ₃(base address is P to middle content corresponding _{3_}Base), carry out being spliced into T with R behind the XOR with 4 bit register L after the sense data, T is carried out the line preface by left cyclic shift m arrange, output y.

Mode 2) realization needs 3 clock cycle at least.Owing to adopt register-stored intermediate object program between each step, so circuit logic partly realizes about 80 of cost (not comprising ram cell), critical path is compared mode 1) shorter, but the time of implementation is much longer relatively, for example under the 80MHz clock, realize that throughput is up to 213Mbps (8 bit * 80MHz/3), adopt sequential logical circuit to realize.

Claims (10)

1. a S box building method the steps include:

1) a selected integer m and three n advance the converter unit that n goes out: P ₁, P ₂, P ₃P wherein ₂Be permute unit, n is a natural number;

2) the 2n bit information x with input is divided into two parts, is designated as x ₁, x ₂, wherein, x ₁High n position, x for input information ₂Low n position for input information;

3) with x ₂Through P ₁After the conversion with x ₁XOR, output result note is made t ₁

4) with t ₁Through P ₂After the conversion with x ₂XOR, output result note is made t ₂

5) with t ₂Through P ₃After the conversion with t ₁XOR, output result note is made t ₃

6) with t ₃As high n position, t ₂Be connected to become the information of a 2n bit as low n position, note is made t;

7) information t ring shift left m position is exported.

2. the method for claim 1, the value that it is characterized in that described integer m is 1～2n-1; Described P ₁, P ₃For n advances the mapping that n goes out; Described n is integer and n 〉=2.

3. method as claimed in claim 1 or 2 is characterized in that adopting a line preface permute unit that information t ring shift left m position is exported.

4. method as claimed in claim 1 or 2 is characterized in that described step 3)～5) in conversion adopt combinational logic circuit to realize; Wherein the critical path of combinational logic circuit is: x ₂→ P ₁→ XOR → P ₂→ XOR → P ₃→ XOR.

5. method as claimed in claim 1 or 2 is characterized in that described step 3)～5) in conversion adopt sequence circuit to realize.

6. method as claimed in claim 5 is characterized in that the method for described employing sequence circuit realization conversion is:

1) with P ₁, P ₂, P ₃In information be stored in respectively in the memory;

2) according to P ₁The base address, with x ₂Read the P that stores in the described memory for offset address ₁Information is with itself and x ₁Carry out being updated among the n bit register L behind the XOR;

3) according to P ₂The base address, as offset address, read the P that stores in the described register with the output of this register L ₂Information is with itself and x ₂Carry out being updated among the n bit register R behind the XOR;

4) according to P ₃The base address, as offset address, read the P that stores in the described register with the output of this register R ₃Information is carried out XOR with itself and this register L.

7. a S box is characterized in that comprising three XOR unit A, B, C, three converter unit P ₁, P ₂, P ₃, a line preface permute unit; Wherein two inputs of XOR unit A respectively with a n bit information data terminal and converter unit P ₁Output connect, the output of XOR unit A respectively with converter unit P ₂Input and the input of XOR unit C be connected; Another n bit information data terminal respectively with converter unit P ₁Input and the input of XOR unit B be connected; Another input of XOR unit B and converter unit P ₂Output connect; The output of XOR unit B respectively with the input and the converter unit P of described line preface permute unit ₃Input connect; The output of XOR unit C is connected with the input of described line preface permute unit; Converter unit P ₃Output be connected with the input of XOR unit C; P wherein ₂Be permute unit, n is a natural number.

8. S box as claimed in claim 7 is characterized in that the S box is 8 bit input interfaces and 8 bit output interfaces; Described n value is 4; Described P ₁, P ₃Be 4 to advance 4 conversion that go out.

9. a S box is characterized in that comprising three XOR unit A, B, C, three converter unit P ₁, P ₂, P ₃, a line preface permute unit, two register L, R, a memory; Converter unit P wherein ₁, P ₂, P ₃Be connected with described memory by base I/O addressI/O respectively; Two inputs of XOR unit A respectively with a n bit information data terminal and converter unit P ₁Output connect, and its output is connected with the input of described register L; Another n bit information data terminal respectively with converter unit P ₁Input and the input of XOR unit B be connected; Another input of XOR unit B and converter unit P ₂Output connect, and its output is connected with the input of described register R; The output of described register R respectively with converter unit P ₃Input and the input of described line preface permute unit be connected; The output of described register L respectively with input and the converter unit P of XOR unit C ₂Input connect; Another input of XOR unit C and converter unit P ₃Output connect, and its output is connected with the input of described line preface permute unit, wherein P ₂Be permute unit, n is integer and n 〉=2.

10. S box as claimed in claim 9 is characterized in that the S box is 8 bit input interfaces and 8 bit output interfaces; Described n value is 4; Described P ₁, P ₃Be 4 to advance 4 conversion that go out.

Images