CN101826958A - Multi-architecture chaotic signal generator - Google Patents
Multi-architecture chaotic signal generator Download PDFInfo
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- CN101826958A CN101826958A CN 201010151257 CN201010151257A CN101826958A CN 101826958 A CN101826958 A CN 101826958A CN 201010151257 CN201010151257 CN 201010151257 CN 201010151257 A CN201010151257 A CN 201010151257A CN 101826958 A CN101826958 A CN 101826958A
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Abstract
The invention relates to a multi-architecture chaotic signal generator which comprises a first access, a second access, a third access and a fourth access. The multi-architecture chaotic signal generator is realized by loading different controllers on the basis of a three-dimensional chaotic Lv system, wherein the controllers are divided into two major parts: constant controllers and state feedback controllers, and different controllers are combined with the chaotic Lv system organically by transition of two groups of dialing switches to obtain output signals of a single-scroll chaotic attractor, a double-scroll chaotic attractor, a four-scroll chaotic attractor and a special hyperchaotic attractor. The invention adopts a pure analog circuit method to design a uniform hardware circuit formed by multiple chaotic systems. Through comparison, the output result of the circuit is basically the same with a numerical simulation result, which shows that by using the circuit realization method, chaotic signal outputs with different characteristics can be obtained by simple transition of switches according to actual application needs in the field of information engineering.
Description
Technical field
The present invention relates to a kind of chaos signal generator, particularly a kind of multi-architecture chaotic signal generator.
Background technology
Chaos phenomenon is the universal phenomenon of occurring in nature, and Changes in weather is exactly a typical chaotic motion.A famous statement of chaos phenomenon is exactly " buterfly effect ": butterfly of South America fans wing, will cause a hurricane in the Florida.Chaos phenomenon refers to a kind of definite but uncertain motion state in nonlinear science.Its external manifestation is very similar with pure random motion, and is promptly all unpredictable.But different with random motion is that chaotic motion determines that on dynamics its unpredictability is the unsteadiness that derives from motion.In sensitiveness, no matter how little disturbance also can make system thoroughly depart from original evolution direction after for a long time to chaos system to the change of infinitesimal initial value and perturbation also tool in other words.
Over nearly 40 years, " chaos " obtained deep research as the non-linear phenomena of a complexity.The chaotic signal that side circuit produces has in many applications such as signal encryption, chaotic radar, secure communication comparatively widely and uses.2003, Liu Wenbo and Chen Guanrong have found new three-dimensional self-governing chaos system a--Int.J.Bifur.Chaos of liu system [relevant references: W.liu and G.Chen.Anew chaotic system and its generation[J] continuously, vol.13, no.1, pp.261-267, Jan.2003], contain three quadratic nonlinearity items in its system's Algebraic Equation set.2004, people such as Lv Jinhu and Chen Guanrong has promoted the Liu system, on the basis of this system, a new chaos system has been proposed--the Int.J.Bifur.Chaos of augmentation L ü system [relevant references: J.L ü, G.Chen, and D.Cheng.A new chaotic system and beyond:thegeneralized Lorenz-like system[J], vol.14, no.5, pp.1507-1537, May 2004].There are three parametric variables in the Liu system, and augmentation L ü system has only two parametric variables, can produce attractor and following attractor on two scroll chaotics of two coexistences.
Numerical simulation is the result show, loads the constant control item of different numerical value in augmentation L ü system respectively, can realize conversion, the connection and the conversion of chaos attractor up and down of chaos attractor up and down of single two scroll chaotic attractors; And load different linear condition feedback controllers on the different expression formula of Algebraic Equation set, can obtain four scroll chaotic attractors and multiple unusual hyperchaos attractor.And how to adopt hardware experiments circuit of pure Analog Circuit Design, to verify above-mentioned numerical simulation result, be the technical barrier of this area.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of multi-architecture chaotic signal generator, to verify the constant control item that in augmentation L ü system, loads different numerical value respectively, can realize conversion, the connection and the conversion of chaos attractor up and down of chaos attractor up and down of single two scroll chaotic attractors; And load different linear condition feedback controllers on the different expression formula of Algebraic Equation set, can obtain four scroll chaotic attractors and multiple unusual hyperchaos attractor.
For solving the problems of the technologies described above, multi-architecture chaotic signal generator provided by the invention comprises: the first path A, alternate path B, the 3rd path C and four-way road D.
The first path A comprises: first of series connection simulate product device M1, first anti-phase input scale operation device U1A and the first integral arithmetic unit U1B successively.
Alternate path B comprises: second of series connection simulate product device M2, the second anti-phase input scale operation device U2A, second integral arithmetic unit U2B and the first inverter U3A successively; The signal output part of the first inverter U3A links to each other with first signal input part of the described first simulation product device M1, and the signal output part of the first inverter U3A is through the inverting input of the 5th resistance R 5 serial connections second anti-phase input scale operation device U2A; The signal output part of first integral arithmetic unit U1B links to each other with first signal input part of the second simulation product device M2, and the signal output part of first integral arithmetic unit U1B is through the inverting input of first resistance R, 1 serial connection, the first anti-phase input scale operation device U1A.
The 3rd path C comprises: the 3rd of series connection the simulate product device M3, the 3rd anti-phase input scale operation device U3B, third integral arithmetic unit U4A and the second inverter U4B successively.
The signal output part of the second inverter U4B links to each other with first signal input part of described the 3rd simulation product device M3, and the signal output part of the second inverter U4B is through the inverting input of the 13 resistance R 13 serial connections the 3rd anti-phase input scale operation device U3B; The signal output part of first integral arithmetic unit U1B links to each other with first signal input part of the 3rd simulation product device M3, and the signal output part of described second integral arithmetic unit U2B links to each other with the secondary signal input of the 3rd simulation product device M3; The signal output part of third integral arithmetic unit U4A links to each other with the secondary signal input of the described first simulation product device M1 and the second simulation product device M2 simultaneously.
Four-way road D comprises: Chuan Lian the 4th anti-phase input scale operation device U5A, the 4th integrator computing unit U5B and the 3rd inverter U6A successively.
The 15V DC power supply links to each other with the inverting input α of the first anti-phase input scale operation device U1A behind first switch S, 1 serial connection, the first current-limiting resistance R101 again, the 15V DC power supply links to each other with the inverting input α of the first anti-phase input scale operation device U1A after second switch S2 is connected in series the second current-limiting resistance R102 again, the 15V DC power supply links to each other with the inverting input β of the second anti-phase input scale operation device U2A behind the 3rd switch S 3 serial connections the 3rd current-limiting resistance R103 again, and the 15V DC power supply links to each other with the inverting input γ of the 3rd anti-phase input scale operation device U3B behind the 4th switch S 4 serial connections the 4th current-limiting resistance R104 again.-15V DC power supply links to each other with the inverting input γ of the 3rd anti-phase input scale operation device U3B behind described the 4th current-limiting resistance R104 of the 5th switch S 5 serial connections again.
The signal output part of the 3rd inverter U6A links to each other with the inverting input β of the second anti-phase input scale operation device U2A behind the 9th switch S 9 serial connections the 5th current-limiting resistance R105 again, and the signal output part of the 3rd inverter U6A links to each other with the inverting input β of the second anti-phase input scale operation device U2A behind the tenth switch S 10 serial connections the 6th current-limiting resistance R106 again; The signal output part of third integral arithmetic unit U4A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 11 switch S 11 serial connections the 7th current-limiting resistance R107 again, the signal output part of third integral arithmetic unit U4A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 14 switch S 14 serial connections the tenth current-limiting resistance R110 again, and the signal output part of third integral arithmetic unit U4A closes through sixteenmo and links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A after S16 is connected in series the 12 current-limiting resistance R112 again; The 4th integrator computing unit U5B closes through twelvemo and links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A after S12 is connected in series the 8th current-limiting resistance R108 again; The signal output part of the first inverter U3A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 13 switch S 13 serial connections the 9th current-limiting resistance R109 again, and the signal output part of the first inverter U3A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 15 switch S 15 serial connections the 11 current-limiting resistance R111 again.
When all switches all disconnected, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A was an attractor on two scrollworks.
When closed described first switch S 1 only, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A is the not full two scroll chaotic attractors of left wing.
When closed described second switch S2 only, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A is single scroll chaotic attractor.
When closed described the 3rd switch S 3 only, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A is the chaos attractor of four scrollworks, also promptly connects attractor up and down.
When closed described the 4th switch S 4 only, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A is an attractor on two scroll chaotics.
When closed described the 4th switch S 5 only, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A is an attractor under two scroll chaotics.
When only closed described the 9th switch S the 9, the 11 switch S 11 and twelvemo were closed S12, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A was four unusual scrollwork attractors.
When only closed described the tenth switch S the 10, the 13 switch S 13 and the 14 switch S 14, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A is the hyperchaos attractor.
When only closed described the tenth switch S the 10, the 15 switch S 15 and sixteenmo closed S16, the figure of rail mutually of first integral arithmetic unit U1B and the output of third integral arithmetic unit U4A was attractor paracycle.
The technique effect that the present invention has: the chaos signal generator of (1) many body system of the present invention is based on three-dimensional chaos L ü system, and different controllers realize by loading, controller is divided into constant controller and state feedback controller two large divisions, conversion by two groups of DIP switches, organically different controllers and chaos L ü system are combined, realized the output signal of single scrollwork, two scrollwork, four scroll chaotic attractors and unusual hyperchaos attractor.(2) the present invention adopts pure analog circuit method to design a unified hardware circuit that multiple chaos system is formed, circuit is exported the result and the numerical simulation result makes comparisons, can find both basically identicals, this illustrates above circuit implementation method, can be according to practical application needs in the information engineering field, switch by simple switch, just can obtain the chaotic signal output of different qualities.
Description of drawings
For the easier quilt of content of the present invention is clearly understood, below the specific embodiment and in conjunction with the accompanying drawings of basis, the present invention is further detailed explanation, wherein
Fig. 1 is the circuit theory diagrams of the multi-architecture chaotic signal generator among the embodiment;
Fig. 2 is the menu that the pairing multi-architecture chaotic signal generator of the different on off states of two groups of DIP switches set among the embodiment is realized;
Fig. 3 (a) is as fixing a=-10, and b=-4 selects u=v=m=0, when establishing initial value for (x0, y0,0), the phase rail figure of attractor on two scroll chaotics of the three-dimensional chaos augmentation L ü system of numerical simulation generation.
Fig. 3 (b) works as fixedly a=-10, and b=-4 selects v=m=0, during u=5, and the phase rail figure of attractor on two scroll chaotics that the three-dimensional chaos augmentation L ü system of numerical simulation produces;
Fig. 3 (c) works as fixedly a=-10, and b=-4 selects v=m=0, during u=18, and the phase rail figure of attractor on single scrollwork that the three-dimensional chaos augmentation L ü system of numerical simulation produces;
Fig. 3 (d) is as fixing a=-10, b=-4 selects v=m=0, and during v=5, the three-dimensional chaos augmentation L ü system of numerical simulation has realized the seamless link of attractor and following attractor on the chaos, has promptly produced the phase rail figure of four scrollwork attractors;
Fig. 3 (e) works as fixedly a=-10, and b=-4 selects v=u=0, during m=1, and the phase rail figure of attractor on two scrollworks that the three-dimensional chaos augmentation L ü system of numerical simulation produces;
Fig. 3 (f) works as fixedly a=-10, and b=-4 selects v=u=0, during m=-1, and the phase rail figure of attractor under two scrollworks that the three-dimensional chaos augmentation L ü system of numerical simulation produces;
Fig. 4 (a) works as fixedly a=-10, and b=-4 selects g (w)=c (w-z), h (w)=w, and during c=-5, the phase rail figure of the unusual four-dimension four scrollwork attractors that the four dimensional chaos system of numerical simulation produces.
Fig. 4 (b) works as fixedly a=-10, and b=-4 selects g (w)=c (z-y), h (w)=10w, and during c=-8, the unusual hyperchaos that the four dimensional chaos system of numerical simulation produces is inhaled the phase rail figure of attractor.
Fig. 4 (c) is as fixing a=-10, and b=-4 selects g (w)=c (z-y), h (w)=10w, during c=-16, the generation of the four dimensional chaos system of numerical simulation unusual paracycle attractor phase rail figure.
Fig. 5 (a) is for when the position of DIP switches set all is in off-state, and the figure of rail mutually that can observe the output of operational amplifier U1B and U4A is an attractor on two scrollworks.
Fig. 5 (b) is as closed S1, inserts 4.4M Ω resistance, adds a constant controller u ' promptly for first path of circuit system, and the figure of rail mutually that can be observed the output of operational amplifier U1B and U4A is the two scroll chaotic attractors that left wing is not full;
Fig. 5 (c) is as closed S2, inserts 1.2M Ω resistance, promptly adds another constant controller u ' to system equation, can be observed the single scroll chaotic attractor shown in Fig. 4 (c).
Fig. 5 (d) is as closed S3, inserts 4.4M Ω resistance, adds a constant controller v ' promptly for second path of circuit system, after attractor is connected about can be observed, has been transformed into the chaos attractor of one four scrollwork.
Fig. 5 (e) is as closed S4, add the 15V direct voltage through 22M Ω resistance access circuit, add a constant controller m ' promptly for the 3rd path of circuit system, the figure of rail mutually that can be observed the output of operational amplifier U1B and U4A is an attractor on two scroll chaotics;
Fig. 5 (f) is as closed S5, adds-15V direct voltage process 22M Ω resistance access circuit, can be observed attractor under two scroll chaotics.
Fig. 6 (a) is for when S9, S11, S12 all are in closure state, D path among Fig. 1 is connected with A, B, three paths of C, constituted a four-dimensional system circuit, promptly inserted a state feedback controller, the figure of rail mutually of operational amplifier U1B and U4A output is four unusual scroll chaotic attractors.
Fig. 6 (b) is when S10, S13, S14 all are in closure state, has inserted another state feedback controller, is the hyperchaos attractor at the figure of rail mutually of operational amplifier U1B and U4A output.
Fig. 6 (c) is when S10, S15, S16 all are in closure state, is four-dimensional paracycle of attractor at the figure of rail mutually of the output of operational amplifier U1B and U4A.
Embodiment
The present invention is described in detail below in conjunction with drawings and Examples:
Three-dimensional chaos augmentation L ü system is a continuous self-governing chaos system of three-dimensional, and its system's Algebraic Equation set contains three quadratic nonlinearity items.After loading three constant control items in the basic augmentation L ü system, this three-dimensional chaos augmentation L ü system (hereinafter to be referred as: system (1)) can unify to be described as:
Wherein a and b are real constants, and u, v, m are respectively the constant controller that is carried on the different expression formulas.Fixing a=-10, b=-4 selects u, v, m works as u as changing, and when v, m got different numerical value, the chaos attractor that system (1) produces had following four kinds of situations:
(1) selects u=v=m=0.If initial value is (x
0, y
0, 0), system (1) can produce attractor on the two scroll chaotics, respectively shown in Fig. 3 (a).
(2) select v=m=0.When u=5, system (1) has produced attractor on the not full two scrollworks of left wing, shown in Fig. 3 (b); When u=18, system (1) has then produced attractor on the single scrollwork, shown in Fig. 3 (c).System (1) has taken place to be transformed into the not full two scrollwork attractors of a wing by full two scrollwork attractors under constant u control, is transformed into single scrollwork attractor then.
(3) select u=m=0, v=5.System (1) has realized the seamless link of attractor and following attractor on the chaos, shown in Fig. 3 (d).
(4) select u=v=0.When m=1 or m=-1, system (1) has produced attractor or following attractor on the two scrollworks respectively, as Fig. 3 (e) with (f).Be that system (1) attractor on having taken place by chaos under the constant m control has been transformed into attractor under the chaos.
By in basic augmentation L ü system, increasing the one-dimensional linear state controller, feed back in the original system and go, can realize a new four dimensional chaos system (hereinafter to be referred as: system (2)), its algebraic equation contains three quadratic nonlinearity items, can unify to be described as:
A wherein, b is a real constant, and g (w) is for being loaded into the linear controller in the augmentation L ü system, and h (w) is the state feedback item.Fixing a=-10, b=-4, select different linear controllers and state feedback item can obtain four unusual scroll chaotic attractors, hyperchaos attractor and paracycle attractor.
When selecting g (w)=c (w-z), state feedback item h (w)=w.System when c=-5 (2) can produce a unusual four-dimension four scroll chaotic attractors, and its projection on the x-z plane is shown in Fig. 4 (a).
When selecting g (w)=c (z-y), state feedback item h (w)=10w.System when c=-8 (2) can produce a unusual hyperchaos attractor, and its projection on the x-w plane is respectively shown in Fig. 4 (b).
When selecting linear controller g (w)=c (z-y), state feedback item h (w)=10w.System when c=-16 (2) can produce unusual attractor paracycle, shown in Fig. 4 (c).
In side circuit manufacturing process, need consider that the allowable voltage scope of general analog multiplier is ± 10V, the allowable voltage scope of operational amplifier is ± 13.5V; Simultaneously also will be with respect to too small input signal, the error that its multiplying output produces can be bigger.Therefore, need guarantee the hardware experiments circuit working in a suitable dynamic range, its signal amplitude both should not surpass the saturation voltage of active device, also should not too smallly make the output signal distortion.
Simulation result under the top different situations, the dynamic range of chaos attractor be ± 40.Therefore, need do the linear transformation of proper ratio, just can make corresponding circuit obtain comparatively satisfied output result top system state variables.Here, the state variable of system (1) is done following linear transformation:
(x，y，z)→(15x，15y，15z)，(3)
Numerical value to each constant control item in the system (1) will have following variation simultaneously:
(u，v，m)→(u/15，v/?15，m/15)，(4)
The differential equation group of system after the conversion (1) just become following form (hereinafter to be referred as: system (5)):
Here, u '=u/15, v '=v/15, m '=m/15.State variable to system (2) is done following linear transformation:
(x，y，z，w)→(15x，15y，15z，15w)，(6)
The differential equation group of system after the conversion (2) just become following form (hereinafter to be referred as: system (7)):
In addition, for observation experiment output waveform more effectively, need make linear session change of scale: t → 10 τ to the time constant factor of the integrator in the hardware circuit.
After above various actual fabrication considerations, a hardware circuit principle figure who exports based on the different chaotic signals of having of augmentation L ü system as shown in Figure 1.
Comprise as the multi-architecture chaotic signal generator among Fig. 1: the first path A, alternate path B, the 3rd path C and four-way road D.
The first path A comprises: first of series connection simulate product device M1, first anti-phase input scale operation device U1A and the first integral arithmetic unit U1B successively; That is: the signal output part of the first simulation product device M1 links to each other with the input signal end of the first anti-phase input scale operation device U1A, and the signal output part of the first anti-phase input scale operation device U1A links to each other with the signal input part of first integral arithmetic unit U1B;
Alternate path B comprises: second of series connection simulate product device M2, the second anti-phase input scale operation device U2A, second integral arithmetic unit U2B and the first inverter U3A successively; That is: the signal output part of the second simulation product device M2 links to each other with the signal input part of the second anti-phase input scale operation device U2A, the signal output part of the second anti-phase input scale operation device U2A links to each other with the signal input part of second integral arithmetic unit U2B, and the signal output part of second integral arithmetic unit U2B links to each other with the signal input part of the first inverter U3A.The signal output part of the first inverter U3A links to each other with first signal input part of the described first simulation product device M1, and the signal output part of the first inverter U3A is through the inverting input of the 5th resistance R 5 serial connections second anti-phase input scale operation device U2A; The signal output part of first integral arithmetic unit U1B links to each other with first signal input part of the second simulation product device M2, and the signal output part of first integral arithmetic unit U1B is through the inverting input of first resistance R, 1 serial connection, the first anti-phase input scale operation device U1A.
The 3rd path C comprises: the 3rd of series connection the simulate product device M3, the 3rd anti-phase input scale operation device U3B, third integral arithmetic unit U4A and the second inverter U4B successively; That is: the signal output part of the 3rd simulation product device M3 links to each other with the signal input part of the 3rd anti-phase input scale operation device U3B, the signal output part of the 3rd anti-phase input scale operation device U3B links to each other with the signal input part of third integral arithmetic unit U4A, and the signal output part of third integral arithmetic unit U4A links to each other with the signal input part of the second inverter U4B.
The signal output part of the second inverter U4B links to each other with first signal input part of described the 3rd simulation product device M3, and the signal output part of the second inverter U4B is through the inverting input of the 13 resistance R 13 serial connections the 3rd anti-phase input scale operation device U3B; The signal output part of first integral arithmetic unit U1B links to each other with first signal input part of the 3rd simulation product device M3, and the signal output part of described second integral arithmetic unit U2B links to each other with the secondary signal input of the 3rd simulation product device M3; The signal output part of third integral arithmetic unit U4A links to each other with the secondary signal input of the described first simulation product device M1 and the second simulation product device M2 simultaneously.
Four-way road D comprises: Chuan Lian the 4th anti-phase input scale operation device U5A, the 4th integrator computing unit U5B and the 3rd inverter U6A successively.
The 15V DC power supply links to each other with the inverting input α of the first anti-phase input scale operation device U1A behind first switch S, the 1 serial connection first current-limiting resistance R101 (4.4M Ω) again, the 15V DC power supply links to each other with the inverting input α of the first anti-phase input scale operation device U1A after second switch S2 is connected in series the second current-limiting resistance R102 (1.2M Ω) again, the 15V DC power supply links to each other with the inverting input β of the second anti-phase input scale operation device U2A behind the 3rd switch S 3 serial connection the 3rd current-limiting resistance R103 (4.4M Ω) again, and the 15V DC power supply links to each other with the inverting input γ of the 3rd anti-phase input scale operation device U3B behind the 4th switch S 4 serial connection the 4th current-limiting resistance R104 (22M Ω) again.
-15V DC power supply links to each other with the inverting input γ of the 3rd anti-phase input scale operation device U3B behind described the 4th current-limiting resistance R104 of the 5th switch S 5 serial connections again.
The signal output part of the 3rd inverter U6A links to each other with the inverting input β of the second anti-phase input scale operation device U2A behind the 9th switch S 9 serial connection the 5th current-limiting resistance R105 (100K Ω) again, and the signal output part of the 3rd inverter U6A links to each other with the inverting input β of the second anti-phase input scale operation device U2A behind the tenth switch S 10 serial connection the 6th current-limiting resistance R106 (10K Ω) again.
The signal output part of third integral arithmetic unit U4A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 11 switch S 11 serial connection the 7th current-limiting resistance R107 (47K Ω) again; The signal output part of third integral arithmetic unit U4A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 14 switch S 14 serial connection the tenth current-limiting resistance R110 (12K Ω) again, and the signal output part of third integral arithmetic unit U4A closes through sixteenmo and links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A after S16 is connected in series the 12 current-limiting resistance R112 (6K Ω) again.
The 4th integrator computing unit U5B closes through twelvemo and links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A after S12 is connected in series the 8th current-limiting resistance R108 (47K Ω) again.
The signal output part of the first inverter U3A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 13 switch S 13 serial connection the 9th current-limiting resistance R109 (12K Ω) again, and the signal output part of the first inverter U3A links to each other with the inverting input δ of the 4th anti-phase input scale operation device U5A behind the 15 switch S 15 serial connection the 11 current-limiting resistance R111 (6K Ω) again.
The model of 11 operational amplifiers is LM324 in Fig. 1 circuit, and the model of 3 simulation product devices is MPY634KP, and each resistance adopts precision resistor, and each electric capacity adopts monolithic capacitor, and part 13 bit switches in right side adopt two 8 DIP switches set to realize.Four paths with A, B, C, D mark among Fig. 1 correspond respectively to the equation of system (5) and (7) (D path the 4th equation corresponding to system (7)), and each path generally is that proportional device, integrator and inverter three-stage operational amplifier circuit constitute (not having inverter circuit in the A path).Come the parameter a and the b value of change system (5) and (7) by the resistance value of regulating R1, R5, R11.
Pass through the change in location of the DIP switches set of a group octet in Fig. 1 circuit, the direct voltage of different numerical value can be input on the reverse input end of different operational amplifiers, realize various controls circuit system; The change in location of the DIP switches set by another group octet can be loaded into different linear controllers and state feedback item on the circuit system, realizes the conversion between the different four dimensional chaos circuit.The function that the pairing circuit of the different on off states of two groups of DIP switches set is realized is seen Fig. 2.
Corresponding to the result that numerical simulation provides when the different situation, will correspondingly provide the output phase rail figure of different experimental circuits here.Here, experiment output observer is the Tek digital storage oscilloscope.
When the position of DIP switches set all was in off-state, the figure of rail mutually of output that can observe operational amplifier U1B and U4A was attractor on two scrollworks shown in Fig. 5 (a).
As closed S1, insert 4.4M Ω resistance, add a constant controller u ' promptly for first path of circuit system, the figure of rail mutually of output that can be observed operational amplifier U1B and U4A is the two scroll chaotic attractors that left wing is not full shown in Fig. 5 (b); As closed S2, insert 1.2M Ω resistance, promptly add another constant controller u ' to system equation, can be observed the two scroll chaotic attractors of list shown in Fig. 5 (c).
As closed S3, insert 4.4M Ω resistance, add a constant controller v ' promptly for second path of circuit system, after attractor is connected about can be observed, be transformed into the chaos attractor of one four scrollwork, shown in Fig. 5 (d).
As closed S4, add the 15V direct voltage through 22M Ω resistance access circuit, add a constant controller m ' promptly for the 3rd path of circuit system, can be observed the figure of rail mutually of the output of operational amplifier U1B and U4A, shown in Fig. 5 (e), be attractor on two scroll chaotics; As closed S5, add-15V direct voltage process 22M Ω resistance access circuit, can be observed attractor under two scroll chaotics, shown in Fig. 5 (f).
When S9, S11, S12 all are in closure state, D path among Fig. 3 is connected with A, B, three paths of C, constituted a four-dimensional system circuit, promptly inserted a state feedback controller, the figure of rail mutually of operational amplifier U1B and U4A output is four unusual scroll chaotic attractors shown in Fig. 6 (a).
When S10, S13, S14 all are in closure state, inserted another state feedback controller, Fig. 6 (b) shows the figure of rail mutually at operational amplifier U1B and U4A output, is the hyperchaos attractor.
When S10, S15, S16 all were in closure state, the figure of rail mutually that Fig. 6 (c) shows at the output of operational amplifier U1B and U4A was four-dimension attractor paracycle.
Obviously, the foregoing description only is for example of the present invention clearly is described, and is not to be qualification to embodiments of the present invention.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here need not also can't give exhaustive to all execution modes.And these belong to conspicuous variation or the change that spirit of the present invention extended out and still are among protection scope of the present invention.
Claims (10)
1. multi-architecture chaotic signal generator is characterized in that comprising: first path (A), alternate path (B), the 3rd path (C) and four-way road (D);
First path (A) comprising: first of series connection simulate product device (M1), the first anti-phase input scale operation device (U1A) and first integral arithmetic unit (U1B) successively;
Alternate path (B) comprising: second of series connection simulate product device (M2), the second anti-phase input scale operation device (U2A), second integral arithmetic unit (U2B) and first inverter (U3A) successively; The signal output part of first inverter (U3A) links to each other with first signal input part of the described first simulation product device (M1), and the signal output part of first inverter (U3A) is through the inverting input of the 5th resistance (R5) the serial connection second anti-phase input scale operation device (U2A); The signal output part of first integral arithmetic unit (U1B) links to each other with first signal input part of the second simulation product device (M2), and the signal output part of first integral arithmetic unit (U1B) is through the inverting input of first resistance (R1) serial connection, the first anti-phase input scale operation device (U1A);
The 3rd path (C) comprising: the 3rd of series connection the simulate product device (M3), the 3rd anti-phase input scale operation device (U3B), third integral arithmetic unit (U4A) and second inverter (U4B) successively;
The signal output part of second inverter (U4B) links to each other with first signal input part of described the 3rd simulation product device (M3), and the signal output part of second inverter (U4B) is through the inverting input of the 13 resistance (R13) serial connection the 3rd anti-phase input scale operation device (U3B); The signal output part of first integral arithmetic unit (U1B) links to each other with first signal input part of the 3rd simulation product device (M3), and the signal output part of described second integral arithmetic unit (U2B) links to each other with the secondary signal input of the 3rd simulation product device (M3); The signal output part of third integral arithmetic unit (U4A) links to each other with the secondary signal input of the described first simulation product device (M1) and the second simulation product device (M2) simultaneously;
(D) comprising on the four-way road: Chuan Lian the 4th anti-phase input scale operation device (U5A), the 4th integrator computing unit (U5B) and the 3rd inverter (U6A) successively;
The 15V DC power supply links to each other with the inverting input (α) of the first anti-phase input scale operation device (U1A) behind first switch (S1) serial connection first current-limiting resistance (R101) again, the 15V DC power supply links to each other with the inverting input (α) of the first anti-phase input scale operation device (U1A) behind second switch (S2) serial connection second current-limiting resistance (R102) again, the 15V DC power supply links to each other with the inverting input (β) of the second anti-phase input scale operation device (U2A) behind the 3rd switch (S3) serial connection the 3rd current-limiting resistance (R103) again, and the 15V DC power supply links to each other with the inverting input (γ) of the 3rd anti-phase input scale operation device (U3B) behind the 4th switch (S4) serial connection the 4th current-limiting resistance (R104) again;
-15V DC power supply links to each other with the inverting input (γ) of the 3rd anti-phase input scale operation device (U3B) behind the 5th switch (S5) described the 4th current-limiting resistance of serial connection (R104) again;
The signal output part of the 3rd inverter (U6A) links to each other with the inverting input (β) of the second anti-phase input scale operation device (U2A) behind the 9th switch (S9) serial connection the 5th current-limiting resistance (R105) again, and the signal output part of the 3rd inverter (U6A) links to each other with the inverting input (β) of the second anti-phase input scale operation device (U2A) behind the tenth switch (S10) serial connection the 6th current-limiting resistance (R106) again;
The signal output part of third integral arithmetic unit (U4A) links to each other with the inverting input (δ) of the 4th anti-phase input scale operation device (U5A) behind the 11 switch (S11) serial connection the 7th current-limiting resistance (R107) again, the signal output part of third integral arithmetic unit (U4A) links to each other with the inverting input (δ) of the 4th anti-phase input scale operation device (U5A) behind the 14 switch (S14) serial connection the tenth current-limiting resistance (R110) again, and the signal output part of third integral arithmetic unit (U4A) links to each other with the inverting input (δ) of the 4th anti-phase input scale operation device (U5A) after sixteenmo closes (S16) serial connection the 12 current-limiting resistance (R112) again;
The 4th integrator computing unit (U5B) links to each other with the inverting input (δ) of the 4th anti-phase input scale operation device (U5A) after twelvemo is closed (S12) serial connection the 8th current-limiting resistance (R108) again;
The signal output part of first inverter (U3A) links to each other with the inverting input (δ) of the 4th anti-phase input scale operation device (U5A) behind the 13 switch (S13) serial connection the 9th current-limiting resistance (R109) again, and the signal output part of first inverter (U3A) links to each other with the inverting input (δ) of the 4th anti-phase input scale operation device (U5A) behind the 15 switch (S15) serial connection the 11 current-limiting resistance (R111) again.
2. multi-architecture chaotic signal generator according to claim 1 is characterized in that: when all switches all disconnected, the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) was an attractor on two scrollworks.
3. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when closed described first switch (S1) only, the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) is the not full two scroll chaotic attractors of left wing.
4. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when closed described second switch (S2) only, the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) is single scroll chaotic attractor.
5. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when closed described the 3rd switch (S3) only, the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) is the chaos attractor of four scrollworks, also promptly connects attractor up and down.
6. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when closed described the 4th switch (S4) only, the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) is an attractor on two scroll chaotics.
7. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when closed described the 4th switch (S5) only, the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) is an attractor under two scroll chaotics.
8. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when only closed described the 9th switch (S9), the 11 switch (S11) and twelvemo were closed (S12), the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) was four unusual scrollwork attractors.
9. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when closed described the tenth switch (S10) only, the 13 switch (S 13) and the 14 switch (S14), the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) is the hyperchaos attractor.
10. multi-architecture chaotic signal generator according to claim 1, it is characterized in that: when only closed described the tenth switch (S10), the 15 switch (S15) and sixteenmo closed (S16), the figure of rail mutually of the first integral arithmetic unit (U1B) and the output of third integral arithmetic unit (U4A) was attractor paracycle.
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