CN101789845B

CN101789845B - Method and circuit applying SFEC to realize bit width transformation of bus in OTN (optical transport network)

Info

Publication number: CN101789845B
Application number: CN 201010111571
Authority: CN
Inventors: 朱齐雄
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd; Wuhan Fisilink Microelectronics Technology Co Ltd
Priority date: 2010-02-22
Filing date: 2010-02-22
Publication date: 2013-01-16
Anticipated expiration: 2030-02-22
Also published as: CN101789845A

Abstract

The invention discloses a method and a circuit applying SFEC to realize bit width transformation of a bus in an OTN (optical transport network). The steps of the method are as follows: S10, OTN-frame data input by a 64-bit system bus is encoded according to the encoding rule of an outer code RS (1,023 and 1,007) and is stored in a buffer memory M which is composed of 8 RAMs, and the size of each RAM is 1,530*10; S20, 10 RS (1,023 and 1,007) encoded data is respectively read at a time from the 8 RAMs of the buffer memory M, encoded according to the encoding rule of an inner code BCH (2,040 and 1,952) and then stored in a buffer memory N which is also composed of 8 RAMs, and the size of each RAM is 244*64; S30, 64 BCH (2,040 and 1,952) encoded data is sequentially output from the 8 RAMs of the buffer memory N to the 64-bit system bus. By controlling the read-write operation of the buffer memories, the invention realizes the bus transformation from 64-bit width to 80-bit width required by the outer code and the bus transformation from 80-bit width to 64-bit width. The realization of the method is simple and effective, and the operability is strong.

Description

Bus bit wide conversion implementation method and circuit in the optical transfer network of application SFEC

Technical field

The present invention relates to the encoding and decoding technique of OTN optical transfer network, be specifically related to use bus bit wide conversion implementation method and circuit in the optical transfer network of SFEC.

Background technology

Along with the arrival of network times, people grow with each passing day to the demand of information.Because optical communication technique has huge bandwidth resources and relative cheap manufacturing cost, therefore, at present OTN is as the basis of broadband communication network of future generation, and as the important support platform of the information transmission technology, will play a very important role in Future Information society.

Along with the day by day of people to information requirement, greatly expanded telecommunications network to the demand space of optical communication system and stimulated the develop rapidly of optical communication system self-technique.The capacity that further increases transmission system is exactly the use of optical wavelength-division multiplex (WDM) technology with the preferably way that reduces every bit transfer cost.In recent years, along with extensive application and the development of wavelength-division multiplex technique, the total speed of communication on a pair of optical fiber is being marched to the order of magnitude of bits per second too.

Because the development of the communication technology and continuing to bring out of new business, the particularly swift and violent emergence of IP operation, causing the global information amount to be the order of magnitude increases, communication service is the broadband services of representative by the single telephone service of tradition to High Speed IP data and multimedia, and bandwidth and the capacity of communication network proposed more and more higher requirement.Yet many unfavorable factors of Networks of Fiber Communications have affected its transmission performance.Along with optical communication system is constantly used in optical fiber telecommunications system to the technology such as application, dense wave division multipurpose (DWDM) system, all optical network and optical cross connect (OXC) of the development of ultrahigh speed, vast capacity and extra long distance direction and synchronous digital hierarchy (SDH) architecture, erbium-doped fiber amplifier (EDFA), device performance constantly improves in addition, system's speed has obtained great-jump-forward ground and has promoted, and power system capacity has obtained expansion at double.But the validity and reliability of transmission is the conflict body, in the time of higher single channel speed, less channel spacing and farther without electronic relay transmission range, dispersion, chromatic dispersion gradient, polarization mode dispersion, nonlinear effect (four wave mixing, Cross-phase Modulation etc.), amplified spontaneous emission noise accumulation, receiver performance etc. also become the principal element of restriction system performance.The expansion of optical communication capacity also can cause a series of such as crosstalking between each road light signal, signal synchronously, regularly, the problem recovered.These problems can cause the generation of error code in the optical communication system, reduce the reliability of communication.The reduction of communication reliability has finally restricted again the raising of communication quality, multiplexed large-scale application and reduction of communication equipment cost etc., thereby can hinder the development of optical communication system.

And forward error correction (FEC) coding techniques is to make every effort to correct mistake as much as possible with minimum redundancy, finds the balance point an of the best between speed and reliability.So employing FEC technology reduces the error rate in the optical communication system, then can not strengthen too much system cost, but can improve significantly the bit error rate performance of optical communication system, thereby improve the reliability of system communication.

The FEC technology is used in high speed optical communication system, has to prolong the optical signal transmission distance, reduces the advantages such as optical sender transmitting power.The FEC technology is applied in the over distance Fiber Optical Submarine Cable System, and along with the development of terrestrial optical communication system, the raising of single channel speed, the application of FEC technology will become one of preferred version that reduces equipment requirement tolerance limit and system group network cost.Theory and practice has proved that all the FEC technology is to improve a kind of effective ways of long-distance large Capacity Optical communication system performance.In optical communication system, utilize the FEC technology that system can be allowed in the optical communication line and larger circuit bit error rate (BER) is arranged (greater than 10 before the FEC decoding ^-12), the application of FEC is allowed to relax to the requirement of the optical parameter of system with lower cost and is made up long-distance large Capacity Optical communication system.

But along with growing to longer distance, larger capacity and more speed of optical communication system, the transmission effects in the optical fiber (such as dispersion, PMD and nonlinear effect etc.) can have a strong impact on the further raising of transmission rate and transmission range.Thereby be necessary that research can better the SFEC pattern, make it obtain higher net coding gain and better error-correcting performance.

Recently, ITU-T has carried out the research of FEC code for optical communication system, some suggestions (as G.975, G.709 and G.975.1 waiting) of being correlated with have therewith been proposed in succession, wherein G.975.1 ITU_T has defined pattern and the coding rule of 8 kinds of SFEC in (forward error correction in the high speed DWDM undersea system), I.4 kind SFEC pattern wherein is: outer code RS (1023,1007)+and the cascaded code of ISN BCH (2040,1952), wherein to patrol magnificent territory be GF (2 to the gal of outer code ¹⁰), the symbol that this means each outer code RS (1023,1007) is 10bit, therefore the bus bit wide of entrance need to be transformed into 10 multiple when carrying out the outer code coding, and ISN BCH (2040,1952) code is one and is defined in gal and patrols magnificent territory GF (2 ¹¹) on binary code, 64 BCH (2040,1952) code word is arranged in each OTN frame, need thus being transformed into take the 64 bus bit wides as multiple take the 10 bus bit wides as multiple behind the outer code coding.

But to this bus conversion specific implementation of enhanced FEC pattern I.4 and not mentioned, these brought difficulty in the design all can for the hardware designs personnel during G.975.1 ITU_T advised.

In sum, existing I.4 super FEC has following deficiency aspect the hardware circuit realization:

I.4SFEC the Hardware Implementation of pattern and coding rule and not mentioned concrete coding and decoding has just simply been described during 1, G.975.1 ITU_T advises;

The bus conversion of during 2, G.975.1 ITU_T advises the different gal that needs in I.4SFEC being patrolled on the magnificent territory was not mentioned.

Summary of the invention

Technical problem to be solved by this invention is to solve the OTN system that uses the SFEC coding rule to have the unmatched problem of bus bit wide.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention provides bus bit wide conversion implementation method in the optical transfer network of a kind of SFEC of application, may further comprise the steps:

S10, will be from the data of the OTN frame of 64 system buss input by outer code RS (1023,1007) deposit buffer memory M in behind the coding rule coding, buffer memory M is made of 8 block RAMs, and the size of every block RAM is respectively 1530 * 10, and the read-write clock of buffer memory M is identical with the system bus clock frequency;

S20, at every turn from 8 block RAMs of buffer memory M, read respectively 10 RS (1023,1007) coded data is also pressed ISN BCH (2040,1952) deposit buffer memory N in behind the coding rule coding, buffer memory N is made of 8 block RAMs, the size of every block RAM is respectively 244 * 64, and the read-write clock of buffer memory N is identical with the system bus clock frequency;

S30, output 64 BCH (2040,1952) coded data to 64 system bus from 8 block RAMs of buffer memory N successively.

In the said method, the RAM among the buffer memory M is dual port RAM, and 765 is divided into two districts of A1 and B1 as the boundary take the address, when reading the A1 district, writes the B1 district, when reading the B1 district, writes the A1 district.

Step S10 may further comprise the steps:

S101, according to SFEC outer code RS (1023,1007) coding rule is divided into RS (0)-RS (15) 16 group addresss with each address ram of buffer memory M, wherein RS (0)-RS (14) is with RS (1023,1007) shortening code RS (781,765) be coding rule, RS (15) is coding rule with RS (778,762);

S102, to write into successively every block RAM of buffer memory M from frame OTN data of 64 system bus inputs, the rule that writes is, FEC overhead byte in the OTN frame does not write buffer memory M, one frame OTN data according to bit transmission order take 10 * 765 for unit respectively correspondence write in the address location of RS in every block RAM (0)-RS (15) correspondence, wherein RS (0)-RS (7) distinguishes corresponding A 1 district, RS (8)-RS (15) is corresponding B1 district respectively, when beginning to write the 0# address of RAM, send the B1 district coding index signal of a buffer memory M, when beginning to write the 765# address, send the A1 district coding index signal of a buffer memory M.

Buffer memory N is made of 8 identical RAM, and this RAM is dual port RAM, and 122 is divided into A2 district and B2 district as the boundary take the address, when reading the A2 district, writes the B2 district, when reading the B2 district, writes the A2 district.

Described step S20 may further comprise the steps:

S201, when detecting the A1 district coding index signal of buffer memory M, buffer memory N once reads the 80bit data among the A1 district RAM among the buffer memory M, when index signal was encoded in the B1 district that detects buffer memory M, buffer memory N once read the 80bit data in the B1 district among the buffer memory M;

S202, the 80bit data of buffer memory M output are assigned among the RAM among the buffer memory N successively, wherein RS (0)-RS (7) distinguishes corresponding A 2 districts, RS (8)-RS (15) is corresponding B2 district respectively, when beginning to write the 0# address of RAM, send the A2 district coding index signal of a buffer memory N, when beginning to write the 122# address, send the B2 district coding index signal of a buffer memory N;

The data of different RS address behind two outer code codings of every block RAM buffer memory among S203, the buffer memory N; Be specially the coded data among 1#RAM buffer memory outer code RS (0) and the RS (8), 1# and the 9#RS code coded data of 2#RAM buffer memory outer code RS code word, 2# and the 10#RS code coded data of 3#RAM buffer memory outer code RS code word, 3# and the 11#RS code coded data of 4#RAM buffer memory outer code RS code word, 4# and the 12#RS code coded data of 5#RAM buffer memory outer code RS code word, 5# and the 13#RS code coded data of 6#RAM buffer memory outer code RS code word, 6# and the 14#RS code coded data of 7#RAM buffer memory outer code RS code word, 7# and the 15#RS code coded data of 8#RAM buffer memory outer code RS code word;

S204, in detecting buffer memory N during A2 district coding index signal, begin read operation from the 122# address of the 1#RAM in the B2 district of buffer memory N, run through successively the B2 district of 1#RAM after, the B2 district of then reading 2#RAM is until the B2 district data of 1-8#RAM all run through; When detecting the B2 district coding index signal of buffer memory N, begin read operation from the 0# address of the 1#RAM in the A2 district of buffer memory N, run through successively the A2 district of 1#RAM after, the A2 district of then reading 2#RAM is until the A2 district data of 1-8#RAM all run through.

The present invention also provides bus bit wide translation circuit in the optical transfer network of a kind of SFEC of application, comprises buffer memory M and buffer memory N, and buffer memory M is made of 8 block RAMs, and the size of every block RAM is respectively 1530 * 10; Buffer memory N is made of 8 block RAMs, and the size of every block RAM is respectively 244 * 64.

In the foregoing circuit, the RAM among the buffer memory M is dual port RAM, and this RAM 765 is divided into two districts of A1 and B1 as the boundary take the address, when reading the A1 district, writes the B1 district, when reading the B1 district, writes the A1 district.

RAM among the buffer memory N is dual port RAM, and 122 is divided into A2 district and B2 district as the boundary take the address, when reading the A2 district, writes the B2 district, when reading the B2 district, writes the A2 district.

The present invention, by the control to the read-write operation of buffer memory, finished input 64 bit wides to the bus conversion of desired 80 bit wides of outer code and from the bus of 80 bit wides again to the conversion of 64 bit wide buses, simple and effective, the strong operability of implementation method.

Description of drawings

Fig. 1 is OTN frame structure schematic diagram;

Fig. 2 is the SFEC structural representation;

Fig. 3 is SFEC outer code RS (1023,1007) coding schematic diagram;

Fig. 4 is SFEC ISN BCH (2040,1952) coding schematic diagram;

Fig. 5 is schematic flow sheet of the present invention;

Fig. 6 is buffer memory M structural representation of the present invention;

Fig. 7 is buffer memory N structural representation of the present invention.

Embodiment

The invention provides implementation method and the circuit of bus bit wide conversion in the optical transfer network of a kind of SFEC of application, be used for realizing that 64 input bus bit wides of OTN frame are to SFEC outer code RS (1023,1007) coding is processed the conversion process of 80 required bus bit wides and through SFEC outer code RS (1023,1007) coding is processed rear 80 bus bit wides to ISN BCH (2040,1952) conversion process of required 64 the bus bit wides of coding, to adapt to SFEC outer code RS (1023,1007) coding is processed and the processing of SFEC ISN BCH (2040,1952) coding.

For understanding better the present invention, below the coding principle of paper SFEC outer code RS (1023,1007) and ISN BCH (2040,1952).

G.709, the OTN frame structure of regulation as shown in Figure 1 during ITU_T advised, this frame structure is 4 row, the block byte structure of 4080 row, wherein front 16 is classified the overhead area of OTN as, be payload area between 17～3824 row, be forward error correction FEC overhead area between 3825～4080 row, therefore, a complete OTN frame bit number is: 4 * 4080 * 8=130560bits, ITU_T is G.975.1 middle to stipulate that the bit number that will transmit at first in the complete OTN frame is otu[0], and then otu[1], numbering is to the last bit otu[130559 that transmits always], so far a complete OTN frame number is complete.

ITU_T G.795.1 in I.4 super forward error correction SFEC structure as shown in Figure 2, this enhanced FEC is formed by outer code and ISN cascade, outer code is that gal is patrolled magnificent territory GF (2 ¹⁰) on RS (1023,1007), ISN is that gal is patrolled magnificent territory GF (2 ¹¹) on BCH (2040,1952), wherein RS (1023,1007) is the multi-system BCH code, BCH (2040,1952) is binary BCH codes.

Fig. 3 is outer code RS (1023,1007) coding rule, according to the OTN frame structure, total bit number of removing in the OTN frame behind the FEC overhead byte is: 4 * 3824 * 8=122368bits, these bits are divided into 16 groups, use RS (1023 for front 15 groups, 1007) the shortening code RS (781 of code, 765) encode the shortening code RS (781 of this 15 RS (1023,1007) code, 765) number consecutively is RS (0)-RS (14), last shortening code RS (778,762) that organizes the 16th group of usefulness RS (1023,1007) code encodes and is numbered RS (15); The bit that transmits at first in the OTN frame is numbered odu[0], that and then transmits is numbered odu[1], the like, until numbering is to odu[122367], this moment, a complete OTN frame number finished, and did not comprise the FEC overhead byte among the OTN in the numbering.Thus, whole outer code coding flow process is as follows: odu[0]-odu[9] this 10 bit consists of first RS (781,765) first symbol of code RS (0), odu[10]-odu[19] consist of second symbol of RS (0), the like, odu[7640]-odu[76499] consist of the 765th symbol of RS (0), so far the message part coding of RS (0) code is complete, and then produce the effect bit of RS (0) code of 160 bits, a whole complete RS (0) code coding is complete, ITU_T G.975.1 in regulation with odu[0]-odu[7649] number consecutively that this 7650 bit is corresponding is the otu[0 of OTN frame]-otu[7649], 160 bit effect positions of RS (0) code in turn be numbered otu[7650]-otu[7809], so just all code elements of the RS that first is complete (0) yard have been mapped to the relevant position of OTN frame accordingly.

According to this rule, successively RS (1)-RS (15) is encoded, at the namely RS (778 of RS (15) that encodes, 762) last information code element symbol is namely during the 762nd symbol, because OTN frame this moment remaining odu[122360 only]-odu[122367] these 8 bits encode, so when the 762nd symbol of coding RS (15), with odu[122360]-odu[122367] these 8 bits place the low level of the 762nd symbol, a high position adds 0 of 2bit, the symbol that gathers into like this 10 bits participates in the 160 bit effect positions calculating of the back of RS (15) code, but when transmitting, this 2bit does not transmit, only be used for the calculating of effect position, in the zone that is mapped to the OTN frame that also can be not corresponding, after finishing dealing with like this, can then carry out the generation of the last 160 bit effect positions of RS (15), can finish thus SFEC outer code RS (1023,1007) to the coding of a complete OTN frame.

At SFEC outer code RS (1023,1007) also need to carry out ISN BCH (2040 on the basis of coding, 1952) coding, after OTN frame outer code coding is finished, the total bit number that produces is: do not comprise all effect bit number 2560=124928 of total bit number 122368+ of the OTN frame of FEC overhead byte, the corresponding otu[0 that is numbered]-otu[124927];

ISN BCH (2040,1952) coding rule as shown in Figure 4, G.975.1, the 124928bit during ITU_T advises behind the regulation outer code coding is divided into 64 groups, every group of 1952bit, consist of thus 64 ISN BCH (2040,1952) information code element part, 64 ISN BCH (2040,1952) number consecutively is BCH[0], BCH[1] until BCH[63], BCH code information code element allocation rule is as follows: otu[0] be first code element of BCH (0) code, otu[1] be first code element of BCH (1) code, the like, otu[63] be first code element of BCH (63) code, otu[64] be second code element of BCH (0) code, be cycled to repeat, 124928bit just is mapped to 64 BCH (2040 like this, 1952) the information code element position of code, each BCH (2040,1952) code can produce the effect code element of 88bit according to information code element separately, the effect symbol mapped allocation rule of these 64 groups of 88bit is as follows: BCH[0] first effect symbol allocation be otu[124928], BCH[1] first effect symbol allocation be otu[124929], the like, BCH[63] first effect symbol allocation be otu[124991], BCH[0] second effect symbol allocation be otu[124992], be cycled to repeat until all effect symbol allocation are complete, all bits of a complete OTN frame have been produced like this after the outer code of process SFEC and the ISN coding, 124928+64 * 88=130560bit, the bit transmission among Fig. 4 is sequentially for from left to right, from top to bottom.

Method provided by the invention is that the RAM with some realizes that SFEC coding input bus 64 bit wides are to SFEC outer code RS (1023 during ITU_T G.975.1,1007) desired take 10 80 bus bit wides as multiple, again with the RAM of some realize behind the outer code coding take 10 as 80 bus bit wides of multiple to the bus bit wide as 64 conversion, to satisfy ISN BCH (2040,1952) coding requirement, as shown in Figure 5, specifically may further comprise the steps:

The implementation of step S10 as shown in Figure 6, buffer memory M is made of 8 block RAMs, every block RAM (dual port RAM, the A mouth is write, the B mouth is read) the degree of depth and width be respectively 1530 * 10, just all data of removing in the complete OTN frame behind the FEC overhead byte can be write in 8 block RAMs, every block RAM 765 is the boundary take the address, be divided into A1 district (address space 0-764) and B1 district (address space 765-1529), when writing the A1 district, attend school the B1 district, when writing the B1 district, attend school the A1 district, MSB (MostSignificant Bit in the 64bit data of input, highest significant position) be bit 0, LSB (Lest Significant Bit, least significant bit) is bit 63.

The write method of buffer memory M is: within first clock cycle of OTN frame initial time, 60bit in the 64 bit wide data of input is write into 0# address among the 1#-6#RAM, and deposit the 4bit data, wherein the 9:0 of the 64bit data of input is write in the 0# address of 1#RAM, the 19:10 of the 64bit data of input is write in the 0# address of 2#RAM, the 29:20 of the 64bit data of input is write in the 0# address of 3#RAM, the 39:30 of the 64bit data of input is write in the 0# address of 4#RAM, the 49:40 of the 64bit data of input is write in the 0# address of 5#RAM, the 59:50 of the 64bit data of input is write in the 0# address of 6#RAM, the data of the 0# address among the 1#-6#RAM are write within a clock cycle simultaneously, the next clock cycle, write simultaneously 7#, the 0# address of 8#RAM, write simultaneously the 1# address of 1#-4#RAM, wherein the data of writing of 7#RAM are: the 5:0bit data correspondence of this clock cycle is put [9:4] among the 10bit into, the 4bit data [63:60] of depositing of the upper clock cycle are put [3:0] among the 10bit into, the 15:6 of the 64bit data of the 0# address handwritten copy clock cycle input of 8#RAM, the 25:16 of the 64bit data of the 1# address handwritten copy clock cycle input of 1#RAM, the 35:26 of the 64bit data of the 1# address handwritten copy clock cycle input of 2#RAM, the 45:36 of the 64bit data of the 1# address handwritten copy clock cycle input of 3#RAM, the 55:46 of the 64bit data of the 1# address handwritten copy clock cycle input of 4#RAM, deposit simultaneously the data of [63:56] bit of this clock cycle, according to this rule of writing, finish writing of whole OTN frame data.According to the rule of the filling 2bit " 0 " of the 762nd symbol among the RS (15) of outer code RS (1023,1007) coding, when writing data in the 1529# address of 5#RAM, [9:8] bit of data bit fills 2 bit " 0 ".

When writing direction and begin to write the 0# address of RAM, send the high level B1 district RS coding index signal of a clock width, can from the B1 district of buffer memory, begin the RS coding by reading out data with indication RS encoder, when writing direction and begin to write the 765# address, send the high level A1 district RS coding index signal of another clock width, can from the A1 district of buffer memory, begin the RS coding by reading out data with indication RS encoder, through behind such write method, first start element symbol of RS (0)-RS (7) has dropped on respectively on the 8 different block RAMs in the A1 district of buffer memory M, be specially: first symbol of RS (0) has dropped on 1#RAM, first symbol of RS (1) has dropped on 6#RAM, first symbol of RS (2) has dropped on 3#RAM, first symbol of RS (3) has dropped on 8#RAM, first symbol of RS (4) has dropped on 5#RAM, first symbol of RS (5) has dropped on 2#RAM, first symbol of RS (6) has dropped on 7#RAM, first symbol of RS (7) has dropped on 4#RAM, so just is that the symbol of the RS (0) that reads simultaneously A1 district in 8 block RAMs in the clock cycle-RS (7) has been created condition.In like manner first start element symbol of RS (8)-RS (15) has dropped on respectively on 8 different in the B1 district of the buffer memory M block RAMs.The symbol that so also is the RS (8) that reads simultaneously B1 district in 8 block RAMs in the clock cycle-RS (15) has been created condition.

Buffer memory M reads method: when being checked through the high level A1 district RS coding index signal of a clock width, begin to read the A1 district of 8 block RAMs among the buffer memory M, each clock cycle is read the symbol of the different middle same sequence number of address acquisition RS (0)-RS (7) in 8 block RAMs, each clock cycle can both obtain each the RS code 10bit 80bit data altogether among RS (0)-RS (7) like this, for example, when A1 district RS coding index signal when being high:

First clock cycle read method is as follows:

The 0# address of 1#RAM obtains RS (0) the 1st number 10bit of unit data;

The 478# address of 2#RAM; Obtain RS (5) the 1st number 10bit of unit data;

The 191# address of 3#RAM; Obtain RS (2) the 1st number 10bit of unit data;

The 669# address of 4#RAM; Obtain RS (7) the 1st number 10bit of unit data;

The 382# address of 5#RAM; Obtain RS (4) the 1st number 10bit of unit data;

The 95# address of 6#RAM; Obtain the 10bi t of RS (1) the 1st number unit data;

The 573# address of 7#RAM; Obtain RS (6) the 1st number 10bit of unit data;

The 286# address of 8#RAM; Obtain RS (3) the 1st number 10bit of unit data;

Second clock cycle read method is as follows:

The 0# address of 2#RAM obtains RS (0) the 2nd number 10bit of unit data;

The 478# address of 3#RAM; Obtain RS (5) the 2nd number 10bit of unit data;

The 191# address of 4#RAM; Obtain RS (2) the 2nd number 10bit of unit data;

The 669# address of 5#RAM; Obtain RS (7) the 2nd number 10bit of unit data;

The 382# address of 6#RAM; Obtain RS (4) the 2nd number 10bit of unit data;

The 95# address of 7#RAM; Obtain RS (1) the 2nd number 10bit of unit data;

The 573# address of 8#RAM; Obtain RS (6) the 2nd number 10bit of unit data;

The 287# address of 1#RAM; Obtain RS (3) the 2nd number 10bit of unit data;

Read down to obtain each clock cycle the data of 8 different RS codes according to this rule, thereby the parallel encoding that can carry out 8 different RS codes is processed, when although each RS code coding produces effect bit, can stop reading out data from buffer memory M, but because 80＞64, can not cause the packing phenomenon of data in buffer memory M.

When being checked through the high level B1 district RS coding index signal of a clock width, begin to read the B1 district of 8 block RAMs among the buffer memory M, each clock cycle is read the symbol of the different middle same sequence number of address acquisition RS (8)-RS (15) in 8 block RAMs, each clock cycle can both obtain each the RS code 10bit 80bit data altogether among RS (8)-RS (15) like this, for example, when B1 district RS coding index signal when being high:

First clock cycle read method is as follows:

The 765# address of 1#RAM obtains RS (8) the 1st number 10bit of unit data;

The 1243# address of 2#RAM; Obtain RS (13) the 1st number 10bit of unit data;

The 956# address of 3#RAM; Obtain RS (10) the 1st number 10bit of unit data;

The 1434# address of 4#RAM; Obtain RS (15) the 1st number 10bit of unit data;

The 1147# address of 5#RAM; Obtain RS (12) the 1st number 10bit of unit data;

The 860# address of 6#RAM; Obtain RS (9) the 1st number 10bit of unit data;

The 1338# address of 7#RAM; Obtain RS (14) the 1st number 10bit of unit data;

The 1051# address of 8#RAM; Obtain RS (11) the 1st number 10bit of unit data;

Second clock cycle read method is as follows:

The 765# address of 2#RAM obtains RS (8) the 2nd number 10bit of unit data;

The 1243# address of 3#RAM; Obtain RS (13) the 2nd number 10bit of unit data;

The 956# address of 4#RAM; Obtain RS (10) the 2nd number 10bit of unit data;

The 1434# address of 5#RAM; Obtain RS (15) the 2nd number 10bit of unit data;

The 1147# address of 6#RAM; Obtain RS (12) the 2nd number 10bit of unit data;

The 860# address of 7#RAM; Obtain RS (9) the 2nd number 10bit of unit data;

The 1338# address of 8#RAM; Obtain RS (14) the 2nd number 10bit of unit data;

The 1052# address of 1#RAM; Obtain RS (11) the 2nd number 10bit of unit data;

Rule reading out data successively namely can be finished input data bus 64 bit wides thus to the conversion process of output bus 80 bit wides according to this.

Step S20 implementation as shown in Figure 7, buffer memory N is made of 8 block RAMs, every block RAM (dual port RAM, the A mouth is write, the B mouth is read) the degree of depth and width be respectively 244 * 64, just can be with the OTN frame through outer code RS (1023,1007) data after processing are write in 8 block RAMs, and every block RAM 122 is the boundary take the address, is divided into A2 district (address space 0-121) and B2 district (address space 122-243), when writing the A2 district, attend school the B2 district, when writing the B2 district, attend school the A2 district, the A2 district correspondence of 1-8#RAM is loaded respectively the data of RS (0)-RS (7), and the B2 district correspondence of 1-8#RAM is loaded respectively RS (8)-RS (15) data.

Buffer memory N write method is: when being checked through the high level A2 district RS coding index signal of a clock width, can receive simultaneously RS (0), RS (1), RS (2), RS (3), RS (4), RS (5), 1# code element behind RS (6) and RS (7) coding amounts to 8 * 10=80bit, distribute the 10bit data of RS (0) to the A2 district of 1#RAM, distribute the 10bit data of RS (1) to the A2 district of 2#RAM, distribute the 10bit data of RS (2) to the A2 district of 3#RAM, distribute the 10bit data of RS (3) to the A2 district of 4#RAM, distribute the 10bit data of RS (4) to the A2 district of 5#RAM, distribute the 10bit data of RS (5) to the A2 district of 6#RAM, distribute the 10bit data of RS (6) to the A2 district of 7#RAM, distribute the 10bit data of RS (7) to the A2 district of 8#RAM, although the bus bit wide is the data of 80bit like this, but after over-allocation, each clock cycle of every block RAM only has the 10bit data, because the width of every block RAM is 64bit, the A2 mouth data that therefore must wait until each RAM gather together enough and just carry out the action of writing of 1-8#RAM after the 64bit data.Wherein the 0# address 64bit data of 2#RAM must wait until that RS (0) just can write the operation of this address after writing in the A2 district of 1#RAM since low 2 of mouthful data of writing of the 0# address of 2#RAM to come from A2 interval that RS (0) code data writes 1#RAM remaining afterwards.Also there is this method of writing processing in other 1# among the 3#-8#RAM.

Every block RAM 64bit data method that gathers together enough is as follows, and take 1# and 2#RAM as example (the 3#-8#RAM method of operation is the same), MSB is bit 0 in 8 10bitRS code datas of input, and LSB is bit 9:

In the 1st clock cycle of the 1#10bit code element of receiving RS (0)-RS (7), at first piece together mouthful data of writing of RAM:

The A2 mouth of 1#RAM is write the 1#10bit code element of data [9:0]=RS (0);

The A2 mouth of 2#RAM is write the 1#10bit code element of data [11:2]=RS (1);

In the 2nd clock cycle of the 2#10bit code element of receiving RS (0)-RS (7), deposit RAM to write mouthful data as follows:

The A2 mouth of 1#RAM is write the 2#10bit code element of data [19:10]=RS (0);

The A2 mouth of 2#RAM is write the 2#10bit code element of data [21:12]=RS (1);

In the 3rd clock cycle of the 3#10bit code element of receiving RS (0)-RS (7), deposit RAM to write mouthful data as follows:

The A2 mouth of 1#RAM is write the 3#10bit code element of data [29:20]=RS (0);

The A2 mouth of 2#RAM is write the 3#10bit code element of data [31:22]=RS (1);

In the 4th clock cycle of the 4#10bit code element of receiving RS (0)-RS (7), deposit RAM to write mouthful data as follows:

The A2 mouth of 1#RAM is write the 4#10bit code element of data [39:30]=RS (0);

The A2 mouth of 2#RAM is write the 4#10bit code element of data [41:32]=RS (1);

In the 5th clock cycle of the 5#10bit code element of receiving RS (0)-RS (7), deposit RAM to write mouthful data as follows:

The A2 mouth of 1#RAM is write the 5#10bi t code element of data [49:40]=RS (0);

The A2 mouth of 2#RAM is write the 5#10bit code element of data [51:42]=RS (1);

In the 6th clock cycle of the 6#10bit code element of receiving RS (0)-RS (7), deposit RAM to write mouthful data as follows:

The A2 mouth of 1#RAM is write the 6#10bit code element of data [59:50]=RS (0);

The A2 mouth of 2#RAM is write the 6#10bit code element of data [61:52]=RS (1);

In the 7th clock cycle of the 7#10bit code element of receiving RS (0)-RS (7), deposit RAM to write mouthful data as follows:

The A2 mouth of 1#RAM is write [3:0] in the 7#10bit code element of data [63:60]=RS (0), 1#RAM has finished the A2 mouth and has write piecing together of 64bit data at this moment, can carry out the write operation of the 0# address of a 1#RAM, deposit simultaneously the 6bit data of [9:4] position in the 7#10bit code element with register, in the next clock cycle, these 6bit data are pieced together in [5:0] of next 64bit data;

The A2 mouth of 2#RAM is write [1:0] in the 7#10bit code element of data [63:62]=RS (1), this moment, 2#RAM did not also finish piecing together of A2 mouth 64bit data, must wait until that also RS (0) code word all writes into after the A2 district of 1#RAM, namely write after the 121# address of 1#RAM, just can obtain this RS (0) and write remaining 2bit data after the A2 district of 1#RAM, piece together these 2bit data into [1:0] of the corresponding 64bit data in 0# address of 2#RAM this moment again, just can carry out the write operation of the 0# address of 2#RAM, before the write operation of the 0# address of not carrying out 2#RAM, the Bit data that has pieced together this address is temporarily put into register and is deposited.

Next carry out the 1# address of 1#RAM and 2#RAM and write piecing together of mouthful data, when piecing together 64bit, namely can carry out the write operation of a RAM, write operation afterwards carries out according to the method, until all RS (0)-RS (7) has write in the A2 district of buffer memory N, when being checked through the high level B2 district RS coding index signal of a clock width, the write operation in the B2 district that adopting uses the same method carries out buffer memory N, until all RS (0)-RS (15) has write in the B2 district of whole buffer memory N, when the data after next frame OTN is through outer code RS coding arrive, begun again the operation of writing buffer memory N of a new round.

Buffer memory N reads method: when buffer memory N writes the 0# address in A2 district, read data from the B2 district of buffer memory N, read first the 122# address of 1#RAM, the 123# address that the next clock cycle is read 1#RAM, read the 243# address of 1#RAM so always, the 122# address of reading 2#RAM of next clock cycle again, carry out so successively until all data in the buffer memory B2 district all are read out the 123# address of reading 2#RAM of next clock cycle again.When buffer memory N writes the 0# address in B2 district, read data from the A2 district of buffer memory N, read first the 0# address of 1#RAM, the 1# address that the next clock cycle is read 1#RAM, read the 121# address of 1#RAM so always, the 0# address of reading 2#RAM of next clock cycle again, carry out so successively until all data in the buffer memory A2 district all are read out the 1# address of reading 2#RAM of next clock cycle again.

After the processing through buffer memory N, namely finished the bus bit wide from 80 outputs to bus bit wide 64.

Circuit based on said method comprises buffer memory M and buffer memory N, and buffer memory M is made of 8 block RAMs, and the size of every block RAM is respectively 1530 * 10; Buffer memory N is made of 8 block RAMs, and the size of every block RAM is respectively 244 * 64.RAM among the buffer memory M is dual port RAM, and this RAM 765 is divided into two districts of A1 and B1 as the boundary take the address, when reading the A1 district, writes the B1 district, when reading the B1 district, writes the A1 district.RAM among the buffer memory N is dual port RAM, and 122 is divided into A2 district and B2 district as the boundary take the address, when reading the A2 district, writes the B2 district, when reading the B2 district, writes the A2 district.

The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.

Claims

1. use bus bit wide conversion implementation method in the optical transfer network of SFEC, it is characterized in that may further comprise the steps:

2. bus bit wide conversion implementation method in the optical transfer network of application as claimed in claim 1 SFEC is characterized in that the RAM among the buffer memory M is dual port RAM, and 765 is divided into two districts of A1 and B1 as the boundary take the address, when reading the A1 district, write the B1 district, when reading the B1 district, write the A1 district.

3. bus bit wide conversion implementation method in the optical transfer network of application as claimed in claim 2 SFEC is characterized in that described step S10 may further comprise the steps:

4. bus bit wide conversion implementation method in the optical transfer network of application SFEC as claimed in claim 3 is characterized in that buffer memory N is made of 8 identical RAM, and this RAM is dual port RAM, and 122 be divided into A2 district and B2 district as the boundary take the address, when reading the A2 district, write the B2 district, when reading the B2 district, write the A2 district.

5. bus bit wide conversion implementation method in the optical transfer network of application as claimed in claim 4 SFEC is characterized in that described step S20 may further comprise the steps:

6. use bus bit wide translation circuit in the optical transfer network of SFEC, it is characterized in that comprising:

Buffer memory M is made of 8 block RAMs, and the size of every block RAM is respectively 1530 * 10;

Buffer memory N is made of 8 block RAMs, and the size of every block RAM is respectively 244 * 64;

Buffer memory M is used for depositing in will be from the data of the OTN frame of 64 the system buss inputs data after by outer code RS (1023,1007) coding rule coding;

Buffer memory N is used for depositing in and reads 10 RS (1023 from 8 block RAMs of buffer memory M respectively at every turn, 1007) coded data is also pressed ISN BCH (2040,1952) data behind the coding rule coding, and output 64 BCH (2040,1952) coded data to 64 system bus from 8 block RAMs of buffer memory N successively;

The read-write clock of buffer memory M and buffer memory N is identical with the system bus clock frequency.

7. bus bit wide translation circuit in the optical transfer network of application as claimed in claim 6 SFEC is characterized in that the RAM among the buffer memory M is dual port RAM, and this RAM 765 is divided into two districts of A1 and B1 take the address as the boundary, when reading the A1 district, write the B1 district, when reading the B1 district, write the A1 district.

8. bus bit wide translation circuit in the optical transfer network of application as claimed in claim 6 SFEC is characterized in that the RAM among the buffer memory N is dual port RAM, and 122 is divided into A2 district and B2 district as the boundary take the address, when reading the A2 district, writes the B2 district, when reading the B2 district, writes the A2 district.