CN101777925B - Data processing device and method thereof - Google Patents

Abstract

The invention discloses a data processing device and a method thereof. The data processing device comprises an interleaver and a component encoder. The method comprises: performing first continuous encoding of an input information sequence and an interleaved input information sequence through the component encoder, calculating a loop state value based on the results of the first step, initializing the register of the component encoder with the calculated value, performing second continuous encoding of the input information sequence and the interleaved input information sequence through the component encoder, and outputting the results of the second continuous encoding as final encoding results. In the technical scheme disclosed by the invention, only one component encoder is used, the quantity of tail bits is reduced simultaneously, and the simpler and more efficient encoding method and the CBRM rate matching method are adopted, thereby effectively reducing processing delay of matching coding with rate, simplifying the complexity of encoding and rate matching, improving the processing speed of encoding and rate matching, and enhancing the encoding efficiency and the spectral efficiency.

Description

A kind of Data Handling Equipment And Method

Technical field

The present invention relates to digital communicating field, particularly, the present invention relates to a kind of Data Handling Equipment And Method.

Background technology

Digital signal is because the impact that is subject to Noise and Interference there will be mistake in transmitting procedure, and in communication system, the general error correction coding that adopts ensures reliable transmission.Turbo code is a kind of encoding scheme that the people such as C.Berrou proposed in 1993, because it is better than other coding efficiency under the applied environment of low signal-to-noise ratio, thereby in various kinds of mobile communication system, one of coding standard using Turbo code as wireless channel.Usually, Turbo encoder is made up of two systematic recursive convolutional (RSC) encoder, interleaver and canceller.

Along with the development of mobile communication, Turbo code coding and decoding technology is constantly developed and perfect, and is widely used in various systems, but the specific coding method and the interleaver that in different mobile communication system, adopt are different.For example, at 3GPP (3rd Generation Partnership Project, third generation partner program) in, comprise the system of Release 6 and LTE, Turbo code is binary system (Binary) coding method, uses tail bit ending (Tail Bits Termination) method.At WiMAX (Worldwide Interoperability for Microwave Access, micro-wave access global inter communication) in, Turbo code is duobinary system (Duo-Binary) coding method, uses and stings tail bit ending (Tail-biting Termination) method, anury bit.The Turbo code coding techniques specification that 3GPP mobile communication system adopts is described in detail by the TS25.212 in 3GPP.The Turbo code coding techniques specification that WiMAX communication system adopts is described in detail by IEEE 802.16d.

Particularly, WiMAX Turbo code encoder comprises CTC (Convolutional TurboCodes, CTC) interleaver and component coder, use 2 encoder parallel concatenated codings, output system position and process interweave and encode the check digit Y1W1, the Y2W2 that process.Wherein, component coder is further made up of three registers and five adders, completes encoding function, and this Turbo code is doubinary encoding (Duo-Binary).

Turbo code in WiMAX uses and stings tail bit ending method, and component coder is first encoded for the first time to input data sequence, obtains the done state of the encoder after encoding for the first time, and then query State table, determines a recurrent state value.Component coder uses the initial condition of this recurrent state value as encoder, and input bit sequence is encoded for the second time again, and the coding result of finally this being encoded is for the second time as the coding output of component coder.In addition, component coder also will encode for the first time accordingly to input data sequence, searches state table, determines recurrent state value and encode for the second time after interweaving.Like this, the tail bit ending method of stinging of the Turbo code in WiMAX need to be through the calculating of 4 cataloged procedures and 2 recurrent state values, and total encoder complexity is high and processing delay is larger.

In addition,, because wireless transmission resources is very limited, wireless communication system need to be each user assignment wireless transmission resources rationally and effectively.For this reason, 3GPP LTE is according to the assigned wireless transmission resources of each user, adopt CBRM (Circular Buffer Rate Matching, circular buffering rate-matched) speed matching method, bit stream to the output of Turbo encoder carries out interleaving treatment, collection and treatment, select to process, pruning modes, wherein selecting to process is that coded bit stream is punched, delete and process, make the quantity of the assigned wireless transmission resources of the number of the coded-bit that each user need to transmit and this user consistent with each other, realize the abundant use of user's wireless transmission resources.But 3GPP Turbo encoder has used 12 tail bits, cause 3GPP LTE CBRM speed matching method also to need these 12 tail bits to do corresponding processing.In addition, also need to use the function that interweaves of 2 kinds of different sub-block interleavers to interweave.Must increase like this processing complexity and the processing delay of CBRM speed matching method, reduce the processing speed of CBRM speed matching method.In addition, these tail bits transmit through wireless transmission resources, also directly cause the decline of efficiency of transmission, make spectrum efficiency lower.

Therefore, be necessary to propose a kind of technical scheme of efficient data processing, to solve, encoder complexity is high in existing system, processing delay is large and the lower problem of spectrum efficiency, makes data processing scheme after improving can adapt to LTE-Advanced system or IMT-Advanced system etc. to have the system of more speed demand.

Summary of the invention

The problem to be solved in the present invention is to propose a kind of Data Handling Equipment And Method, and in solution existing system coding, rate-matched, complexity is high, processing delay is large and the lower problem of spectrum efficiency.

In order to achieve the above object, the invention discloses a kind of data processing equipment, comprising: interleaver, described interleaver is by input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ Interweave, obtain the sequence after interweaving $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\},$ Wherein K represents the number of the bit groupings of input message sequence;

Component coder, described component coder is by described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Sending into successively component coder encodes for the first time, state value S while obtaining the register end-of-encode for the first time of component coder, table look-up and obtain corresponding recurrent state value according to the number of S, K and interleaver, by the register of described recurrent state value initialization component coder, then by described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Send into successively the component coder respectively output verification sequence of encoding for the second time $X_1^p=\{x_0^p,x_1^p,\·\·\·,x_{K-1}^p\}$ With $X_2^p=\{x_k^p,x_{k+1}^p,\·\·\·,x_{2K-1}^p\},$ By described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·,x_{2K-1}^p\}$ Output.

According to embodiments of the invention, described in table look-up obtain corresponding recurrent state value comprise:

The number summation of the bit groupings to described input message sequence and the bit groupings after interweaving, and to (2 ^m-1) delivery, i.e. r=[(1+t) × K] mod (2 ^m-1), the number that wherein t is interleaver, m is the number of component coder register;

According to described r value and described S value, table look-up and obtain corresponding recurrent state value.

According to embodiments of the invention, every dibit is one group, and the length of described input message sequence is 2K bit, and described interleaver is 1, and described component coder register is 3, correspondingly, r=2K mod (7), the state table of inquiring about is:

Wherein, S _02K-1state value while representing the register end-of-encode for the first time of component coder.

According to embodiments of the invention, described component coder comprises recursive convolutional encoder device, and described verification sequence X ₁ ^pand X ₂ ^pby feedforward multinomial { 1,0,1,1} or { 1,0,0,1} output.

According to embodiments of the invention, also comprise rate matchers, described rate matchers comprises:

Bit distributor, described bit distributor is by information sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·,x_{2K-1}^p\}$ Be divided into 4 road burst outputs, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ Or

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(W\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\·\·\·,v_{4K_{\mathrm{\Π}}-1}\}=\{v_0^{\left(0\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(0\right)},v_0^{\left(1\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(1\right)},v_0^{\left(2\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(2\right)},v_0^{\left(3\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(3\right)}\},$ Wherein v _kfor k bit in bit stream V, k=0 ..., 4K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1,2,3, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\Π}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\×C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor, described bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k}=v_{2K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k+1}=v_{3K_{\mathrm{\Π}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer; Described bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

According to embodiments of the invention, described component coder comprises recursive convolutional encoder device, and described verification sequence X ₁ ^pand X ₂ ^pby feedforward multinomial { 1,0,1,1} and { 1,0,0,1} output.

According to embodiments of the invention, also comprise rate matchers, described rate matchers comprises:

Bit distributor, described bit distributor is by information sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·{,x}_{2K-1}^p\}$ Be divided into 6 road burst outputs, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ $d_k^{\left(4\right)}=x_k^p\left(W\right),$ $d_k^{\left(5\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\·\·\·,v_{6K_{\mathrm{\Π}}-1}\}=\{v_0^{\left(0\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(0\right)},v_0^{\left(1\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(1\right)},v_0^{\left(2\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(2\right)},v_0^{\left(3\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(5\right)}\}$ Wherein v _kfor k bit in bit stream V, k=0 ..., 6K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1 ..., 5, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\Π}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\×C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor, described bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k}=v_{2K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k+1}=v_{3K_{\mathrm{\Π}}+k},$ $w_{4K_{\mathrm{\Π}}+2k}=v_{4K_{\mathrm{\Π}}+k},$ $w_{4K_{\mathrm{\Π}}+2k+1}=v_{5K_{\mathrm{\Π}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer; Described bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

The invention allows for a kind of data processing method, comprise the following steps:

By described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Send into successively component coder and encode for the first time, wherein K represents the number of the bit groupings of input message sequence;

State value S while obtaining the register end-of-encode for the first time of component coder, tables look-up and obtains corresponding recurrent state value according to the number of S, K and interleaver;

By the register of described recurrent state value initialization component coder, then by described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Send into successively the component coder respectively output verification sequence of encoding for the second time $X_1^p=\{x_0^p,x_1^p,\·\·\·,x_{K-1}^p\}$ With $X_2^p=\{x_k^p,x_{k+1}^p,\·\·\·,x_{2K-1}^p\},$ By described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·,x_{2K-1}^p\}$ Output.

According to embodiments of the invention, described in table look-up obtain corresponding recurrent state value comprise:

The number summation of the bit groupings to described input message sequence and the bit groupings after interweaving, and to (2 ^m-1) delivery, i.e. r=[(1+t) × K] mod (2 ^m-1), the number that wherein t is interleaver, m is the number of component coder register;

According to described r value and described S value, table look-up and obtain corresponding recurrent state value.

According to embodiments of the invention, every dibit is one group, and the length of described input message sequence is 2K bit, and described interleaver is 1, and described component coder register is 3, correspondingly, r=2K mod (7), the state table of inquiring about is:

Wherein, S _02K-1state value while representing the register end-of-encode for the first time of component coder.

According to embodiments of the invention, described component coder comprises recursive convolutional encoder device, and described verification sequence X ₁ ^pand X ₂ ^pby feedforward multinomial { 1,0,1,1} or { 1,0,0,1} output.

According to embodiments of the invention, also comprise rate-matched processing, described rate-matched processing comprises:

By information sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·,x_{2K-1}^p\}$ Be divided into 4 road burst outputs through bit distributor, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ Or

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(W\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\·\·\·,v_{4K_{\mathrm{\Π}}-1}\}=\{v_0^{\left(0\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(0\right)},v_0^{\left(1\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(1\right)},v_0^{\left(2\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(2\right)},v_0^{\left(3\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(3\right)}\},$ Wherein v _kfor k bit in bit stream V, k=0 ..., 4K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1,2,3, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\Π}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\×C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k}=v_{2K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k+1}=v_{2K_{\mathrm{\Π}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

According to embodiments of the invention, described component coder comprises recursive convolutional encoder device, and described verification sequence X ₁ ^pand x ₂ ^pby feedforward multinomial { 1,0,1,1} and { 1,0,0,1} output.

According to embodiments of the invention, also comprise rate-matched processing, described rate-matched processing comprises:

By information sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·,x_{2K-1}^p\}$ Be divided into 6 road burst outputs through bit distributor, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ $d_k^{\left(4\right)}=x_k^p\left(W\right),$ $d_k^{\left(5\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\·\·\·,v_{6K_{\mathrm{\Π}}-1}\}=\{v_0^{\left(0\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(0\right)},v_0^{\left(1\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(1\right)},v_0^{\left(2\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(2\right)},v_0^{\left(3\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},\·\·\·,v_{K_{\mathrm{\Π}}-1}^{\left(5\right)}\}$ Wherein v _kfor k bit in bit stream V, k=0 ..., 6K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1 ..., 5, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\Π}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\×C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k}=v_{2K_{\mathrm{\Π}}+k},$ $w_{2K_{\mathrm{\Π}}+2k+1}=v_{3K_{\mathrm{\Π}}+k},$ $w_{4K_{\mathrm{\Π}}+2k}=v_{4K_{\mathrm{\Π}}+k},$ $w_{4K_{\mathrm{\Π}}+2k+1}=v_{5K_{\mathrm{\Π}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

High with respect to complexity in existing system coding, rate-matched, processing delay is large and the lower problem of spectrum efficiency, the present invention reduces the number of component coder, reduce the quantity of tail bit, adopt more simple coding method efficiently and CBRM speed matching method, effectively reduce the processing delay of coding and rate-matched, simplify the complexity of coding and rate-matched, improve the processing speed of coding and rate-matched, improve code efficiency and spectrum efficiency.

Brief description of the drawings

Fig. 1 is the structural representation of data processing equipment embodiment of the present invention;

Fig. 2 is the structural representation of an embodiment of component coder of the present invention;

Fig. 3 is the schematic diagram of an embodiment of rate matchers of the present invention;

Fig. 4 is the structural representation of another embodiment of rate matchers of the present invention;

Fig. 5 is the flow chart of data processing method of the present invention;

Fig. 6 is the structural representation of realizing the electronic equipment of data processing method of the present invention.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail:

As shown in Figure 1, be the structural representation of data processing equipment embodiment of the present invention.

Data processing equipment disclosed by the invention, comprises interleaver and component coder.

Wherein, interleaver is by input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ Interweave, obtain the sequence after interweaving $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\},$ Wherein K represents the number of the bit groupings of input message sequence.

By described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Sending into successively component coder encodes for the first time, state value S while obtaining the register end-of-encode for the first time of component coder, table look-up and obtain corresponding recurrent state value according to the number of S, K and interleaver, by the register of described recurrent state value initialization component coder, then by described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Send into successively the component coder respectively output verification sequence of encoding for the second time $X_1^p=\{x_0^p,x_1^p,\·\·\·,x_{K-1}^p\}$ With $X_2^p=\{x_k^p,x_{k+1}^p,\·\·\·,x_{2K-1}^p\},$ By described input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\·\·\·,x_{2K-1}^p\}$ Output.

As shown in Figure 2, be the schematic diagram of component coder specific embodiment of the present invention.

In the embodiment of Fig. 2, what component coder adopted is recursive convolutional encoder device.Obviously, component coder also can adopt other encoder, such as non-recursive convolution coder, block coder etc.

As embodiments of the invention, the feedback multinomial of this recursive convolutional encoder device is that { 1,1,0,1}, its feedforward multinomial is { 1,0,1,1} and/or { 1,0,0,1}.

In the present embodiment, verification sequence X ₁ ^pand X ₂ ^pby feedforward multinomial, { 1,0,1,1} is with { 1,0,0,1} exports, certain, also can be only by feedforward multinomial { 1,0,1,1} or { the some tap output in 1,0,0,1}.Obviously the code efficiency that, the rear sequence of output verification sequence formation coding forms the rear sequence of coding than part output verification sequence is completely low.

Obviously, the component coder in above-described embodiment is not limited to feedback multinomial for example and feedforward multinomial, can also adopt other feedback multinomial and feedforward multinomial.

Preferably, in the present embodiment, described Turbo code is doubinary encoding, and corresponding, every dibit is one group, and the total length of each input message sequence is 2K bit.

Encoder disclosed by the invention first by component coder by input message sequence $X^s=\{x_0^s,x_1^s,\·\·\·,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\Π}}^s=\{x_{\mathrm{\Π}\left(0\right)}^s,x_{\mathrm{\Π}\left(1\right)}^s,\·\·\·,x_{\mathrm{\Π}(K-1)}^s\}$ Send into successively component coder and encode for the first time, the state value S while obtaining the register end-of-encode for the first time of component coder, tables look-up and obtains corresponding recurrent state value according to the number of S, K and interleaver.That is, the number summation of the bit groupings to input message sequence and the bit groupings after interweaving, and to (2 ^m-1) delivery, obtains r=[(1+t) × K] mod (2 ^m-1), the number that wherein t is interleaver, m is the number of component coder register, then according to r value and S value, tables look-up and obtains corresponding recurrent state value.

In conjunction with the present invention embodiment as shown in Figure 2, interleaver is 1, and component coder register is 3, correspondingly, and r=2K mod (7).

With S _02K-1state value while representing the register end-of-encode for the first time of component coder in the present embodiment, by utilizing 2K mod (7) and S _02K-1question blank 1, obtains corresponding recurrent state value, and by the register of this recurrent state value initialization component coder, then encode for the second time.

Table 1

Below in conjunction with Fig. 1 and Fig. 2, the specific works flow process of encoder disclosed by the invention is described in detail:

(1) register of initialization component coder, register is set to " 0 " entirely.

(2) component coder is encoded for the first time.In the time encoding for the first time, diverter switch is connected to tap " 1 ", to input message sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ Encode.Complete current input message sequence X at component coder ^scoding time, diverter switch from tap " 1 " disconnect, be connected to tap " 2 ", component coder is the data sequence after interweaving to input message sequence $X_{\mathrm{\&Pi;}}^s=\{x_{\mathrm{\&Pi;}\left(0\right)}^s,x_{\mathrm{\&Pi;}\left(1\right)}^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{\mathrm{\&Pi;}(K-1)}^s\}$ Encode.Complete current data sequence X at component coder _∏ ^scoding time, diverter switch from tap " 2 " disconnect, be connected to tap " 1 ".Now, the end-of-encode for the first time of component coder.Wherein, input message sequence X ^sthe information symbol that has comprised K group.X _i ^s(0≤i < K) is sequence X ^si element, represent i group information symbol.In Fig. 2, X ^scorresponding to A, the input of B two-way of the interleaver of figure below.Data sequence X _∏ ^salso comprised K group information symbol.X _{∏ (i)} ^s(0≤i < K) is sequence X _∏ ^sin i element, corresponding to input message sequence X ^sthe individual element of ∏ (i) or ∏ (i) group information symbol.In Fig. 2, X _∏ ^scorresponding to C, the output of D two-way of interleaver.

(3) at component coder after having encoded for the first time, the present invention, according to coding result for the first time, obtains the done state value S of component coder _02K-1, and according to the length 2K of input message sequence, use table 1 calculates a recurrent state value, and with the register of this recurrent state value initialization component coder, the state value of the register of component coder is set to this recurrent state value.

(4) component coder is encoded for the second time.In the time encoding for the second time, diverter switch is connected to tap " 1 " by component coder, then to input message sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ Encode, and obtain a verification sequence $X_1^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^p\}.$ Complete current input message sequence X at component coder ^scoding time, diverter switch from tap " 1 " disconnect, be connected to tap " 2 ", component coder is the data sequence after interweaving to input message sequence $X_{\mathrm{\&Pi;}}^s=\{x_{\mathrm{\&Pi;}\left(0\right)}^s,x_{\mathrm{\&Pi;}\left(1\right)}^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{\mathrm{\&Pi;}(K-1)}^s\}$ Encode, and obtain another verification sequence $X_2^p=\{x_k^p,x_{k+1}^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}.$ Complete current data sequence X at component coder _∏ ^scoding time, diverter switch from tap " 2 " disconnect, be connected to tap " 1 ".In Fig. 2, X ^pcorresponding to Y, the output of W two-way or a wherein road output of component coder.Now, the end-of-encode for the second time of component coder.

(5) by X ₁ ^pand X ₂ ^pform a complete verification sequence $X^p=\{X_1^p,X_2^p\}=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}.$

(6) last, by information sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\},$ Verification sequence $X^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}$ Output.

In addition, data processing equipment disclosed by the invention, also comprises rate matchers, and as shown in Figure 3, Figure 4, rate matchers comprises: bit distributor, sub-interleaver, bit collection processor and bit are selected and trimmer.

When verification sequence is only by feedforward multinomial { 1,0,1,1} or { when 1,0,0,1} output, rate-matched implement body as shown in Figure 3.

As shown in Figure 3, rate matchers comprises:

Bit distributor, described bit distributor is by information sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}$ Be divided into 4 road burst outputs, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ Or

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(W\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\&CenterDot;\&CenterDot;\&CenterDot;,v_{4K_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}\},$ Wherein v _kfor k bit in bit stream V, k=0 ..., 4K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1,2,3, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor, described bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k}=v_{2K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k+1}=v_{3K_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer; Described bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

Particularly, x _k ^s(A) bit of the output of the information bits A in corresponding diagram 2, x _k ^s(B) bit of the output of the information bits B in corresponding diagram 2, x _k ^p(Y), x _k+k ^p(Y) bit of the output of the check bit Y in corresponding diagram 2, x _k ^p(W), x _k+k ^p(W) bit of the output of the check bit W in corresponding diagram 2.

As shown in Figure 3, diverter switch T1 is by above-mentioned 4 road burst d _k ⁽⁰⁾, d _k ⁽¹⁾, d _k ⁽²⁾, d _k ⁽³⁾send into respectively sub-block interleaver, carry out successively independently block interleaving processing, sub-block interleaver is correspondingly exported the bit stream V after interweaving of 4 tunnels ⁽⁰⁾, V ⁽¹⁾, V ⁽²⁾and V ⁽³⁾.

Detailed process is as follows:

First, sub-block interleaver Jiang Yi road burst d _k ⁽ⁱ⁾(i=0,1,2,3) write a line number by row is R _subblock ^tC, columns is C _subblock ^tCinterleaver matrix T

Wherein, each row of interleaver matrix T are that the 0th row are to C from left to right successively _subblock ^tC-1 row, each row is the 0th to walk to R from top to bottom successively _subblock ^tC-1 row.Wherein, C _subblock ^tCbe an integer, for example $C_{\mathrm{subblock}}^{\mathrm{TC}}=32.$ R _subblock ^tCsatisfied $L_s\&le;(R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}})$ Smallest positive integral, L _dthe length of Wei Mei road burst.If $(R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}})>L_d,$ First sub-block interleaver fills by row at the beginning element position of interleaver matrix $N_D=(R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}}-L_d)$ Individual vacant symbol <NULL>, then writes all bits in the burst of every road by row more successively at other element position of interleaver matrix.Concrete operations are as follows:

Y _k=<NULL>, wherein $k=\mathrm{0,1},...,N_D-1,y_{N_D+k}=d_k^{\left(i\right)},$ Wherein k=0,1 ..., L _d-1.

Then, sub-block interleaver uses a permutation vector P that interleaver matrix T is carried out to column permutation, and P comprises C _subblock ^tCindividual different element, the value of each element is 0 to C _subblock ^tCinteger between-1.P (k) represents k the element of permutation vector P.

For example $P=[P\left(0\right),P\left(1\right),...,P(C_{\mathrm{subblock}}^{\mathrm{TC}}-1)]=[\mathrm{0,16,8,24,4,20,12,28,2,18,10,26,6},$ $\mathrm{22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31}]$ Or [1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31,0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30], above-mentioned two kinds of different permutation vector P all comprise 32 different elements, and the span of each element is 0 to 31 integer.

Finally, sub-block interleaver is read all elements in the interleaver matrix after displacement by row, exports a corresponding road burst d _k ⁽ⁱ⁾interweave after bit stream $V^{\left(i\right)}=\{v_0^{\left(i\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(i\right)}\},$ Wherein v _k ⁽ⁱ⁾represent the bit stream V on i road ⁽ⁱ⁾in k bit.Wherein $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}}.$ First sub-block interleaver reads the element of δ row, then reads successively δ+1 and is listed as to C _subblock ^tC-1 row.If δ >=1, sub-block interleaver just continues to read successively the element of the 0th row to δ-1 row.Output intent is specific as follows:

$v_k^{\left(i\right)}=y_{\mathrm{\&Pi;}\left(k\right)},$

Wherein, k=0 ..., K _∏-1, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}},$ The function ∏ (k) that interweaves is

Wherein, δ is an integer, can directly equal 0 or 1.The value of δ can also change according to the difference of the input information bits number of component coder.

Sub-block interleaver is to above-mentioned i road burst d _k ⁽ⁱ⁾use a kind of permutation vector P in two kinds of above-mentioned different permutation vector _iwith the function ∏ that interweaves _icarry out independently block interleaving processing, wherein i=0,1,2,3.

These permutation vector P _iwith the function ∏ that interweaves _ican be identical a kind of permutation vector P and the function ∏ (k) that interweaves, now P ₀=P ₁=P ₂=P ₃.Wherein i=0,1,2,3.

These permutation vector P _iwith the function ∏ that interweaves _ican also be different permutation vector P and the function ∏ (k) that interweaves, now P ₀=P ₁=P ₂≠ P ₃.Wherein i=0,1,2,3.

Sub-block interleaver is by the bit stream V after the interweaving of above-mentioned 4 tunnels ⁽⁰⁾, V ⁽¹⁾, V ⁽²⁾and V ⁽³⁾one group of bit stream is exported in serial successively $V=\{v_0,\&CenterDot;\&CenterDot;\&CenterDot;,v_{4K_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}\}.$ Wherein v _krepresent k bit in bit stream V, k=0 ..., 4K _∏-1.

When verification sequence, only by feedforward multinomial, { 1,0,1,1} is with { when 1,0,0,1} output, rate-matched implement body as shown in Figure 4.

As shown in Figure 4, rate matchers comprises:

Bit distributor, described bit distributor is by information sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}$ Be divided into 6 road burst outputs, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ $d_k^{\left(4\right)}=x_k^p\left(W\right),$ $d_k^{\left(k\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\&CenterDot;\&CenterDot;\&CenterDot;,v_{6K_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(5\right)}\}$ Wherein v _kfor k bit in bit stream V, k=0 ..., 6K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1 ..., 5, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor, described bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k}=v_{2K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k+1}=v_{3K_{\mathrm{\&Pi;}}+k},$ $w_{4K_{\mathrm{\&Pi;}}+2k}=v_{4K_{\mathrm{\&Pi;}}+k},$ $w_{4K_{\mathrm{\&Pi;}}+2k+1}=v_{5K_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer; Described bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

Particularly, x _k ^s(A) bit of the output of the information bits A in corresponding diagram 2, x _k ^s(B) bit of the output of the information bits B in corresponding diagram 2, x _k ^p(Y), x _k+k ^p(Y) bit of the output of the check bit Y in corresponding diagram 2, x _k ^p(W), x _k+k ^p(W) bit of the output of the check bit W in corresponding diagram 2.

As shown in Figure 4, all bits of encoder output are dispensed to as follows 6 road burst d by bit distributor _k ⁽⁰⁾, d _k ⁽¹⁾, d _k ⁽²⁾, d _k ⁽³⁾, d _k ⁽⁴⁾and d _k ⁽⁵⁾, the length of every road burst is L _d=K bit:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ $d_k^{\left(4\right)}=x_k^p\left(W\right),$ $d_k^{\left(5\right)}=x_{K+k}^p\left(W\right),$ Wherein k=0 ..., K-1.

Diverter switch T1 is by above-mentioned 6 road burst d _k ⁽⁰⁾, d _k ⁽¹⁾, d _k ⁽²⁾, d _k ⁽³⁾, d _k ⁽⁴⁾and d _k ⁽⁵⁾send into respectively sub-block interleaver, carry out successively independently block interleaving processing, sub-block interleaver is correspondingly exported the bit stream V after interweaving of 6 tunnels ⁽⁰⁾, V ⁽¹⁾, V ⁽²⁾, V ⁽³⁾, V ⁽⁴⁾and V ⁽⁵⁾.

Sub-block interleaver uses above-mentioned block interleaving processing, comprises and uses above-mentioned permutation vector P and the function ∏ (k) that interweaves.

Sub-block interleaver is to above-mentioned i road burst d _k ⁽ⁱ⁾use above-mentioned a kind of permutation vector P _iwith the function ∏ that interweaves _icarry out independently block interleaving processing, wherein i=0,1,2,3,4,5.

These permutation vector P _iwith the function ∏ that interweaves _ican be identical a kind of permutation vector P and the function ∏ (k) that interweaves, now P ₀=P ₁=P ₂=P ₃=P ₄=P ₅, wherein i=0,1,2,3,4,5.

These permutation vector P _iwith the function ∏ that interweaves _ican also be different permutation vector P and the function ∏ (k) that interweaves, now { P ₀=P ₁=P ₂=P ₄} ≠ { P ₃=P ₅, wherein i=0,1,2,3,4,5.

Sub-block interleaver is by the bit stream V after the interweaving of above-mentioned 6 tunnels ⁽⁰⁾, V ⁽¹⁾, V ⁽²⁾, V ⁽³⁾, V ⁽⁴⁾and V ⁽⁵⁾one group of bit stream V is exported in serial successively:

$V=\{v_0,\&CenterDot;\&CenterDot;\&CenterDot;,v_{6K_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(5\right)}\}$ Wherein v _krepresent k bit in bit stream V, k=0 ..., 6K _∏-1.

Bit is collected device by the bit stream V processing that interlocks, and exports one group of bit stream $W=\{w_0,\&CenterDot;\&CenterDot;\&CenterDot;,w_{6K_{\mathrm{\&Pi;}}-1}\},$ Wherein w _krepresent k bit in bit stream W, k=0 ..., 6K _∏-1.Output intent is specific as follows:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k}=v_{2K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k+1}=v_{3K_{\mathrm{\&Pi;}}+k},$ $w_{4K_{\mathrm{\&Pi;}}+2k}=v_{4K_{\mathrm{\&Pi;}}+k},$ $w_{4K_{\mathrm{\&Pi;}}+2k+1}=v_{5K_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _∏-1.

In the above-described embodiments, only adopt one-component encoder, reduce the quantity of tail bit simultaneously, by adopting more simple coding method efficiently and CBRM speed matching method, effectively reduce the processing delay of coding and rate-matched, simplify the complexity of coding and rate-matched, improve the processing speed of coding and rate-matched, improve code efficiency and spectrum efficiency.

As shown in Figure 5, the invention also discloses a kind of data processing method.Method disclosed by the invention comprises the following steps:

S501: the sequence after input message sequence and interleaving treatment is sent into component coder successively and encode for the first time.

In step S501, will state input message sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\&Pi;}}^s=\{x_{\mathrm{\&Pi;}\left(0\right)}^s,x_{\mathrm{\&Pi;}\left(1\right)}^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{\mathrm{\&Pi;}(K-1)}^s\}$ Send into successively component coder and encode for the first time, wherein K represents the number of the bit groupings of input message sequence.

Wherein, coding method disclosed by the invention can have multiple interleavers, and interleaver completes the function that input message sequence is interweaved.Interleaver is by input message sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ Interweave, obtain the sequence after interweaving $X_{\mathrm{\&Pi;}}^s=\{x_{\mathrm{\&Pi;}\left(0\right)}^s,x_{\mathrm{\&Pi;}\left(1\right)}^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{\mathrm{\&Pi;}(K-1)}^s\},$ Wherein K represents the number of the bit groupings of input message sequence, interweaves taking bit groupings as elementary cell.

What wherein, component coder adopted is recursive convolutional encoder device.Obviously, component coder also can adopt other encoder, such as non-recursive convolution coder, block coder etc.

As embodiments of the invention, the feedback multinomial of this recursive convolutional encoder device is that { 1,1,0,1}, its feedforward multinomial is { 1,0,1,1} and/or { 1,0,0,1}.

Preferably, in the present embodiment, described Turbo code is doubinary encoding, and corresponding, every dibit is one group, and the total length of each input message sequence is 2K bit.

S502: the state value during according to the end-of-encode for the first time of the register of component coder, the number of bit groupings of input message sequence and the number of interleaver are tabled look-up and obtained corresponding recurrent state value.

In step S502, the state value S when obtaining the register end-of-encode for the first time of component coder, tables look-up and obtains corresponding recurrent state value according to the number of S, K and interleaver.That is, the number summation of the bit groupings to input message sequence and the bit groupings after interweaving, and to (2 ^m-1) delivery, tries to achieve r=[(1+t) × K] mod (2 ^m-1), the number that wherein t is interleaver, m is the number of component coder register, then according to r value and S value, tables look-up and obtains corresponding recurrent state value.

As embodiments of the invention, be that 1, component coder register are the situation of 3 for interleaver, correspondingly, r=2K mod (7).

With S _02K-1state value while representing the register end-of-encode for the first time of component coder in the present embodiment, by utilizing 2K mod (7) and S _02K-1question blank 1, obtains corresponding recurrent state value, and by the register of this recurrent state value initialization component coder, then encode for the second time.

S503: by the register of recurrent state value initialization component coder, encode for the second time and export.

In step S503, by the register of the recurrent state value initialization component coder obtaining, then by input message sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\&Pi;}}^s=\{x_{\mathrm{\&Pi;}\left(0\right)}^s,x_{\mathrm{\&Pi;}\left(1\right)}^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{\mathrm{\&Pi;}(K-1)}^s\}$ Send into successively the component coder respectively output verification sequence of encoding for the second time $X_1^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^p\}$ With $X_2^p=\{x_k^p,x_{k+1}^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\},$ By input message sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}$ Output.

In step S503, also comprise rate-matched processing procedure.

When verification sequence only by feedforward multinomial 1,0,1,1} or when 1,0,0,1} output, rate-matched processing procedure comprises:

By information sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}$ Be divided into 4 road burst outputs through bit distributor, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ Or

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(W\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\&CenterDot;\&CenterDot;\&CenterDot;,v_{4K_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}\},$ Wherein v _kfor k bit in bit stream V, k=0 ..., 4K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1,2,3, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k}=v_{2K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k+1}=v_{3K_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

When verification sequence only by feedforward multinomial 1,0,1,1} and when 1,0,0,1} output, rate-matched process comprises:

By information sequence $X^s=\{x_0^s,x_1^s,\&CenterDot;\&CenterDot;\&CenterDot;,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,\&CenterDot;\&CenterDot;\&CenterDot;,x_{2K-1}^p\}$ Be divided into 6 road burst outputs through bit distributor, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),$ $d_k^{\left(1\right)}=x_k^s\left(B\right),$ $d_k^{\left(2\right)}=x_k^p\left(Y\right),$ $d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ $d_k^{\left(4\right)}=x_k^p\left(W\right),$ $d_k^{\left(5\right)}=x_{K+k}^p\left(W\right),$ Wherein x _k ^s(A) be input message sequence X ^sthe half bit of middle K group bit, x _k ^s(B) be input message sequence X ^ssecond half bit of middle K group bit, x _k ^pand x (Y) _k+k ^p(Y) be feedforward multinomial { bit of 1,0,1,1} output, x _k ^pand x (W) _k+k ^p(W) for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,\&CenterDot;\&CenterDot;\&CenterDot;,v_{6K_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},\&CenterDot;\&CenterDot;\&CenterDot;,v_{K_{\mathrm{\&Pi;}}-1}^{\left(5\right)}\}$ Wherein v _kfor k bit in bit stream V, k=0 ..., 6K _∏-1, v _t ⁽ⁱ⁾be t bit of i road output after sub-interleaver is processed, t=0 ..., K _∏-1, i=0,1 ..., 5, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, R _subblock ^tCfor line number, the C of T _subblock ^tCfor the columns of T, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k＝v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k}=v_{2K_{\mathrm{\&Pi;}}+k},$ $w_{2K_{\mathrm{\&Pi;}}+2k+1}=v_{3K_{\mathrm{\&Pi;}}+k},$ $w_{4K_{\mathrm{\&Pi;}}+2k}=v_{4K_{\mathrm{\&Pi;}}+k},$ $w_{4K_{\mathrm{\&Pi;}}+2k+1}=v_{5K_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _∏-1;

Bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

In said method, data processing only adopts one-component encoder, reduce the quantity of tail bit simultaneously, by adopting more simple coding method efficiently and CBRM speed matching method, effectively reduce the processing delay of coding and rate-matched, simplify the complexity of coding and rate-matched, improve the processing speed of coding and rate-matched, improve code efficiency and spectrum efficiency.

Fig. 6 is the structural representation of realizing the electronic equipment of data processing method of the present invention.In Fig. 6, subscriber equipment 610 is realized communication by access Access Network 620.Wherein, subscriber equipment 610 comprises data processor 613, the memory 612 of connection data processor 613, and the wireless transceiver 614 that can receive and send, and subscriber equipment 610 is the two-way communication with Access Network 620 by wireless transceiver 614 realizations.Memory 612 is storing program 611.Access Network 620 comprises data processor 623, the memory 622 of connection data processor 623, and the wireless transceiver 624 that can receive and send, and Access Network 620 is the two-way communication with subscriber equipment 610 by wireless transceiver 624 realizations.Memory 622 is storing program 621.Wherein Access Network 620 is connected to one or more external networks or system by data channel, for example, be mobile communications network or Internet, because described partial content is the known technology of this area, therefore in Fig. 6, does not draw.

Data processor 613 and data processor 623 are carried out corresponding program 611, program 621, and the program command that program 611, program 621 comprise, for carrying out the embodiment of the above-mentioned elaboration of the present invention, is realized data processing method of the present invention.Embodiments of the invention can be realized by the data processor 613 in subscriber equipment 610 and Access Network 620 and data processor 623 object computer software programs, or the form combining with hardware by hardware, by software realizes.

More specifically, in the above-described embodiments, the way of realization of carrying out data processing method of the present invention includes, but are not limited to DSP (Digital Signal Processing, digital signal processor), FPGA (Field Programmable Gate Array, field programmable gate array), the specific implementation such as ASIC (ApplicationSpecific Integrated Circuit, application-specific integrated circuit (ASIC)).

Obviously, the subscriber equipment 610 in the present embodiment includes but not limited to following equipment: the subscriber terminal equipments such as mobile phone, personal digital assistant PDA, portable computer.Access Network 620 in the present embodiment includes but not limited to following equipment: the access network equipment of the system that the relevant connection users such as the access point AP (Access Point) of base station, WLAN (wireless local area network) access.

Based on above-mentioned data processing method, the present invention also proposes a kind of computer program, for carrying out the data processing method of above-described embodiment.

Based on above-mentioned data processing method, the present invention also proposes a kind of readable computer medium, for carrying the computer program of the data processing method of carrying out above-described embodiment.

Here " readable computer medium " term used refers to that any program of execution that is provided for is to the medium of data processor.So a kind of medium can have various ways, includes, but are not limited to non-volatile media, Volatile media, transmission medium.Non-volatile media comprises the CD or the disk that for example resemble memory device, and Volatile media comprises the dynamic memory that resembles main storage.

Transmission medium comprises coaxial cable, copper cash and optical fiber, comprises the circuit that comprises bus.Transmission medium also can adopt acoustics, optics or electromagnetic form, as those produce in radio frequency (RF) and infrared (IR) data communication.The common version of readable computer medium comprises for example floppy disk, soft dish, hard disk, tape, any other magnetizing mediums, CD-ROM, CDRW, DVD, any other light medium, punched card, paper tape, optical side millimeter paper.Any with hole or band can recognize the physical medium of mark, RAM, PROM and EPROM, FLASH-EPROM, any other memory feature or cassette tape, carrier wave or any other computer-readable medium.Multi-form computer-readable medium can be used for being provided for the program of carrying out to data processor.For example, can be created at first the disk of a remote computer for realizing the program of part at least of the present invention.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (6)

1. a data processing equipment, is characterized in that, comprising:

Interleaver, described interleaver is by input message sequence interweave, obtain the sequence after interweaving wherein K represents the number of the bit groupings of input message sequence;

Component coder, described component coder is by described input message sequence and sequence after interleaving treatment sending into successively component coder encodes for the first time, state value S while obtaining the register end-of-encode for the first time of component coder, table look-up and obtain corresponding recurrent state value according to the number of S, K and interleaver, by the register of described recurrent state value initialization component coder, then by described input message sequence and sequence after interleaving treatment send into successively the component coder respectively output verification sequence of encoding for the second time $X_1^p=\{x_0^p,x_1^p,...,x_{K-1}^p\}$ With $X_2^p=\{x_k^p,x_{k+1}^p,...,x_{2K-1}^p\},$ By described input message sequence $X^s=\{x_0^s,x_1^s,...,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,...,x_{2K-1}^p\}$ Output,

Wherein, described component coder comprises recursive convolutional encoder device, and described verification sequence with by feedforward multinomial 1,0,1,1} and/or 1,0,0,1} output, and described data processing equipment also comprises rate matchers, described rate matchers comprises that bit distributor, sub-interleaver, bit collection processor and bit select and trimmer,

In described verification sequence with by feedforward multinomial 1,0,1,1} or in the situation of 1,0,0,1} output,

Described bit distributor is by information sequence and verification sequence be divided into 4 road burst outputs, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),d_k^{\left(1\right)}=x_k^s\left(B\right),d_k^{\left(2\right)}=x_k^p\left(Y\right),d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ Or

$d_k^{\left(0\right)}=x_k^s\left(A\right),d_k^{\left(1\right)}=x_k^s\left(B\right),d_k^{\left(2\right)}=x_k^p\left(W\right),d_k^{\left(3\right)}=x_{K+k}^p\left(W\right),$ Wherein for input message sequence X ^sthe half bit of middle K group bit, for input message sequence X ^ssecond half bit of middle K group bit, with for feedforward multinomial the bit of 1,0,1,1} output, with for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,...,v_{{4K}_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}\},$ Wherein v _kfor k bit in bit stream V, k=0 ..., 4K _Π-1, be t bit of i road output after sub-interleaver is processed, t=0 ..., K _Π-1, i=0,1,2,3, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, for the line number of T, for the columns of T,

Described bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k=v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},w_{{2K}_{\mathrm{\&Pi;}}+2k}=v_{{2K}_{\mathrm{\&Pi;}}+k},w_{{2k}_{\mathrm{\&Pi;}}+2k+1}=v_{{3K}_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _Π-1;

Described bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission;

And in described verification sequence with by feedforward multinomial 1,0,1,1} and in the situation of 1,0,0,1} output,

Described bit distributor is by information sequence and verification sequence be divided into 6 road burst outputs, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),d_k^{\left(1\right)}=x_k^s\left(B\right),d_k^{\left(2\right)}=x_k^p\left(Y\right),d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),d_k^{\left(4\right)}=x_k^p\left(W\right),d_k^{\left(5\right)}=x_{K+k}^p\left(W\right),$ Wherein for input message sequence X ^sthe half bit of middle K group bit, for input message sequence X ^ssecond half bit of middle K group bit, with for feedforward multinomial the bit of 1,0,1,1} output, with for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,...,v_{{6K}_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(5\right)}\}$ Wherein v _kfor k bit in bit stream V, k=0 ..., 6K _Π-1, be t bit of i road output after sub-interleaver is processed, t=0 ..., K _Π-1, i=0,1 ..., 5, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, for the line number of T, for the columns of T, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{Tc}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}};$

Described bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k=v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},w_{{2K}_{\mathrm{\&Pi;}}+2k}=v_{{2K}_{\mathrm{\&Pi;}}+k},w_{{2k}_{\mathrm{\&Pi;}}+2k+1}=v_{{3K}_{\mathrm{\&Pi;}}+k},w_{{4K}_{\mathrm{\&Pi;}}+2k}=v_{{4K}_{\mathrm{\&Pi;}}+k},$ $w_{{4K}_{\mathrm{\&Pi;}}+2k+1}=v_{{5K}_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _Π-1;

Described bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

2. data processing equipment as claimed in claim 1, is characterized in that, described in table look-up obtain corresponding recurrent state value comprise:

The number summation of the bit groupings to described input message sequence and the bit groupings after interweaving, and to (2 ^m-1) delivery, i.e. r=[(1+t) × K] mod (2 ^m-1), the number that wherein t is interleaver, m is the number of component coder register;

According to described r value and described S value, table look-up and obtain corresponding recurrent state value.

3. data processing equipment as claimed in claim 2, is characterized in that, every dibit is one group, the length of described input message sequence is 2K bit, and described interleaver is 1, and described component coder register is 3, correspondingly, r=2Kmod (7), the state table of inquiring about is:

4. a data processing method, is characterized in that, comprises the following steps:

By input message sequence and described input message sequence is carried out to the sequence after interleaving treatment send into successively component coder and encode for the first time, wherein K represents the number of the bit groupings of input message sequence;

State value S while obtaining the register end-of-encode for the first time of component coder, tables look-up and obtains corresponding recurrent state value according to the number of S, K and interleaver;

By the register of described recurrent state value initialization component coder, then by described input message sequence $X^s=[x_0^s,x_1^s,...,x_{K-1}^s\}$ And sequence after interleaving treatment $X_{\mathrm{\&Pi;}}^s=\{x_{\mathrm{\&Pi;}\left(0\right)}^s,x_{\mathrm{\&Pi;}\left(1\right)}^s,...,x_{\mathrm{\&Pi;}(K-1)}^s\}$ Send into successively the component coder respectively output verification sequence of encoding for the second time with $X_2^p=\{x_x^p,x_{k+1}^p,...,x_{2K-1}^p\},$ By described input message sequence $X^s=\{x_0^s,x_1^s,...,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,...,x_{2K-1}^p\}$ Output,

Wherein, described component coder comprises recursive convolutional encoder device, and described verification sequence with by feedforward multinomial 1,0,1,1} and/or 1,0,0,1} output, and described data processing method also comprises rate-matched processing:

In described verification sequence with by feedforward multinomial 1,0,1,1} or in the situation of 1,0,0,1} output, described rate-matched processing comprises:

By information sequence and verification sequence be divided into 4 road burst outputs through bit distributor, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),d_k^{\left(1\right)}=x_k^s\left(B\right),d_k^{\left(2\right)}=x_k^p\left(Y\right),d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),$ Or

$d_k^{\left(0\right)}=x_k^s\left(A\right),d_k^{\left(1\right)}=x_k^s\left(B\right),d_k^{\left(2\right)}=x_k^p\left(W\right),d_k^{\left(3\right)}=x_{K+k}^p\left(W\right),$ Wherein for input message sequence X ^sthe half bit of middle K group bit, for input message sequence X ^ssecond half bit of middle K group bit, with for feedforward multinomial the bit of 1,0,1,1} output, with for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,...,v_{{4K}_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}\},$ Wherein v _kfor k bit in bit stream V, k=0 ..., 4K _Π-1, be t bit of i road output after sub-interleaver is processed, t=0 ..., K _Π-1, i=0,1,2,3, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, for the line number of T, for the columns of T,

Bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k=v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},w_{{2K}_{\mathrm{\&Pi;}}+2k}=v_{{2K}_{\mathrm{\&Pi;}}+k},w_{{2k}_{\mathrm{\&Pi;}}+2k+1}=v_{{3K}_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _Π-1;

Bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission;

And in described verification sequence with by feedforward multinomial 1,0,1,1} and in the situation of 1,0,0,1} output, described rate-matched processing comprises:

By information sequence $X^s=\{x_0^s,x_1^s,...,x_{K-1}^s\}$ And verification sequence $X^p=\{x_0^p,x_1^p,...,x_{2K-1}^p\}$ Be divided into 6 road burst outputs through bit distributor, the length of every road burst is L _d=K bit, allocation criteria is:

$d_k^{\left(0\right)}=x_k^s\left(A\right),d_k^{\left(1\right)}=x_k^s\left(B\right),d_k^{\left(2\right)}=x_k^p\left(Y\right),d_k^{\left(3\right)}=x_{K+k}^p\left(Y\right),d_k^{\left(4\right)}=x_k^p\left(W\right),d_k^{\left(5\right)}=x_{K+k}^p\left(W\right),$

Wherein for input message sequence X ^sthe half bit of middle K group bit, for input message sequence X ^ssecond half bit of middle K group bit, with for feedforward multinomial the bit of 1,0,1,1} output, with for feedforward multinomial the bit of 1,0,0,1} output, k=0 ..., K-1;

Sub-interleaver, described sub-interleaver receives a road and enters interleaver matrix T through the bit stream of described bit distributor output, with the function that interweaves v after interweaving, the bit stream of described bit distributor output is exported in each road, $V=\{v_0,...,v_{{6K}_{\mathrm{\&Pi;}}-1}\}=\{v_0^{\left(0\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(0\right)},v_0^{\left(1\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(1\right)},v_0^{\left(2\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(2\right)},v_0^{\left(3\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(3\right)}{v}_0^{\left(4\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(4\right)}{v}_0^{\left(5\right)},...,v_{K_{\mathrm{\&Pi;}}-1}^{\left(5\right)}\}$ Wherein vk is k bit in bit stream V, k=0 ..., 6K _Π-1, be t bit of i road output after sub-interleaver is processed, t=0 ..., K _Π-1, i=0,1 ..., 5, δ is integer, P is the permutation vector of interleaver matrix T being carried out to column permutation, for the line number of T, for the columns of T, $K_{\mathrm{\&Pi;}}=R_{\mathrm{subblock}}^{\mathrm{TC}}\&times;C_{\mathrm{subblock}}^{\mathrm{TC}};$

Bit collection processor receives after the bit stream V of described sub-interleaver output, and bit stream V is interlocked and processes rear output, and output criterion is:

w _2k=v _k， $w_{2k+1}=v_{K_{\mathrm{\&Pi;}}+k},w_{{2K}_{\mathrm{\&Pi;}}+2k}=v_{{2K}_{\mathrm{\&Pi;}}+k},w_{{2k}_{\mathrm{\&Pi;}}+2k+1}=v_{{3K}_{\mathrm{\&Pi;}}+k},w_{{4K}_{\mathrm{\&Pi;}}+2k}=v_{{4K}_{\mathrm{\&Pi;}}+k},$ $w_{{4K}_{\mathrm{\&Pi;}}+2k+1}=v_{{5K}_{\mathrm{\&Pi;}}+k},$ Wherein k=0 ..., K _Π-1;

Bit is selected and trimmer receives the bit stream that described bit collection processor is exported, and vacant symbol is abandoned, and forms bit stream waiting for transmission.

5. data processing method as claimed in claim 4, is characterized in that, described in table look-up obtain corresponding recurrent state value comprise:

The number summation of the bit groupings to described input message sequence and the bit groupings after interweaving, and to (2 ^m-1) delivery, i.e. r=[(1+t) × K] mod (2 ^m-1), the number that wherein t is interleaver, m is the number of component coder register;

According to described r value and described S value, table look-up and obtain corresponding recurrent state value.

6. data processing method as claimed in claim 5, is characterized in that, every dibit is one group, the length of described input message sequence is 2K bit, and described interleaver is 1, and described component coder register is 3, correspondingly, r=2Kmod (7), the state table of inquiring about is: