CN101771663B - Verification system based on UCPS protocol - Google Patents
Verification system based on UCPS protocol Download PDFInfo
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- CN101771663B CN101771663B CN 200810208233 CN200810208233A CN101771663B CN 101771663 B CN101771663 B CN 101771663B CN 200810208233 CN200810208233 CN 200810208233 CN 200810208233 A CN200810208233 A CN 200810208233A CN 101771663 B CN101771663 B CN 101771663B
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Abstract
The invention discloses a verification system based on a UCPS protocol, which comprises an FPGA chip, an HDMI receiving chip, an HDMI sending chip, an SRAM module, an EEPROM module, an MCU configuration module, a second EEPROM module and a power supply module, wherein the FPGA chip is used for realizing various algorithms of the UCPS protocol, the HDMI receiving chip, the HDMI sending chip, the SRAM module and the EEPROM module are connected with the FPGA chip, and the MCU configuration module and the second EEPROM module are connected with the HDMI sending chip, the FPGA chip and the HDMI sending chip through buses. The invention can lower the development difficulty of the UCPS protocol on the basis of ensuring the speed of the algorithms of the UCPS protocol.
Description
Technical field
The present invention relates to MultiMedia Field, particularly relate to a kind of UCPS agreement verification system of (Unified ContentProtection System unifies the numerical protection agreement).
Background technology
The principal character of Digital Television is the total digitalization processing of program making, transmission, reception and storage.Abundant in content colorful be the key of Digital Television development.Digital Television has also further strengthened the worry of content supplier for digitized content bringing high-quality audio frequency and video effect to the user when.Content supplier thinks in case the audio-video frequency content digitlization, unwarrantedly copies and sells with regard to easier suffering.In fact, no matter be number format or analog format, how protecting the copyright of audio-video frequency content not encroached on, is that film and music dealer make a profit and the matter of utmost importance of surviving.At present, owing to the illegal use of content, greatly affect enthusiasm and the commercial interest of content supplier, also had influence on development.For head it off, adopted the transmission means based on HDCP (High-bandwidth Digital Content Protection High-bandwidth Digital Content Protectio) agreement abroad.The HDCP agreement is the audio-video frequency content of protecting on the high frequency interface.From technical elements; famous chip, complete-system vendor have carried out related work in the world; alliance or independent development have been formed; form technical specification and the product of some digital TV contents protections, transmitted and received chip such as a series of HDMI with the HDCP agreement (high-definition media interface) such as AD9889, AD9398 of ADI company.
In view of this, under national audio frequency and video bid committee instructs, set up the UCPS standard group, form Technical specifications.Target is to set up the Digital Television unified content resist technology standard of independent intellectual property right.
The UCPS agreement is the numerical protection agreement with independent intellectual property right that China proposes, and can be used for portable multimedia apparatus to the various multimedia equipments of high definition DTV (Digital Television).UCPS agreement basic ideas are technical specifications etc. outside the analysis, comparator by all kinds of physical interfaces of logarithm word tone video equipment; set up unified content resist technology framework for interfaces such as HDMI, DVI, USB, 1394, CI and Displayport; form independent intellectual property right, construct perfect digital TV contents protection system.Therefore, the verification system for the UCPS agreement is that economic worth is arranged very much down to the chip product exploitation.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of verification system based on the UCPS agreement, can on the basis that guarantees UCPS protocol algorithm speed, reduce the degree of raising difficult questions of UCPS agreement.
For solving the problems of the technologies described above, the verification system based on the UCPS agreement of the present invention comprises:
One FPGA (Field Programmeble Gate Array field programmable gate array) chip, programmable hardware circuit by FPGA forms algorithmic system with software ARM (high-end Reduced Instruction Set Computer) system that operates in FPGA inside, is used for realizing the various algorithms of UCPS agreement;
One HDMI receiving chip and connected HDMI interface, the HDMI receiving chip is connected with fpga chip, is used for receiving the digital video-audio signal, and sends it to fpga chip;
One HDMI sends chip and connected HDMI interface, and HDMI sends chip and is connected with fpga chip, and the digital video-audio signal after the deciphering that fpga chip is sent is sent to the DTV demonstration through the HDMI interface;
One SRAM module is connected with fpga chip, is used for ARM application cache district, and the data buffer area of enciphering and deciphering algorithm, to solve the problem of FPGA off-capacity;
One EEPROM module is connected with fpga chip, is used for storage HDMI configuration parameter;
One MCU configuration module is connected chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used for the state information of configuration initialization HDMI receiving chip, HDMI transmission chip and fpga chip;
One the 2nd EEPROM module is connected chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used for depositing the expanded display recognition data of key and equipment;
Power module is for each module of described verification system provides power supply.
Because the verification system based on the UCPS agreement of the present invention adopts the mode of software and hardware combining to realize Digital Television unified content protection system agreement (UCPS agreement).Realize top layer software to the scheduling of each algorithm by the ARM system, the algorithm that operand is large adopts hardware to realize.The mode of software and hardware combining has reduced UCPS protocol development difficulty on the basis that guarantees UCPS protocol algorithm speed, obtained good technique effect, and test result proves that verification system of the present invention is feasible.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the complete transmission system schematic that consists of according to the UCPS agreement;
Fig. 2 is the verification system structure chart based on the UCPS agreement of the present invention;
Fig. 3 is the verification system theory diagram based on the UCPS agreement of the present invention;
Fig. 4 is HDMI signal line wiring main points;
Fig. 5 is the algorithm structure figure of FPGA system;
Fig. 6 is the program flow diagram of ARM system;
Fig. 7 is Vsyn and the Hsyn signal waveform that receives through AD9389;
Fig. 8 is through the UCPS encryption but the image of not deciphering;
The image that reduces after Fig. 9 process UCPS encryption and decryption.
Embodiment
The UCPS agreement is to realize having the secrecy transmission of audio frequency and video digital content between the legitimate device interface of protection demand, the integrality that the relevant control information of realization digital content is transmitted between the legitimate device interface, the integrality of maintenance system.
Referring to shown in Figure 1, in the digital television signal transmission, finished the integrality of the device systems of transmission and reception by the UCPS agreement.At first after two equipment are authenticated to be legitimate device mutually, audio-video frequency content sends to equipment B from the A2 interface of device A by type X through the B1 of the type X of equipment B interface.Audio-video frequency content is from the S unit of device A, the identification administrative unit of the device A of flowing through, need to judge whether to encrypt, flow to subsequently the A2 interface of device A, transmission medium by the centre is to the B1 interface of equipment B, identification administrative unit by equipment B need to judge whether deciphering, finally arrives the S unit of equipment B.Finished like this transmission according to UCPS actualizing audio-video frequency content.
The UCPS protocol contents comprises:
(1) device authentication: comprise the authentication of the authentication between equipment and its own interfaces, two equipment room interfaces and the authentication of two equipment rooms;
(2) cipher key delivery: comprise that the secrecy transmission of protected content reaches the complete transmission of the control information relevant with this protected content;
(3) system integrity is safeguarded: comprise generation, checking and the renewal of CRL (CRL).
The protection system that is consisted of by the UCPS agreement as can be known, this system needs a pair of encryption and decryption system.Corresponding Hardware Design encrypts transmission board by two almost completely identical circuit boards and the deciphering dash receiver consists of.Accordingly, the verification system based on the UCPS agreement of the present invention also consists of by encrypting transmission board and deciphering dash receiver, as shown in Figure 2.This verification system receives the digital audio-video signal that the HDMI interface by DVD sends out, and after encrypting through the encryption transmission board of verification system, sends to the deciphering dash receiver of verification system by the HDMI interface, sends to DTV by the HDMI interface after the deciphering and shows.This verification system all is comprised of digital circuit, does not contain analog circuit, has both reduced the system difficulty, is convenient to design and development, has guaranteed again systemic-function.
Referring to shown in Figure 3, described verification system is comprised of following part in one embodiment of this invention:
One FPGA (field programmable gate array) chip is selected XC3S5000 type fpga chip in the present embodiment, and it is the signal processing core cell of described verification system, and various UCPS protocol algorithm are all finished in this fpga chip.
One HDMI receiving chip and connected HDMI interface, the HDMI receiving chip is connected with fpga chip, is used for receiving the digital video-audio signal, and sends it to fpga chip;
One HDMI sends chip and connected HDMI interface, and HDMI sends chip and is connected with fpga chip, and the digital video-audio signal after the deciphering that fpga chip is sent is sent to the DTV demonstration through the HDMI interface.
One SRAM module is connected with fpga chip, is used for ARM application cache district, and the data buffer area of enciphering and deciphering algorithm, to solve the problem of FPGA off-capacity.
One EEPROM module is connected with fpga chip, is used for storage HDMI configuration parameter.
One MCU configuration module is connected chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used for the state information of configuration initialization HDMI receiving chip, HDMI transmission chip and fpga chip.
One the 2nd EEPROM module is connected chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used for depositing the expanded display recognition data (EDID) of key and equipment.
Power module is for each module of described verification system provides power supply.
In described verification system design, power module is that system is indispensable and vital, and the power consumption of system also is a key index of system.Not only consider input voltage, output voltage and electric current when selecting power supply, also to think over efficient that the stability, power supply of the total power consumption of system, power supply realizes, power unit to the transient response ability of load variations, Primary Component tolerance and the corresponding power supply ripple that allows to power-supply fluctuation, and heat dissipation problem etc.In verification system of the present invention, need altogether 5 kinds of power supply: 5V, 3.3V, 2.5V, 1.8V, 1.2V.Wherein the 5V power supply is the input power of system, and remaining power supply all is by the 5V power generation.3.3V be the power supply of I/O interface power supply and other chips, 1.2V is the core power of FPGA.3.3V and the 1.2V power is larger, all adopts high power D C-DC power conversion chip, to improve power-efficient, reduces power consumption and heat.
Need the test signal point in the system debug process for making things convenient for, whether (be used for checking FPGA in the debug phase works 8 LED lamps of special increase in verification system of the present invention; Be used to indicate the state of system's operation in the verification system normal work period) and 30 signal testing points.Described LED lamp and signal testing point all are connected on the vacant I/O interface of FPGA or draw from the vacant I/O interface of FPGA.
Because the HDMI interface can be realized hot plug, so when system, considered the anti-plug discharge performance of antistatic of system.Being interfaced at HDMI has increased anti-static precautions and (has received joint to having increased antistatic protection chip CM2021 between the HDMI receiving chip at HDMI between the HDMI main control chip (namely receiving and send chip); send chip at HDMI and between HDMI transmission joint, increased antistatic protection chip CM2020); the system that can guarantee so can not destroy Systems balanth because of the plug joint in the course of the work, strengthens the anti-interference of system.
In described verification system, the HDMI transmission speed can be up to 4G, need to think better of for the wiring of 4 pairs of differential lines of HDMI main control chip.The transfer impedance of at first guaranteeing these 4 pairs of differential lines remains on about 50 ohm, differential pair transmission line via hole definitely can not occur (when via hole refers to the design circuit plate when wiring simultaneously, a holding wire need to be when two copper layer wirings, need to realize by beating a via hole continuity of same signal between the different Cu layer) situation, if there is via hole must cause the motional impedance of transmission line to guarantee, its consequence is to cause high frequency radiation serious, transmission bandwidth descends, even whole system can't normally be moved.Fig. 4 is the wiring of HDMI interface and the difference transmission lines between the AD9381 chip (the AD9381 chip is the HDMI receiving chip) of verification system, because clock (clock) differential lines can't realize connecting up in order, need to realize the atresia wiring around half-turn, other 3 pairs of data (data) differential lines all can connect up in order.
FPGA need to receive 24 parallel-by-bit data, and these data frequencys will be up to 165M, and single-ended signal so at a high speed needs to consider the transmission DYNAMIC REFLECTION PROPERTY of signal, to guarantee the quality of signal transmission.In verification system of the present invention, adopted three kinds of modes to guarantee signal performance:
(1) in signal source termination 22～56 Ohmic resistances, determined that by emulation mode the resistance of terminating resistor is 33 ohm by circuit design simulation software.The signal source refers to the data-signal of HDMI receiving chip after deciphering.
(2) signal transmssion line is short as far as possible, and the synchronous signal live width is consistent, and it is substantially isometric that line length keeps, and guarantees the impedance of transmission.
(3) integrality on maintenance stratum in the HW High Way zone guarantees the signal transmission integrity.
FPGA processes core cell as signal, directly crucial success or failure to system.And key factor of FPGA application design is exactly the power configuration to FPGA, and wherein the use of filter capacitor is again the important indicator of power source performance.Therefore, in the present invention to the filter capacitor of every kind of power supply of FPGA all need to distribute three kinds of 0.1uF, 10uF and 47uF etc., wherein 47uF electric capacity should be tried one's best and be arranged near the FPGA back side, and the power pin of accomplishing as far as possible each chip disposes a 0.1uF electric capacity, to guarantee the power supply performance of power supply, guarantee that FPGA can normally move.
All algorithms of UCPS agreement all are in the inner realization of FPGA.These algorithms comprise:
(A) software is finished ECVP (elliptic curve verification algorithm) digital verification and ECSP (ellipse curve signature algorithm) digital signature;
(B) software is finished HMAC-256 (256 hash messages are confirmed) hash algorithm;
(C) hardware is realized AES (superencipherment algorithm) and stream enciphering and deciphering algorithm.
Wherein ECVP digital verification and ECSP Digital Signature Algorithm comprise:
(a) software is finished SHA-1 (Secure Hash Algorithm) algorithm;
(b) the software and hardware combining mode is finished the scalar multiplication based on ECC (elliptic curve cipher system);
(c) hardware is realized large digital-to-analogue multiplication algorithm;
(d) hardware is realized the mould algorithm for inversion;
(e) hardware realizes that random number produces algorithm.
And in the HMAC-256 hash algorithm, then comprised the SHA-256 algorithm of being realized by software.
Above described algorithm realized by the hardware circuit of FPGA and the software ARM system that operates in FPGA inside.The algorithmic system structured flowchart of FPGA as shown in Figure 5.
Software ARM system is the scheduling controller of described algorithmic system as the top layer of algorithmic system, finishes cooperation and the scheduling of all hardware algorithm; Hardware circuit is as the bottom of algorithmic system; Carry out communication by 32 bit data bus and 32 bit address buses between the two.
In software ARM system, by the C code each algorithm is dispatched.The scheduling problem that adopts software view to solve algoritic module can be avoided very complicated state machine occurring by the hardware scheduling of FPGA, reduces the exploitation debugging difficulty.In software ARM system, need the algorithm of operation that HMAC-256 hash algorithm, ECVP digital verification and ECSP digital signature and SHA-1 algorithm (" dot product " and " times point " is the subalgorithm of " scalar multiplication " in Fig. 5, carries out data interaction between " scalar multiplication " and " ECVP and ECSP ") are arranged.The algorithm of being realized by programmable hardware circuit has: large digital-to-analogue multiplication algorithm, mould algorithm for inversion function, random number produce algorithm, AES (128) and stream cipher algorithm.Based on the scalar multiplication of ECC by software ARM system and programmable hardware circuit in conjunction with realization.The register tables of programmable hardware circuit is revised by 32 bus read-write modes by software ARM system, calls algorithm and carries out.
Described programmable hardware circuit comprises:
One Register File (register file) chip by bus and software ARM system communication, is taken advantage of function module, mould inverse function module, random number generation function module, safe transmission module to call large digital-to-analogue.
Large digital-to-analogue is taken advantage of function module, is connected with Register File chip, realizes large digital-to-analogue multiplication algorithm.
Mould inverse function module is connected with Register File chip, realizes the mould algorithm for inversion.
Random number generation function module is connected with Register File chip, realizes that random number produces algorithm.
The safe transmission module is connected with Register File chip, realizes AES (128) and stream cipher algorithm.The input of described safe transmission module is connected input video, audio frequency, clock and control signal with the MDMI receiving chip, and its output sends chip with MDMI and is connected output video, audio frequency, clock and control signal.
In software ARM system the control flow of C program in machine code as shown in Figure 6, detailed process is:
Step 3, initialization: initialization UCPS protocol transmission register, reception begins synchronously with transmitting terminal;
Step 4, carry out the UCPS protocol authentication, if protocol authentication not by again authentication otherwise carried out for the 5th step.
Step 5, the transfer of data of carrying out: the audio/video flow transmission ends is encrypted, and receiving terminal is decrypted.
The verification system platform is made of verification system, DVD (digital video disk (DVD)), DTV (Digital Television) respectively.PC by RS232 respectively with verification system in densifying plate and deciphering plate communication, with the control verification system and can obtain the running status of current verification system.By oscilloscope can the testing authentication system signal performance.Fig. 7 is FPGA Vsyn and the Hsyn signal out by the AD9389 reception that oscilloscope detects.Signal quality or extraordinary as can be seen from Figure 7, the edge is very steep, and signal peak is little, and transitional processes is short.Can find out that designed system satisfies the hardware designs demand aspect signal transmission performance.
In the situation that signal meets the demands, begin to test the UCPS agreement, the fixing vision signal that DVD is sent out shows at DTV.Fig. 8 is the image of not deciphering after encrypting through UCPS, and Fig. 9 deciphers again the image that restores after encrypting through UCPS.Contrast this 2 width of cloth image as can be known, only through encrypting not the image of deciphering be rambling, basic None-identified, Fig. 9 is then very clear, has reduced the DVD image.
Test result shows that the verification system based on the UCPS agreement of the present invention can correctly realize the UCPS protocol algorithm, for realizing that chip-scale provides good Front-end Design, for the development of domestic Digital Television industry plays an important role, also possess good market prospects simultaneously.
Below in conjunction with specific embodiments the present invention is had been described in detail, these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should belong to protection scope of the present invention.
Claims (9)
1. the verification system based on the UCPS agreement is characterized in that, comprising:
One fpga chip forms algorithmic system by the programmable hardware circuit of FPGA and the software ARM system that operates in FPGA inside, is used for the various algorithms of realization UCPS agreement;
One HDMI receiving chip and connected HDMI interface, the HDMI receiving chip is connected with fpga chip, is used for receiving the digital video-audio signal, and sends it to fpga chip;
One HDMI sends chip and connected HDMI interface, and HDMI sends chip and is connected with fpga chip, and the digital video-audio signal after the deciphering that fpga chip is sent is sent to the DTV demonstration through the HDMI interface;
One SRAM module is connected with fpga chip, is used for the data buffer area of buffer memory ARM application program and enciphering and deciphering algorithm;
One EEPROM module is connected with fpga chip, is used for storage HDMI configuration parameter;
One MCU configuration module is connected chip by bus with HDMI receiving chip, fpga chip and HDMI and is connected, and is used for the state information of configuration initialization HDMI receiving chip, HDMI transmission chip and fpga chip;
One the 2nd EEPROM module is connected chip by bus with HDMI receiving chip, fpga chip and HDMI and is connected, and is used for depositing the expanded display recognition data of key and equipment;
Power module is for each module of described verification system provides power supply.
2. the verification system based on the UCPS agreement as claimed in claim 1, it is characterized in that: described power supply comprises: 5V, 3.3V, 2.5V, 1.8V, 1.2V; Wherein the 5V power supply is the input power of system, and remaining power supply is all by the 5V power generation; 3.3V power supply is the power supply of I/O interface power supply and other chips, 1.2V is the core power of FPGA.
3. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: be provided with 8 LED lamps and 30 signal testing points in the described verification system; Whether 8 LED lamps are used for checking FPGA in the debug phase and work, and are used to indicate the state of system's operation in the verification system normal work period; Described LED lamp and signal testing point all are connected on the I/O interface of FPGA or draw from the FPGAI/O interface.
4. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: described HDMI receiving chip and HDMI send chip and have respectively 4 pairs of differential signal lines, and the transfer impedance of this differential signal line is 50 ohm.
5. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: signal source termination 22～56 Ohmic resistances of described verification system.
6. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: for every kind of power supply of FPGA power supply is provided with 0.1 μ F, 10 μ F and three kinds of filter capacitors of 47 μ F, the power pin of each chip disposes 0.1 a μ F filter capacitor.
7. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that:
Described software ARM system is the scheduling controller of described algorithmic system as the top layer of algorithmic system, finishes cooperation and the scheduling of all hardware algorithm; Hardware circuit is as the bottom of algorithmic system; Carry out communication by 32 bit data bus and 32 bit address buses between the two;
The algorithm of being realized by software ARM system comprises: HMAC-256 hash algorithm, ECVP digital verification and ECSP digital signature and SHA-1 algorithm; In the HMAC-256 hash algorithm, comprised the SHA-256 algorithm of being realized by software; In software ARM system, by the C code each algorithm is dispatched;
The algorithm of being realized by programmable hardware circuit has: large digital-to-analogue multiplication algorithm, mould algorithm for inversion function, random number produce algorithm, AES and stream cipher algorithm;
Based on the scalar multiplication of ECC by software ARM system and programmable hardware circuit in conjunction with realization;
The register tables of programmable hardware circuit is revised by 32 bus read-write modes by software ARM system, calls algorithm and carries out.
8. such as claim 1 or 7 described verification systems based on the UCPS agreement, it is characterized in that:
Described programmable hardware circuit comprises:
One Register File chip by bus and software ARM system communication, is taken advantage of function module, mould inverse function module, random number generation function module, safe transmission module to call large digital-to-analogue;
Large digital-to-analogue is taken advantage of function module, is connected with Register File chip, realizes large digital-to-analogue multiplication algorithm;
Mould inverse function module is connected with Register File chip, realizes the mould algorithm for inversion;
Random number generation function module is connected with Register File chip, realizes that random number produces algorithm;
The safe transmission module is connected with Register File chip, realizes AES and stream cipher algorithm; The input of described safe transmission module is connected input video, audio frequency, clock and control signal with the HDMI receiving chip, and its output sends chip with HDMI and is connected output video, audio frequency, clock and control signal.
9. the verification system based on the UCPS agreement as claimed in claim 7, it is characterized in that: the detailed process of the various algorithms of control of described C code is: ARM powers on; Configuration function; Initialization; Carry out the UCPS protocol authentication; Carry out transfer of data.
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| CN102184158B (en) * | 2011-03-31 | 2014-04-23 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN102222032B (en) * | 2011-05-20 | 2013-10-30 | 哈尔滨工业大学 | Fault injection method of fault injection device of 1394 bus |
| CN103632103B (en) * | 2013-06-07 | 2016-08-24 | 中国科学院电子学研究所 | A kind of real time data safety device and method thereof |
| CN104050068B (en) * | 2014-05-23 | 2016-06-15 | 北京兆易创新科技股份有限公司 | The method of FPGA Debugging and device in MCU chip |
| CN104184578B (en) * | 2014-07-30 | 2017-07-07 | 山东大学 | A kind of Elliptic Curve Scalar Multiplication method accelerating circuit and its algorithm based on FPGA |
| CN105376061B (en) * | 2015-10-10 | 2019-02-01 | 广州慧睿思通信息科技有限公司 | A kind of decryption hardware platform based on FPGA |
| CN111258511B (en) * | 2020-01-10 | 2023-05-05 | 武汉先同科技有限公司 | HDMI transmission printing protocol-based implementation method |
| CN113010142B (en) * | 2021-03-23 | 2023-07-28 | 广州万协通信息技术有限公司 | Novel pulse node type scalar dot multiplication double-domain implementation system and method |
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