CN101770345B - Method for establishing logical address space, method for access to storage device and storage architecture - Google Patents
Method for establishing logical address space, method for access to storage device and storage architecture Download PDFInfo
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Abstract
The invention provides a method for establishing a logical address space for a controller using a PCIE protocol, which comprises the following steps that: a first controller using the PCIE protocol obtains the parameters of a storage device with PCIE protocol ports controlled by the first controller; and the first controller maps a storage space of the storage device into a first logical address space of the first controller according to the parameters. The invention also provides an access method of three controllers using PCIE protocols and a controller using a PCIE protocol to the storage device with the PCIE protocol ports, and two storage architectures. The invention can improve the efficiency of access to the storage device with the PCIE protocol ports.
Description
Technical field
The present invention relates to memory technology, relate in particular to the method for setting up logical address space, the method and the storage architecture of access to storage device.
Background technology
Present storage architecture mainly comprises controller and memory storage, and memory storage for example is a hard disk.When needs, controller can access to storage device.For example, after the read data request that controller acquisition server sends, controller can provide said data to the memory storage request, and after memory storage offered controller with said data, controller provided said data to server again.Again for example, after the write data requests that controller acquisition server sends, controller can be stored said data to the memory storage request; After the said data of memory device stores; Can return the write data response to controller, afterwards, controller returns the write data response to server again.
The inventor finds in realizing process of the present invention: use Peripheral Component Interconnect (PCIE fast; When Peripheral Component Interconnect Express) the each visit of the controller of agreement has the memory storage of PCIE protocol port; All need carry out alternately with memory storage; At least controller need send request to memory storage, and thisly must need the regular hour alternately.When controller needs the frequent visit memory storage, because the each access to storage device of controller all needs the regular hour, so the efficient of controller access memory storage must descend.
Summary of the invention
Method and storage architecture that the controller access that the embodiment of the invention provides method that the controller that uses the PCIE agreement sets up logical address space, use the PCIE agreement has the memory storage of PCIE protocol port use the controller access of PCIE agreement to have the efficient of the memory storage of PCIE protocol port in order to improve.
A kind of controller of the PCIE of use agreement is set up the method for logical address space, comprising: first controller of use PCIE agreement obtains the parameter of the memory storage with PCIE protocol port of its control; Said first controller is according to said parameter; The storage space of said memory storage is mapped to first logical address space of said first controller; The size of said first logical address space is big or small identical with the storage space of said memory storage; And the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage is so that said first controller is controlled said memory storage through operating first logical address space.
A kind of first controller that uses the PCIE agreement comprises: obtain the unit, be used to obtain the parameter of the memory storage with PCIE protocol port of said first controller control; Map unit; Be used for parameter according to the said memory storage of said acquisition unit acquisition; The storage space of said memory storage is mapped to first logical address space of said first controller; The size of said first logical address space is big or small identical with the storage space of said memory storage; And the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage is so that said first controller is controlled said memory storage through operating first logical address space.
A kind of controller access of the PCIE of use agreement has the method for the memory storage of PCIE protocol port; First controller that uses the PCIE agreement is mapped to the storage space of the memory storage of its control first logical address space of said first controller in advance; The size of said first logical address space is big or small identical with the storage space of said memory storage; And the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage, said method comprises: said first controller obtains the triggering of the said memory storage of visit; Said first logical address space of said first controller access is so that said first controller is controlled said memory storage through operating first logical address space.
A kind of first controller that uses the PCIE agreement; Comprise: map unit; Be used for the storage space of the memory storage with PCIE protocol port of said first controller control is mapped to first logical address space of said first controller; The size of said first logical address space is big or small identical with the storage space of said memory storage, and the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage; Obtain the unit, be used to obtain to visit the triggering of said memory storage; Addressed location is used for after said acquisition unit obtains the triggering of the said memory storage of visit, visiting said first logical address space, so that said first controller is controlled said memory storage through operating first logical address space.
A kind of storage architecture comprises: the memory storage that at least one has the PCIE protocol port is used to store data; Use first controller of PCIE agreement; Be used to control said memory storage; Wherein, Said first controller is mapped to first logical address space of said first controller with the storage space of said memory storage, and the size of said first logical address space is big or small identical with the storage space of said memory storage, and the data consistent stored of the data of said first logical address space storage and the storage space of said memory storage; Obtain the triggering of the said memory storage of visit when said first controller after, visit said first logical address space, so that said first controller is controlled said memory storage through operating first logical address space.
In embodiments of the present invention; Owing to have the logical address space that the storage space of the memory storage of PCIE protocol port is mapped to the controller that uses the PCIE agreement; So using the controller access of PCIE agreement to be mapped to local logical address space is exactly in fact the memory storage that visit has the PCIE protocol port; This shows; The memory storage that the controller access of use PCIE agreement has the PCIE protocol port needn't send request to the memory storage with PCIE protocol port again, has reduced and has visited the needed time of memory storage with PCIE protocol port, has improved visit and has had the efficient of the memory storage of PCIE protocol port.
The embodiment of the invention also provides a kind of memory storage, and said memory storage has a plurality of PCIE protocol ports, and said memory storage connects a controller that uses the PCIE agreement respectively through each PCIE protocol port.
The embodiment of the invention also provides a kind of storage architecture, comprising: the memory storage that at least one has a plurality of PCIE protocol ports is used to store data; Use first controller of PCIE agreement, be used for the said memory storage of first port controlling through said memory storage; Use second controller of PCIE agreement, be used for the said memory storage of second port controlling through said memory storage.
In embodiments of the present invention, memory storage has a plurality of PCIE protocol ports, and like this, memory storage can be controlled by the controller of a plurality of use PCIE agreements simultaneously.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 sets up the process flow diagram of the method for logical address space for the controller of a kind of PCIE of use agreement of the embodiment of the invention;
Fig. 2 is a kind of structural representation that uses the controller of PCIE agreement of the embodiment of the invention;
Fig. 3 is the process flow diagram of method of a kind of controller access memory storage of the embodiment of the invention;
Fig. 4 is the structural representation of the another kind of controller of the embodiment of the invention;
Fig. 5 is the structural representation of a kind of storage architecture of the embodiment of the invention;
Fig. 6 is the structural representation of a kind of middle-end storage architecture of the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The method of at first controller of a kind of PCIE of use agreement of the embodiment of the invention being set up logical address space describes.As shown in Figure 1, comprising:
S101: first controller of use PCIE agreement obtains the parameter of the memory storage with PCIE protocol port of its control, and for ease of describing, the memory storage with PCIE protocol port of the embodiment of the invention that hereinafter relates to all abbreviates memory storage as;
S102: said first controller is mapped to the storage space of said memory storage first logical address space of said first controller according to said parameter.
First controller here and memory storage can be meant controller and the memory storage in the middle-end storage architecture respectively; Wherein, First controller can be the controller that comprises PCIE switch (Switch); Memory storage can be the solid state hard disc (SSD, Solid State Disk) with PCIE protocol port.Certainly; First controller here and memory storage also can be meant controller and the memory storage in other storage architectures; As long as the controller in this storage architecture can the control store device; Controller can be mapped to controller with the storage space of memory storage, and controller and memory storage all use the PCIE agreement to get final product.
The first controller control store device can have a lot of implementations.For example, first controller provides data according to the read data request of server to the memory storage request.Again for example, first controller is asked the memory device stores data according to the write data requests of server.Certainly, first controller can also come the control store device through other modes, illustrates no longer one by one here.
Memory storage can have a plurality of PCIE protocol ports; First controller can (be described for ease of hereinafter through one of them port; Here be called first port) obtain the parameter of memory storage; Concrete, parameter for example is used for the storage space of memory storage is mapped to the parameter of the logical address space of first controller for the capacity of memory storage, sequence number and position (for example groove position) etc.Here need to prove that the storage space of memory storage is mainly used in the storage data, certainly; The storage space of memory storage also can comprise configuration space; Be used to store some configuration informations, for example, the SSD with PCIE protocol port just has the configuration space that is used for storage configuration parameter.First controller can be through memory storage first port storage space of memory storage is mapped to first logical address space.The size of first logical address space in first controller after the mapping can be with the storage space of memory storage big or small identical; And the data consistent of the storage space storage of the data of first logical address space storage and memory storage; Like this, first controller can come the control store device through operating first logical address space.For example, when first controller need be from the memory storage read data, can be equal to from the memory storage read data directly from the first logical address space read data.Again for example, when first controller need be to the memory storage write data, can directly data be write first logical address space, be equal to the memory storage write data.Here need to prove that logical address space is a notion in logic, in fact the logical address space that the storage space of SSD is mapped to controller is exactly the logical space of setting up corresponding storage space physically.
In the prior art, a memory storage can be controlled by a plurality of controllers.Sometimes; Controller may the uncontrollable memory storage that it can be controlled originally; For example; Being connected and may breaking down between the memory storage of said controller and its control still can continue the control store device for guaranteeing this controller, and controller can be controlled this memory storage through another controller of controlling this memory storage.For example; When controller obtain the request that server sends and confirm with memory storage between be connected break down after; Request is issued another controller of this memory storage of control; Another controller sends request to this memory storage again, after data that another this memory storage of controller acquisition provides or the response of sending, again data or response is issued the controller that obtains server requests.
When embodiment of the present invention embodiment, also may occur breaking down and the phenomenon of uncontrollable memory storage between the memory storage of a controller and its control.For addressing this problem; First controller is mapped to first logical address space except that direct storage space with memory storage; Can also set up second logical address space of coming from second controller mapping of the use PCIE agreement of control store device, said second logical address space is the logical address space that said second controller is mapped to the storage space of said memory storage said second controller.That is to say; Second controller also can (be described for ease of hereinafter through another port of above-mentioned memory storage; Here be called second port) obtain the parameter of above-mentioned memory storage; And the storage space of above-mentioned memory storage is mapped to the logical address space of said second controller through second port, afterwards, the logical address space after will shining upon again is mapped to second logical address space of said first controller.Like this, said first controller has the logical address space of two above-mentioned memory storages of correspondence in fact.When said first controller did not break down with being connected of above-mentioned memory storage; Said first controller can come the control store device through operating first logical address space; Actual be equal to said first controller through with the direct control store device that is connected of memory storage; In case said first controller broke down with being connected of above-mentioned memory storage; So said first controller just comes the control store device through operating second logical address space, actually is equal to said first controller through the second controller control store device.
From the above, since first controller can come the control store device through second controller, second controller can come the control store device through said first controller too so.For guarantee second controller with memory storage between be connected when breaking down, can continue the control store device, said first controller can cooperate second controller first logical address space to be mapped to the logical address space of second controller.Like this, though second controller with memory storage between be connected and break down, second controller also can come the control store device through the logical address space that operation is come from said first controller mapping.
Because second controller and first controller can be controlled same memory storage, so the associated description of second controller can be repeated no more with reference to above-mentioned description to first controller here.
Need to prove; Memory storage among S101 and the S102 can be a plurality of memory storages; That is to say that first controller can be controlled a plurality of memory storages simultaneously, also can the storage space of a plurality of memory storages be mapped to the logical address space of first controller.In addition, second controller can together be controlled a plurality of memory storages with first controller.
Corresponding to method shown in Figure 1; The embodiment of the invention also provides a kind of first controller of the PCIE of use agreement; As shown in Figure 2, comprising: parameter obtains unit 21, is used to obtain the parameter of the memory storage with PCIE protocol port of said first controller control; Map unit 22 is used for the parameter according to the said memory storage of said parameter acquisition unit 21 acquisitions, the storage space of said memory storage is mapped to first logical address space of said first controller.
Correspondence with method shown in Figure 1 is described the same; First controller here and memory storage can be meant controller and the memory storage in the middle-end storage architecture respectively; Wherein, First controller can be the controller that comprises the PCIE switch, and at this moment, memory storage can be the SSD with PCIE protocol port.Certainly; First controller here and memory storage also can be meant controller and the memory storage in other storage architectures; As long as the controller in this storage architecture can the control store device; Controller can be mapped to controller with the storage space of memory storage, and controller and memory storage all use the PCIE agreement to get final product.
The first controller control store device can have a lot of implementations.For example, first controller provides data according to the read data request of server to the memory storage request.Again for example, first controller is asked the memory device stores data according to the write data requests of server.Certainly, first controller can also come the control store device through other modes, illustrates no longer one by one here.
Memory storage can have a plurality of PCIE protocol ports; Parameter obtains unit 21 and can (describe for ease of hereinafter through one of them port; Here be called first port) obtain the parameter of memory storage; Concrete, parameter for example is used for the storage space of memory storage is mapped to the parameter of the logical address space of first controller for the capacity of memory storage, sequence number and position (for example groove position) etc.Here need to prove that the storage space of memory storage is mainly used in the storage data, certainly; The storage space of memory storage also can comprise configuration space; Be used to store some configuration informations, for example, the SSD with PCIE protocol port just has the configuration space that is used for storage configuration parameter.
Map unit 22 can be through memory storage first port storage space of memory storage is mapped to first logical address space.The size of first logical address space in first controller after map unit 22 mapping can be with the storage space of memory storage big or small identical; And the data consistent of the storage space storage of the data of first logical address space storage and memory storage; Like this, first controller can come the control store device through the logical address space after the operation map.For example, when first controller need be from the memory storage read data, can be equal to from the memory storage read data directly from the first logical address space read data.Again for example, when first controller need be to the memory storage write data, can directly data be write first logical address space, be equal to the memory storage write data.
Here need to prove that logical address space is a notion in logic, in fact the logical address space that the storage space of SSD is mapped to controller is exactly the logical space of setting up corresponding storage space physically.
Map unit 22 is mapped to first logical address space except that direct storage space with memory storage; Can also set up second logical address space of coming from second controller mapping of the use PCIE agreement of control store device, said second logical address space is the logical address space that said second controller is mapped to the storage space of said memory storage said second controller.That is to say; Second controller also can (be described for ease of hereinafter through another port of above-mentioned memory storage; Here be called second port) obtain the parameter of above-mentioned memory storage; And the storage space of above-mentioned memory storage is mapped to the logical address space of said second controller through second port, afterwards, the logical address space after will shining upon again is mapped to second logical address space of said first controller.Like this, said first controller has the logical address space of two above-mentioned memory storages of correspondence in fact.When said first controller did not break down with being connected of above-mentioned memory storage; Said first controller can come the control store device through operating first logical address space; Actual be equal to said first controller through with the direct control store device that is connected of memory storage; In case said first controller broke down with being connected of above-mentioned memory storage; So said first controller just comes the control store device through operating second logical address space, actually is equal to said first controller through the second controller control store device.
From the above, since first controller can come the control store device through second controller, second controller can come the control store device through said first controller too so.For guarantee second controller with memory storage between be connected when breaking down, can continue the control store device, map unit 22 can be mapped to first logical address space logical address space of second controller.Like this, though second controller with memory storage between be connected and break down, second controller also can come the control store device through the logical address space that operation is come from said controller mapping.
Because second controller and said first controller can be controlled same memory storage, so the associated description of second controller can be repeated no more with reference to above-mentioned description to said first controller here.
Need to prove that first controller can be controlled a plurality of memory storages simultaneously, also can the storage space of a plurality of memory storages be mapped to the logical address space of first controller.In addition, second controller can together be controlled a plurality of memory storages with first controller.
In practical application, controller must access to storage device for the control store device.To this; The embodiment of the invention also provides a kind of controller access of the PCIE of use agreement to have the method for the memory storage of PCIE protocol port; The precondition of implementing this method is; First controller that uses the PCIE agreement is mapped to the storage space of the memory storage of its control first logical address space of said first controller in advance, and is as shown in Figure 3, comprising:
S301: said first controller obtains the triggering of the said memory storage of visit;
S302: said first logical address space of said first controller access.
First controller here and memory storage can be meant controller and the memory storage in the middle-end storage architecture respectively, and wherein, first controller can be the controller that comprises the PCIE switch, and memory storage can be the SSD with PCIE protocol port.Certainly; First controller here and memory storage also can be meant controller and the memory storage in other storage architectures; As long as the controller in this storage architecture can the control store device; Controller can be mapped to controller with the storage space of memory storage, and controller and memory storage all use the PCIE agreement to get final product.
The size of first logical address space in first controller after the mapping can be with the storage space of memory storage big or small identical; And the data consistent of the storage space storage of the data of first logical address space storage and memory storage; Like this, first controller can visit memory storage through visiting first logical address space.For example, when first controller need be from the memory storage read data, can be equal to from the memory storage read data directly from the first logical address space read data.Again for example, when first controller need be to the memory storage write data, can directly data be write first logical address space, be equal to the memory storage write data.
Here need to prove that logical address space is a notion in logic, in fact the logical address space that the storage space of SSD is mapped to controller is exactly the logical space of setting up corresponding storage space physically.
The triggering of the said memory storage of visit that said first controller obtains can be the triggering of various ways, for example, obtains the request that server sends, and request can be a read data request, also can be write data requests, can also be other requests.Certainly, triggering can also be the other forms of triggering that can make said first controller access, first logical address space, illustrates no longer one by one here.
Said first logical address space of said first controller access also can have various ways.For example, if said first controller obtains the read data request that server sends, then said first controller obtains the data that said server need obtain from said first logical address space; If said first controller obtains the write data requests that server sends, the data that then said first controller need be stored said server are written to said first logical address space.
Said first controller can also be set up second logical address space of coming from second controller mapping of the use PCIE agreement of controlling said memory storage in advance, and said second logical address space is the logical address space that said second controller is mapped to the storage space of said memory storage said second controller.That is to say; Second controller of controlling above-mentioned memory storage also can obtain the parameter of above-mentioned memory storage through a port of above-mentioned memory storage; The storage space of above-mentioned memory storage is mapped to the logical address space of said second controller; Afterwards, the logical address space after will shining upon again is mapped to second logical address space of said first controller.Like this, said first controller has the logical address space of two above-mentioned memory storages of correspondence in fact.When said first controller can't be visited the storage space of above-mentioned memory storage; When for example breaking down with being connected of above-mentioned memory storage owing to said first controller; So said first controller is just visited second logical address space and is realized access to storage device, actually is equal to said first controller through the second controller access memory storage.
Because second controller and first controller can be controlled same memory storage, so the associated description of second controller can be repeated no more with reference to above-mentioned description to first controller here.
Need to prove that the memory storage among the S301 can be a plurality of memory storages, that is to say that first controller can be controlled a plurality of memory storages simultaneously, also can the storage space of a plurality of memory storages be mapped to the logical address space of first controller.In addition, second controller can together be controlled a plurality of memory storages with first controller.
Corresponding to method shown in Figure 3, the embodiment of the invention provides a kind of first controller of the PCIE of use agreement.As shown in Figure 4, comprising: map unit 41 is used for the storage space of the memory storage with PCIE protocol port of said first controller control is mapped to first logical address space of said first controller; Trigger obtaining unit 42, be used to obtain to visit the triggering of said memory storage; Addressed location 43 is used for after said triggering obtains the triggering of the said memory storage of unit 42 acquisition visits, visiting said first logical address space.
First controller here and memory storage can be meant controller and the memory storage in the middle-end storage architecture respectively, and wherein, controller can be the controller that comprises the PCIE switch, and memory storage can be the SSD with PCIE protocol port.Certainly; First controller here and memory storage also can be meant controller and the memory storage in other storage architectures; As long as the controller in this storage architecture can the control store device, map unit 41 can be mapped to the storage space of memory storage controller and controller and memory storage and all use the PCIE agreement to get final product.
The size of first logical address space in first controller after map unit 41 mapping can be with the storage space of memory storage big or small identical; And the data consistent of the storage space storage of the data of first logical address space storage and memory storage; Like this, addressed location 43 can be realized access to storage device through visiting first logical address space.For example, when addressed location 43 need be from the memory storage read data, addressed location 43 can be equal to from the memory storage read data directly from the first logical address space read data.Again for example, when addressed location 43 need be to the memory storage write data, addressed location 43 can directly be write first logical address space with data, is equal to the memory storage write data.
Here need to prove that logical address space is a notion in logic, in fact the logical address space that the storage space of SSD is mapped to controller is exactly the logical space of setting up corresponding storage space physically.
The triggering that triggers the said memory storage of visit that obtains unit 42 acquisitions can be the triggering of various ways; For example, trigger obtaining the request that unit 42 acquisition servers send, request can be a read data request; Also can be write data requests, can also be other requests.Certainly, triggering can also be the other forms of triggering that can make said first controller access, first logical address space, illustrates no longer one by one here.
Said first logical address space of addressed location 43 visits also can have various ways.For example, obtain the read data request that unit 42 acquisition servers send if trigger, then addressed location 43 obtains the data that said server need obtain from first logical address space; Obtain the write data requests that servers send if trigger to obtain unit 42, then addressed location 43 data that said server need be stored are written to first logical address space.
Because second controller and said controller can be controlled same memory storage, so the associated description of second controller can be repeated no more with reference to above-mentioned description to said controller here.
Need to prove that first controller can be controlled a plurality of memory storages simultaneously, also can the storage space of a plurality of memory storages be mapped to the logical address space of first controller.In addition, second controller can together be controlled a plurality of memory storages with first controller.
Description by top is not difficult to find out that the embodiment of the invention has related to two controllers and a memory storage at least, so the embodiment of the invention also provides a kind of storage architecture.As shown in Figure 5, said storage architecture comprises: the memory storage 53 that at least one has the PCIE protocol port is used to store data; Use first controller 51 of PCIE agreement, be used to control said memory storage 53, wherein, said first controller 51 is mapped to the storage space of said memory storage 53 first logical address space of said first controller 51; After said first controller 51 obtains the triggering of the said memory storage 53 of visit, visit said first logical address space.
Said storage architecture can also comprise second controller 52 that uses the PCIE agreement; Be used to control said memory storage 53; Wherein, Second controller 52 is mapped to the logical address space of said second controller 52 with the storage space of said memory storage 53, and cooperates logical address space after said first controller 51 will shine upon to be mapped to second logical address space of said first controller 51 again.After said first controller 51 obtains the triggering of the said memory storage 53 of visit,, then visit said second logical address space if can't visit said first logical address space.
Said first controller 51 can be for comprising the controller of PCIE switch; Said second controller 52 also can be for comprising the controller of PCIE switch; Said memory storage 53 is for having the SSD of PCIE protocol port; Said first controller 51 can be controlled said memory storage through it PCIE switch that comprises; Said second controller 52 also can be controlled said memory storage through it PCIE switch that comprises, the logical address space after said second controller 52 can will shine upon through it PCIE switch that comprises is mapped to second logical address space of said first controller 51 again.
To the associated description of first controller 51, second controller 52 and memory storage 53 can referring among top 4 embodiment about the associated description of controller and memory storage, repeat no more here.For making those skilled in the art more clearly understand the embodiment of the invention, be example with middle-end storage architecture shown in Figure 6 more below, again the embodiment of the invention is described.
As shown in Figure 6, the middle-end storage architecture comprises the SSD of the individual PCIE of the having protocol port of the controller 0 that uses the PCIE agreement, the controller 1 that uses the PCIE agreement and m+1 (m is the integer greater than 0).Controller 0 comprises PCIE switch, PCIE interface card, internal memory, CPU and chipset respectively with controller 1.Certainly, controller 0 can also comprise miscellaneous part with controller 1, and Fig. 6 does not illustrate, and points out no longer one by one here yet.
See also Fig. 6; Controller 0 is mapped to the storage space of SSD0 through the port (for example port A) of SSD0 first logical address space of controller 0; The storage space of SSD1 is mapped to second logical address space of controller 0 through the port A of SSD1; By that analogy, through the port A of SSDm the storage space of SSDm is mapped to (m+1) logical address space of controller 0.Equally; Controller 1 is mapped to the storage space of SSD0 through another port (for example port B) of SSD0 first logical address space of controller 1; The storage space of SSD1 is mapped to second logical address space of controller 1 through the port B of SSD1; By that analogy, through the port B of SSDm the storage space of SSDm is mapped to (m+1) logical address space of controller 1.What controller 0 and controller 1 will be mapped to the inherent logic address space all is mapped to the other side's logical address space corresponding to the storage space of m+1 SSD.
Is example with controller 0 with SSD0, and when controller 0 needed through port A visit SSD0,0 of controller needed visit through port A the storage space of SSD0 to be mapped to local logical address space, actual being equal to through port A visit SSD0.When controller 0 needed through controller 1 visit SSD0,0 of controller needed visit through controller 1 storage space of SSD0 to be mapped to local logical address space, actual being equal to through controller 1 visit SSD0.
In addition, all accomplishing alternately between mutual and controller and the SSD between controller 0 and the controller 1 through the PCIE switch.
In the embodiment shown in fig. 6; The storage space of SSD is mapped to the logical address space of controller through the PCIE switch; To the operating system (OS, Operation System) of controller, access map is to the actual storage space that is equivalent to visit SSD of the logical address space of controller.So embodiment shown in Figure 6 can improve access efficiency.
In traditional storage architecture; Traditional controller also comprises devices such as hard disk controller with respect to controller shown in Figure 6; And the request that server sends must be passed through devices such as hard disk controller and could arrive traditional hard disk; Obviously, all to be subject to the performance of devices such as hard disk controller, and ask to arrive the speed that traditional hard disk also can restrict the traditional hard disk of visit through too much device to the performances such as read-write operation of traditional hard disk.And in the embodiment shown in fig. 6, controller can not comprise the devices such as hard disk controller that traditional device is included, can accomplish through the PCIE switch alternately between the mutual and controller between SSD and the controller.So embodiment shown in Figure 6 not only can reduce access path, can also reduce the device that controller comprises, practiced thrift application cost.
Those skilled in the art should be understood that the one access unit of traditional hard disk is a logical block, and the size of most logical blocks is 512 bytes.The one access unit of SSD is a page or leaf, and the size of a page or leaf is 2k byte and 4k byte.In the prior art, when controller need be visited SSD, controller can provide the address of a logical block to SSD, and SSD need be the address of page or leaf with the address translation of logical block, in fact, is traditional hard disk with SSD emulation exactly.Yet the memory management of controller all is unit with the page or leaf, like this; When controller need be visited SSD, it was the address of logical block with the address translation of page or leaf that controller needs elder generation, and SSD is the address of page or leaf with the address translation of logical block again; Obviously, such access mode is too loaded down with trivial details.In the embodiment shown in fig. 6; Because controller will have the logical address space that the storage space of the SSD of PCIE protocol port is mapped to controller, so, when controller need be visited SSD; The OS of controller is the access logic address space directly; Need be not the address of logical block, and the address of logical block is offered SSD, also not need SSD the address of logical block to be converted into the address of page or leaf again the address translation of page or leaf.So embodiment shown in Figure 6 can save the conversion expense, thereby improved the efficient of visiting SSD.
In addition, the embodiment of the invention also provides a kind of memory storage, and said memory storage has a plurality of PCIE protocol ports, and said memory storage connects a controller that uses the PCIE agreement respectively through each PCIE protocol port.
Concrete, said memory storage can be SSD, said SSD can have two PCIE protocol ports.
See also among above-mentioned several embodiment the description of memory storage about the description of memory storage, repeat no more here.
Because memory storage can be arranged in the storage architecture, so the embodiment of the invention also provides a kind of storage architecture, comprising: the memory storage that at least one has a plurality of PCIE protocol ports is used to store data; Use first controller of PCIE agreement, be used for the said memory storage of first port controlling through said memory storage; Use second controller of PCIE agreement, be used for the said memory storage of second port controlling through said memory storage.
Concrete, said memory storage can be SSD, said SSD can have two PCIE protocol ports.
See also among above-mentioned several embodiment the description of memory storage about the description of controller and memory storage, repeat no more here.In the prior art, use the SSD of PCIE agreement to have only a port, and in embodiments of the present invention, a SSD can have a plurality of two PCIE protocol ports, like this, a SSD can be simultaneously by a plurality of controller controls.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method; Be to instruct relevant hardware to accomplish through computer program; Described program can be stored in the computer read/write memory medium; This program can comprise the flow process like the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (17)
1. a controller that uses the PCIE agreement is set up the method for logical address space, it is characterized in that, comprising:
First controller of use PCIE agreement obtains the parameter of the memory storage with PCIE protocol port of its control;
Said first controller is according to said parameter; The storage space of said memory storage is mapped to first logical address space of said first controller; The size of said first logical address space is big or small identical with the storage space of said memory storage; And the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage is so that said first controller is controlled said memory storage through operating first logical address space.
2. the method for claim 1; It is characterized in that; Also comprise: said first controller is set up second logical address space of coming from second controller mapping of the use PCIE agreement of controlling said memory storage, and said second logical address space is the logical address space that said second controller is mapped to the storage space of said memory storage said second controller.
3. the method for claim 1; It is characterized in that; After said first controller is mapped to first logical address space of said controller with the storage space of said memory storage, cooperate second controller of the use PCIE agreement of the said memory storage of control that said first logical address space is mapped to said second controller.
4. like claim 1,2 or 3 described methods, it is characterized in that said memory storage has a plurality of ports;
The parameter that said first controller obtains said memory storage is specially: said first controller obtains the parameter of said memory storage through first port of said memory storage;
Said first controller is specially first logical address space that the storage space of said memory storage is mapped to said first controller: said first controller is mapped to the storage space of said memory storage through said first port first logical address space of said first controller.
5. like claim 1,2 or 3 described methods, it is characterized in that said memory storage is the solid-state hard disk SSD with PCIE protocol port.
6. first controller that uses the PCIE agreement is characterized in that, comprising:
Obtain the unit, be used to obtain the parameter of the memory storage with PCIE protocol port of said first controller control;
Map unit; Be used for parameter according to the said memory storage of said acquisition unit acquisition; The storage space of said memory storage is mapped to first logical address space of said first controller; The size of said first logical address space is big or small identical with the storage space of said memory storage; And the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage is so that said first controller is controlled said memory storage through operating first logical address space.
7. controller as claimed in claim 6 is characterized in that, said memory storage is the SSD with PCIE protocol port.
8. one kind is used the controller access of PCIE agreement to have the method for the memory storage of PCIE protocol port; It is characterized in that; First controller that uses the PCIE agreement is mapped to the storage space of the memory storage of its control first logical address space of said first controller in advance; The size of said first logical address space is big or small identical with the storage space of said memory storage; And the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage, said method comprises:
Said first controller obtains the triggering of the said memory storage of visit;
Said first logical address space of said first controller access is so that said first controller is controlled said memory storage through operating first logical address space.
9. method as claimed in claim 8; It is characterized in that; Said first controller is also set up second logical address space of coming from second controller mapping of the use PCIE agreement of controlling said memory storage in advance, and said second logical address space is the logical address space that said second controller is mapped to the storage space of said memory storage said second controller.
10. method as claimed in claim 9 is characterized in that, said first controller if can't visit said first logical address space, is then visited said second logical address space after obtaining the triggering of the said memory storage of visit.
11., it is characterized in that the triggering that said first controller obtains the said memory storage of visit is specially: said first controller obtains read data request or the write data requests that server sends like any described method of claim 8-10;
Said first logical address space of said first controller access specifically comprises: if said first controller obtains the read data request that server sends, then said first controller obtains the data that said server need obtain from said first logical address space; If said first controller obtains the write data requests that server sends, the data that then said first controller need be stored said server are written to said first logical address space.
12., it is characterized in that said memory storage is the SSD with PCIE protocol port like any described method of claim 8-10.
13. first controller that uses the PCIE agreement is characterized in that, comprising:
Map unit; Be used for the storage space of the memory storage with PCIE protocol port of said first controller control is mapped to first logical address space of said first controller; The size of said first logical address space is big or small identical with the storage space of said memory storage, and the data consistent of the storage space storage of the data of said first logical address space storage and said memory storage;
Obtain the unit, be used to obtain to visit the triggering of said memory storage;
Addressed location is used for after said acquisition unit obtains the triggering of the said memory storage of visit, visiting said first logical address space, so that said first controller is controlled said memory storage through operating first logical address space.
14., it is characterized in that said memory storage is the SSD with PCIE protocol port like any described controller of claim 13.
15. a storage architecture is characterized in that, comprising:
The memory storage that at least one has the PCIE protocol port is used to store data;
Use first controller of PCIE agreement; Be used to control said memory storage; Wherein, Said first controller is mapped to first logical address space of said first controller with the storage space of said memory storage, and the size of said first logical address space is big or small identical with the storage space of said memory storage, and the data consistent stored of the data of said first logical address space storage and the storage space of said memory storage;
Obtain the triggering of the said memory storage of visit when said first controller after, visit said first logical address space, so that said first controller is controlled said memory storage through operating first logical address space.
16. storage architecture as claimed in claim 15; It is characterized in that; Also comprise: use second controller of PCIE agreement, be used to control said memory storage, wherein; Said second controller is mapped to the logical address space of said second controller with the storage space of said memory storage, and cooperates logical address space after said first controller will shine upon to be mapped to second logical address space of said first controller again;
Obtain the triggering of the said memory storage of visit when said first controller after,, then visit said second logical address space if can't visit said said first logical address space that is mapped to.
17. like claim 15 or 16 described storage architectures; It is characterized in that; Said first controller is the controller that comprises the PCIE switch; Said second controller is the controller that comprises the PCIE switch, and said memory storage is the SSD with PCIE protocol port, and said first controller is controlled said memory storage through the PCIE switch that it comprises; Said second controller is controlled said memory storage through the PCIE switch that it comprises, the logical address space after said second controller will shine upon through it PCIE switch that comprises is mapped to second logical address space of said first controller again.
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| CN104951406B (en) * | 2015-06-12 | 2018-05-04 | 上海华为技术有限公司 | A kind of paging type address space menagement method and controller |
| CN108471384B (en) * | 2018-07-02 | 2020-07-28 | 北京百度网讯科技有限公司 | Method and device for forwarding messages for end-to-end communication |
| CN109688214B (en) * | 2018-12-24 | 2021-11-23 | 杭州数梦工场科技有限公司 | Data transmission method, device and storage medium |
| CN112596678B (en) * | 2020-12-24 | 2024-01-16 | 得一微电子股份有限公司 | Storage device, firmware setting method thereof and repartitioning method thereof |
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| CN1285061A (en) * | 1997-12-19 | 2001-02-21 | 霍尼韦尔有限公司 | Systems and methods for synchronizing redundant controllers with minimal control disruption |
| CN101324867A (en) * | 2007-06-16 | 2008-12-17 | 深圳市硅格半导体有限公司 | Device and method for managing data based on semiconductor storage medium |
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| CN1285061A (en) * | 1997-12-19 | 2001-02-21 | 霍尼韦尔有限公司 | Systems and methods for synchronizing redundant controllers with minimal control disruption |
| CN101324867A (en) * | 2007-06-16 | 2008-12-17 | 深圳市硅格半导体有限公司 | Device and method for managing data based on semiconductor storage medium |
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