CN101738994A - Method for transmitting digital signals among solar energy acquisition array controllers - Google Patents
Method for transmitting digital signals among solar energy acquisition array controllers Download PDFInfo
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- 230000005669 field effect Effects 0.000 claims description 8
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/4185—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by the network communication
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/10—Parallel operation of dc sources
- H02J1/102—Parallel operation of dc sources being switching converters
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/31—From computer integrated manufacturing till monitoring
- G05B2219/31094—Data exchange between modules, cells, devices, processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/33—Director till display
- G05B2219/33186—Circuit for signal adaption, voltage level shift, filter noise
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/42—Servomotor, servo controller kind till VSS
- G05B2219/42237—Pwm pulse width modulation, pulse to position modulation ppm
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Abstract
The invention discloses a method for transmitting digital signals among solar energy acquisition array controllers. The method is characterized in that: a main controller is connected in parallel with one or more sub-controllers to a double-strand bus; three level values, a, b and c respectively, are defined on the bus, and the condition that b is greater than a and less than c is satisfied; when the bus is used for supplying power to a direct current supply of the sub-controller, the main controller drives a bus level to the value c and maintains the value; when the bus is used for the main controller to send a command to the sub-controller, the main controller drives the bus to emit widened pulse signals with the levels from b to c; and when the bus is used for the sub-controller to send a response signal to the main controller, the main controller stops driving the bus and the sub-controller which sends the response signal drives the bus to emit the widened pulse signals with the levels from a to b. In the invention, reverse multi-level widened pulses are superposed on a power circuit, so the same double-strand bus transmits power and signals at the same time to realize low cost and reliable work.
Description
Technical field
The present invention relates to digital signal transmission field, be specifically related to the digital signal transmission method between a kind of solar energy acquisition array controllers.
Background technology
The motion tracking solar collection generally need use a plurality of independently optically focused collectors to form arrays, each independently collector by of the tracking of an electronic controller controls to the sun.All controllers all are connected to a master controller, constitute the sub-controller battle array of master controller.Master controller is responsible for the power supply of sub-controller and it is sent instruction, detects the duty of sub-controller simultaneously.Therefore, between master controller and sub-controller, need the digital data transmission passage.
In order to guarantee the signal transmission between each controller, existing way commonly used is to connect one or more signal wire between master controller and each sub-controller except power lead again.The defective of this way is, will lay a large amount of lines between the solar collector, not only increases cost, also increased the failure rate of system.Improved way is not establish special signal wire, but utilizes the power lead transmission signals between the controller.The known for this reason practice is an overlapped high-frequency carrier wave on power lead, by the modulation transmissions digital signal to high frequency carrier.But doing so all will increase modulation-demodulation circuit in each controller, raise the cost equally and increase failure rate, and since solar energy acquisition array take up an area of wider, apart from each other often between the controller, thus high frequency carrier can be introduced inevitably and disturbs the reliability that reduces the signal transmission.
Another problem of signal transmission is the address setting of sub-controller between the controller of solar energy acquisition system.Share at all controllers under the situation of a bars circuit, in order to obtain the respectively control of master controller to each sub-controller, and simultaneously the instruction of master controller is sent answer and caused conflict, each sub-controller must be provided with a unique Signal Message Address for fear of a plurality of sub-controllers.Existing solution is that way by hardware or program setting is its setting address in the production of each sub-controller or when installing.But these schemes all have a series of common defectives: increase cost, reduce reliability, increase the complicacy of installation and maintenance.
Summary of the invention
The object of the present invention is to provide the digital signal transmission method between a kind of solar energy acquisition array controllers, utilize the power circuit transmission of digital signals of sub-controller.
To achieve these goals, technical scheme of the present invention is as follows: the digital signal transmission method between the solar energy acquisition array controllers, solar energy acquisition array controllers comprises master controller and one or more sub-controller, it is characterized in that a master controller and one or more sub-controller are parallel on the bifilar bus; Master controller and each sub-controller can upwards drive bus; Master controller is urged to the c value with bus level and is kept when bus is used for the DC power supply of sub-controller; When being used for master controller master controller driving bus when sub-controller sends instruction, bus makes it to send level by the widened pulse signal of b to c; Stop to drive bus when bus is used for sub-controller master controller when master controller sends recall signal, drive bus by the sub-controller that sends recall signal and make it to send level by the widened pulse signal of a to b, wherein a＜b＜c.
The invention has the advantages that the utilization reverse many level widened pulse that on power circuit, superposes, accomplish to transmit power supply and signal simultaneously with a bifilar bus, with low cost, reliable operation, and can support a kind of automatic signal address setting way of sub-controller.
Description of drawings
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is an example electrical schematic diagram of master controller bus output input of the present invention.
Fig. 3 is an example electrical schematic diagram of sub-controller bus output input of the present invention
Fig. 4 is a bus level waveform example of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is elaborated.
In the accompanying drawing: 1 is bus, 2 is master controller, 3 is sub-controller, 4 is master controller microcontroller chip, 5 is sub-controller microcontroller chip, 6 is the first signal output driving interface of master controller microcontroller chip to bus c level, 7 is the secondary signal output driving interface of master controller microcontroller chip to bus b level, 8 is the digital signal samples interface of master controller microcontroller chip, 9 is the digital signal output interface of sub-controller microcontroller chip, 10 is the digital signal first sampling interface of sub-controller microcontroller chip, 11 is the digital signal second sampling interface of sub-controller microcontroller chip, 12 is the high capacity filter capacitor in the power circuit of sub-controller, 13 is to prevent the anti-discharge diode of capacitor to the bus back discharge in the power circuit of sub-controller, 14 instruction address bytes for master controller output, the value of byte is 5 in the example; 15 command content bytes for master controller output, the value of byte is 36 in the example; 16 answer bytes for sub-controller output, the value of byte is 1 in the example; 17 and 18 is the three-terminal voltage-stabilizing element.
Digital signal transmission method between the solar energy acquisition array controllers, solar energy acquisition array controllers comprises master controller and { one or } a plurality of sub-controllers, it is characterized in that a master controller and one or more sub-controller are parallel on the bifilar bus; Each controller can upwards drive bus; Three level values of definition are respectively a, b, c, a＜b that satisfies condition＜c on the bus; Master controller is urged to the c value with bus level and is kept when bus is used for the DC power supply of sub-controller; When being used for master controller master controller driving bus when sub-controller sends instruction, bus makes it to send level by the widened pulse signal of b to c; Stop to drive bus when bus is used for sub-controller master controller when master controller sends recall signal, drive bus by the sub-controller that sends recall signal and make it to send level by the widened pulse signal of a to b.Wherein in this bifilar bus one be the low level bus-, another strand be the high level bus+.
According to a specific embodiment of the present invention, a is taken as 0V (can change between the 0.4V at 0V), b is taken as 5V (can change between the 5.5V at 2.4V), the standard that meets the TTL logical circuit, so the microcontroller chip in the controller can directly be read or the drive level scope is by the widened pulse of a to b.C is taken as 13V (can change between the 14V at 11V), and being suitably for rated voltage in the sub-controller is the stepper motor power supply of 12V.
Master controller comprises master controller microcontroller chip 4, this master controller microcontroller chip comprises first signal output driving interface 6 to bus c level, secondary signal output driving interface 7 to bus b level, digital signal samples interface 8, this digital signal samples interface 8 is connected with an end of the 4th resistance R 4, the other end of the 4th resistance R 4 is connected with an end of the 5th resistance R 5, the other end of the 5th resistance R 5 is connected with the ground level of master controller, the high level bus of secondary signal output driving interface 7 by diode D1 and bus 1+be connected, first signal output driving interface 6 is connected with the base stage of triode T1 by the 3rd resistance R 3, the low level bus of the emitter of triode T1 and bus 1-be connected, the collector of triode T1 is connected with the 13V voltage of master controller with first resistance R 1 by second resistance R 2, the tie point of second resistance R 2 and first resistance R 1 is connected with the grid of field effect transistor T2, the drain electrode of field effect transistor T2 is connected with an end of the 5th resistance R 5, and the source electrode of field effect transistor T2 is connected with the 13V voltage of master controller.
When first signal output driving interface 6 of microcontroller 4 was high level, triode T1 conducting also drove field effect transistor T2 conducting, makes bus level be raised to the c value.
When first signal output driving interface 6 was low level, field effect transistor T2 closed.This moment is if secondary signal output driving interface 7 be a high level, this high level directly pass through diode D1 with bus driver to the b level.Diode D1 damages secondary signal output driving interface in order to prevent inverse current.
The variation of level between a and b is sent to digital signal samples interface 8 by the 4th resistance R 4 and detected on the bus.A capacitor C1 filtering interfering in parallel between sampling interface and ground wire.
Sub-controller comprises sub-controller microcontroller chip 5, this sub-controller microcontroller chip 5 comprises digital signal output interface 9, the digital signal first sampling interface 10, the digital signal second sampling interface 11, high level bus by diode D2 and bus 1 of digital signal output interface 9+be connected, the digital signal first sampling interface 10 is connected with an end of the 6th resistance R 12, the high level bus of the other end of the 6th resistance R 12 by electric capacity and bus 1+be connected, the other end of the 6th resistance R 12 also is connected with the 5V voltage of master controller by the 8th resistance R 13, digital signal second sampling interface 11 is connected with an end of the 7th resistance R 14, the high level bus of the other end of the 7th resistance R 14 and bus 1+be connected.
The high level bus of bus 1+be connected with the power circuit of sub-controller inside is anodal by diode 13, this power circuit positive pole and low level bus-between be provided with large value capacitor 12, low level bus-be connected with the ground level of sub-controller; Microcontroller chip 5 power supplies that this power circuit positive pole is given sub-controller by a three-terminal voltage-stabilizing element 18 output 5V voltages simultaneously.
When the bus no signal was transmitted, the c level value of bus was set up a bias voltage by the 8th resistance R 13 on capacitor C3.This bias voltage makes the lower end level of C3 reduce to 0 when bus level is reduced to the b value.The lower end level of C3 detects by the 6th resistance R 12 incoming digital signals first sampling interface 10, and the interface of therefore should sampling is to the variation sensitivity of bus level between b and c.
The variation of bus level between a and b detected toward the digital signal second sampling interface 11 by the 7th resistance R 14 pines.
When master controller stopped to drive bus, digital signal output interface 9 can be urged to the b value with bus level by diode D2.Diode D2 damages the digital signal output interface in order to prevent inverse current.
The first sampling interface of sub-controller receives the command signal of autonomous controller and gives demodulation; The sampling interface of master controller receives from the recall signal of sub-controller and gives demodulation.The second sampling interface of sub-controller is in order to detect the conflict situations that a plurality of sub-controllers send recall signal simultaneously.When clashing, being in has one can detect conflict by the second sampling interface in the sub-controller of conflict situation.
Each level of widened pulse changes a bit corresponding to instruction or answer byte, and be pulse width the interval time that adjacent twice level changes, and it depends on the value of corresponding bit.The pulse width of correspondence is made as 30 microseconds (can change) between 20 to 40 microseconds when this bit is 0, and the pulse width of correspondence is made as 90 microseconds (can change) between 60 to 120 microseconds when this bit is 1.Master controller was earlier reduced to bus level b value and was kept at least 200 microseconds before sending each byte, had time enough to detect and performed the reception preparation of byte to guarantee sub-controller.Master controller is reduced to bus level a value and is kept at least 200 microseconds earlier when waiting for the answer of sub-controller, and sub-controller can drive bus and send recall signal after detecting this bus state.
Fig. 4 has shown the waveform example of a reality.In this example, master controller at first sends an instruction address byte (14 intervals among the figure).Here master controller at first drops to bus level the b value and keeps 300 microseconds, as the preparatory stage of byte transmission.After preparatory stage finished, it was the preparation pulse of 30 microseconds for the c duration that master controller sends a level.Be byte content after the preparation pulse, represent a bit interval time between per here twice adjacent level changes, and short (30 microsecond) at interval represents 0, and long (90 microsecond) at interval represents 1.Therefore to count successively be 0 (the b level is at interval short) to whole byte area, 0 (the c level is at interval short), 0 (the b level is at interval short), 0 (the c level is at interval short), 0 (the b level is at interval short), 1 (the c level is at interval long), 0 (the b level is at interval short), 1 (the c level is at interval long).So the byte of transmission is a Binary Zero 0000101, or metric 5.The last bus state (c level) that restores electricity after through a b level spacing.This last interval is total in this example at interval short, but also can be used as parity check bit.
The 15 interval command content bytes of sending immediately for master controller of Fig. 4, the answer byte that send for corresponding sub-controller in 16 intervals.According to same cryptoprinciple, 15 intervals are corresponding to scale-of-two byte 00100100, or metric 36.16 intervals are corresponding to scale-of-two byte 00000001, or metric 1.
In the process of output recall signal, second of the control chip sampling interface keeps the monitoring to bus level when the output level of this sub-controller is a value at a sub-controller.Bus level rises to the b value if this moment is found in monitoring, and then illustrating has second sub-controller just with same address master controller being made answer in addition on the bus, and content and first sub-controller of answering are different, so both conflict to some extent.Under these circumstances, above-mentioned first sub-controller stops to export recall signal immediately, and changes self address to avoid further conflict.Ignorant to this above-mentioned second sub-controller, it will continue normally to export recall signal and continue to occupy original address.And the signal that master controller is received also fits like a glove with the output of second sub-controller, do not contain the conflict content, because the signal of the sub-controller of two conflicts output is consistent before conflict is found, and the conflict be found after above-mentioned first sub-controller stopped output, so the situation that two sub-controllers are exported different signals simultaneously can not occur.For master controller, the answer that does not just change the sub-controller of address that it is received.Master controller can be regarded the sub-controller that changes the address as occur a new address a new sub-controller.
All sub-controllers can be set an identical initial address when controller is produced.When starting working in system, master controller sends a standby address different with above-mentioned initial address to each sub-controller.Find ownly during with another sub-controller address conflict when certain sub-controller, this sub-controller is adjusted into standby address with self address.In operation process, master controller regularly sends query statement to standby address.In case master controller finds standby address and occupied by certain sub-controller, promptly select a vacant address else as new standby address and notify all sub-controllers.So, when system works a period of time of after, along with conflict constantly be found continuous adjustment with the address, all sub-controllers all can obtain a mutually different address automatically.
In a period of time that system starts working, the situation that a plurality of sub-controllers are shared an address may appear.This work to system only brings very limited influence, because the operating characteristic of solar energy acquisition array is, master controller is unanimous to the action command of sub-controller under most situations, i.e. all sub-controllers or tracking simultaneously, or have a rest simultaneously.The main situation that master controller need be implemented identification to sub-controller be when master controller when sub-controller is assembled data, and at this moment a plurality of sub-controller is shared the situation of an address and only can be caused the address separation of sub-controller and can not cause data corruption.
Claims (8)
1. the digital signal transmission method between the solar energy acquisition array controllers, solar energy acquisition array controllers comprises master controller and one or more sub-controller, it is characterized in that a master controller and one or more sub-controller are parallel on the bifilar bus; Each controller can upwards drive bus; Master controller is urged to the c value with bus level and is kept when bus is used for the DC power supply of sub-controller; When being used for master controller master controller driving bus when sub-controller sends instruction, bus makes it to send level by the widened pulse signal of b to c; Stop to drive bus when bus is used for sub-controller master controller when master controller sends recall signal, drive bus by the sub-controller that sends recall signal and make it to send level by the widened pulse signal of a to b, wherein a＜b＜c.
2. the digital signal transmission method between the solar energy acquisition array controllers as claimed in claim 1, it is characterized in that a at 0V between the 0.4V, b at 2.4V between the 5.5V, c at 11V between the 14V.
3. the digital signal transmission method between the solar energy acquisition array controllers as claimed in claim 1 is characterized in that the pulse width of widened pulse signal is 20 to 40 microseconds corresponding to bit 0, is 60 to 120 microseconds corresponding to bit 1.
4. the digital signal transmission method between the solar energy acquisition array controllers as claimed in claim 1, it is characterized in that sub-controllers all when controller is produced can set an identical initial address, when starting working in system, master controller sends a standby address different with above-mentioned initial address to each sub-controller, when certain sub-controller is found own and another sub-controller address conflict, this sub-controller is adjusted into standby address with self address, in operation process, master controller regularly sends query statement to standby address, in case master controller finds standby address and occupied by certain sub-controller, promptly select a vacant address else as new standby address and notify all sub-controllers; A sub-controller is in the process of output recall signal, when being a value, the output level of this sub-controller keeps monitoring to bus level, bus level rises to the b value if this moment is found in monitoring, then illustrating has second sub-controller just with same address master controller being made answer in addition on the bus, and content and first sub-controller of answering are different, therefore both conflict to some extent, under these circumstances, above-mentioned first sub-controller stops to export recall signal immediately, and changing self address to avoid further conflict, above-mentioned second sub-controller will continue normally to export recall signal and continue to occupy original address.
5. solar energy acquisition array controllers, solar energy acquisition array controllers comprises master controller and one or more sub-controller, it is characterized in that a master controller and one or more sub-controller are parallel on the bifilar bus, one is the low level bus in this bifilar bus, and another strand is the high level bus.
6. solar energy acquisition array controllers as claimed in claim 5, it is characterized in that master controller comprises master controller microcontroller chip, this master controller microcontroller chip comprises first signal output driving interface, secondary signal output driving interface, the digital signal samples interface, this digital signal samples interface is connected with an end of the 4th resistance, the other end of the 4th resistance is connected with an end of the 5th resistance, the other end of the 5th resistance is connected with the ground level of master controller, secondary signal output driving interface is connected with the high level bus of bus by diode, first signal output driving interface is connected with the base stage of triode by the 3rd resistance, the emitter of triode is connected with the low level bus one of bus, the collector of triode is connected with the 13V voltage of master controller with first resistance by second resistance, the tie point of second resistance and first resistance is connected with the grid of field effect transistor, the drain electrode of field effect transistor is connected with an end of the 5th resistance, and the source electrode of field effect transistor is connected with the 13V voltage of master controller.
7. described solar energy acquisition array controllers as claimed in claim 5, it is characterized in that sub-controller comprises sub-controller microcontroller chip, this sub-controller microcontroller chip comprises the digital signal output interface, the digital signal first sampling interface, the digital signal second sampling interface, the digital signal output interface is connected with the high level bus of bus by diode, the digital signal first sampling interface is connected with an end of the 6th resistance, the other end of the 6th resistance is connected with the high level bus of bus by electric capacity, the other end of the 6th resistance also is connected with the 5V voltage of master controller by the 8th resistance, the digital signal second sampling interface is connected with an end of the 7th resistance, and the other end of the 7th resistance is connected with the high level bus of bus.
8. described solar energy acquisition array controllers as claimed in claim 5, the high level bus that it is characterized in that bus is connected with the power circuit of sub-controller inside is anodal by a diode, be provided with large value capacitor between this power circuit positive pole and the low level bus, the low level bus is connected with the ground level of sub-controller; This power circuit positive pole is given the microcontroller chip power supply of sub-controller simultaneously by a three-terminal voltage-stabilizing element output 5V voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810203326 CN101738994A (en) | 2008-11-25 | 2008-11-25 | Method for transmitting digital signals among solar energy acquisition array controllers |
| PCT/CN2009/000961 WO2010060256A1 (en) | 2008-11-25 | 2009-08-21 | Method for digital signal transmission between solar acquisition array controllers |
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| CN 200810203326 CN101738994A (en) | 2008-11-25 | 2008-11-25 | Method for transmitting digital signals among solar energy acquisition array controllers |
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| TWI421517B (en) * | 2010-08-02 | 2014-01-01 | Macronix Int Co Ltd | System and method for testing integrated circuits |
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| US8407950B2 (en) | 2011-01-21 | 2013-04-02 | First Solar, Inc. | Photovoltaic module support system |
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| US6043629A (en) * | 1998-11-03 | 2000-03-28 | Hughes Electronics Corporation | Modular control electronics for batteries |
| US6614253B2 (en) * | 2001-08-03 | 2003-09-02 | Northrop Grumman Corporation | On-circuit board continuity tester |
| DE10215790B4 (en) * | 2002-04-10 | 2004-02-19 | S. Siedle & Söhne, Telefon- und Telegrafenwerke Stiftung & Co. | House communication system |
| JP2005025309A (en) * | 2003-06-30 | 2005-01-27 | Canon Inc | Information processor |
| CN1649233A (en) * | 2005-02-05 | 2005-08-03 | 嘉善县长顺电子厂 | Radio control colonizing solar light system |
| CN1808284A (en) * | 2006-01-26 | 2006-07-26 | 上海微电子装备有限公司 | Serial data transmission system with multiple acquisition channels and control method thereof |
| CN1825784A (en) * | 2006-04-07 | 2006-08-30 | 北京中科信电子装备有限公司 | Communication method and apparatus |
| CN200987228Y (en) * | 2006-06-09 | 2007-12-05 | 浙江大学 | Intelligent lighting system |
| CN1877473A (en) * | 2006-06-30 | 2006-12-13 | 中国南车集团株洲电力机车研究所 | Power battery management system for electric vehicle |
| CN201075709Y (en) * | 2007-08-09 | 2008-06-18 | 张文宝 | Solar energy controller |
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| TWI421517B (en) * | 2010-08-02 | 2014-01-01 | Macronix Int Co Ltd | System and method for testing integrated circuits |
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Open date: 20100616 |