CN101707485A - LDPC decoding method combining bit flipping (BF) and majority logic (MLG) - Google Patents

Abstract

The invention relates to a LDPC decoding method combining bit flipping (BF) and majority logic (MLG), belonging to the technical field of digital information transmission. The LDPC decoding method comprising the following steps of: (1) computing syndromes s of a check matrix of M rows and N columns, wherein s=(s1, s2, to sM), if the syndromes are all 0, and then carrying out step 4; (2) finding the most unreliable bit through a bit reliability measurement; (3) flipping and finding out the most unreliable bit; (4) when a largest iteration is achieved, carrying out step (5), and when all the syndromes are all 0, stopping decoding and outputting corresponding codons to complete decoding treatment, or else, repeating the steps of (1) to (3); and (5) sending the codons containing non 0 value in the syndromes to an MLG decoder for decoding, and finally outputting the codons decoded by the majority logic decoder to complete the decoding treatment. The invention utilizes the decoding method combining BF decoding and MLG without floating point arithmetic in the whole decoding process, reduces computation complexity and time delaying, and has favorable decoding performance.

Description

The LDPC interpretation method of hybrid bitstream upset and majority logic

Technical field

The invention belongs to digital information transmission technical field, the LDPC interpretation method of especially a kind of hybrid bitstream upset and majority logic.

Background technology

Low-density checksum (LDPC, Low Density Parity Check) sign indicating number is a large amount of chnnel codings of using in the present digital information transmission field.The LDPC sign indicating number is represented with generator matrix G and check matrix H usually as a kind of common linear block codes, is characterized in: the number of nonzero element is far smaller than the number of neutral element in the parity check matrix H.In message transmitting procedure, receiving terminal need be deciphered the LDPC sign indicating number, the LDPC interpretation method mainly contains tree-like decoding, probabilistic decoding and long-pending decoding, minimum and decoding, bit reversal decoding and majority-logic decoding etc., and all there is certain limitation in above-mentioned various interpretation methods.The bit reversal interpretation method is a kind of interpretation method relatively more commonly used.

Bit reversal (BF, Bit flipping) decoding belongs to a kind of Hard decision decoding method, this interpretation method at first will be imported the data of decoder and carry out hard decision, ' 0 ' and all check equations of ' 1 ' sequence substitution that obtain, calculate the result of each syndrome, then according to check results, find out and make the verification formula maximum variable node of number of being false, at last with the pairing bit reversal of this variable node, so far finish iteration one time, whole decode procedure constantly repeats each step of front, all sets up up to all verification formulas, perhaps arrive the maximum iteration time of prior setting, finished decode procedure.Below bit reversal interpretation method (BF interpretation method) is described:

Here note set N (c) expression participates in all bit nodes of verification c, and M (v) represents all verifications that bit node v participates in.N (c) v represent to gather other bit node of removing bit node v among the N (c), in like manner M (v) c represent that M (removes other verifications of verification c v).(d for rule _v, d _c) the LDPC sign indicating number, have | and M (v) |=d _vWith | N (c) |=d _c

If (N, K) a LDPC code word c=(c ₁, c ₂, c ₃... .., c _N), its code check matrix has M capable.After the BPSK modulation,, obtain sequences y=(y at receiving terminal by awgn channel ₁, y ₂, y ₃... .., y _N), the y at bit node v place wherein _v=2c _v-1+w _v, w _vBe that the obedience average is 0, variance is N ₀/ 2 Gaussian random variable, corresponding hard decision sequence is z=(z ₁, z ₂, z ₃... .., z _N).

Its decode procedure is as follows:

(1) channel output is done firmly declared z ⁰=(z ₁ ⁰, z ₂ ⁰, z ₃ ⁰... .., z _N ⁰) (if y _n＞0, z then _n=1, otherwise z _n=0), initialization iterations: k=1.

(2) calculate syndrome

M=1,2 ..., M, h here _{M, n}N capable element of expression check matrix H m.

(3) add up each variable node v _nInvalid number in the pairing verification formula

(4) from f=(f ₁, f ₂..., f _N) in find out maximum f _Max, with the bit z of its pairing variable node _MaxUpset obtains new code word z ^k

(5) all satisfy up to all verification formulas repeating step (2)～(4), or arrive till the maximum iteration time of setting in advance.

BF deciphers each iterative decoding and selects f _nMaximum variable node upset, each value that only changes a bit, when the code length of LDPC sign indicating number was longer, the iterations that needs was very big, the computational process more complicated. and can certainly set certain thresholding, work as f _nDuring greater than this thresholding, overturn, bit of the more than upset of such iteration can reduce iterations.If but overturn a plurality of bits simultaneously, might cause occurring untestable fault, promptly be translated into other code word, cause the decline of decoding performance.Usually BF deciphers under the good situations of channel condition such as being suitable for optical fiber communication and uses.

In order to strengthen the error correcting capability of BF decoding, can adopt weighting bit reversal (WBF, WeightedBit-Flipping) in the interpretation method, its with the minimum value of the channel output amplitude of all variable node correspondences of verification formula as weighted factor, to upset criterion weighted, its concrete decoding step is as follows:

(1) calculates syndrome

M=1,2 ..., M, h here _{M, n}N capable element of expression check matrix H m.

(2) calculate the reliability of each bit $E_v=\underset{m\∈M\left(v\right)}{\mathrm{\Σ}}(2s_m-1){\left|y\right|}_{\min -m}$ Here ${\left|y\right|}_{\min -m}=\underset{v\∈N\left(c\right)}{\min }\left|y_v\right|;$

(3) flip bits z _v, v=argmax _1≤v≤NE _v

(4) all satisfy up to all verifications repeating step (1)-(3), perhaps reaches maximum iteration time.

WBF decoding also can the several bits of once inside out, but determining of threshold value is relevant with the SNR of channel, so calculate more complicated, and can cause the increase of untestable fault equally.Other of WBF decoding are improved one's methods as LP-WBF (Liu-Pados-Weighted Bit-Flipping) interpretation method and Weighted-Sum WBF (WS-WBF) interpretation method, improved decoding performance to a certain extent, but computational complexity is not improved, all exist complexity big, contain a large amount of problems such as floating-point operation.

At present, be used along with more and more having quadrature parity check LDPC sign indicating number, as based on euclidean geometry, the 4 class LDPC sign indicating numbers that the Points And lines of perspective geometry constructs: the 1st class and the 2nd class EG-LDPC sign indicating number (European how much low density parity check code Euclidean-Geometry LDPC), the 1st class and the 2nd class PG-LDPC (perspective geometry low density parity check code Projective-Geometry LDPC), this 4 class LDPC sign indicating number is cyclic code or quasi-cyclic code, its check matrix possesses consistent orthogonality, all can adopt majority logic MLG (Majority-LoGic) interpretation method to realize.

Vertical the above, have problems such as decoding performance difference and calculation of complex at existing BF interpretation method, press for and a kind of bit reversal and majority logic combined having the method that the conforming LDPC of quadrature carries out hybrid decoding.

Summary of the invention

The objective of the invention is to overcome the deficiencies in the prior art, a kind of LDPC interpretation method that adopts the integer computing, calculates simple and decoding performance good mixing bit reversal and majority logic is provided.

The present invention solves its technical problem and takes following technical scheme to realize:

The LDPC interpretation method of a kind of hybrid bitstream upset and majority logic may further comprise the steps:

(1) syndrome of calculation check matrix and decoding, if syndrome is 0 entirely, execution in step (4);

(2) find the least reliable bit by bit reliability tolerance;

(3) the least reliable bit that overturns and find;

(4) if reach the maximum iteration time of setting, execution in step (5) if all syndromes are 0 entirely, stops decoding, exports corresponding code word, and finish decoding and handle, otherwise repeating step (1)～(3);

(5) code word that syndrome is contained non-0 value is delivered to the majority-logic decoding device and is deciphered, and exports the code word behind majority-logic decoding at last, finishes decoding and handles.

And the method for the syndrome s of described calculation check matrix is:

$s_m={\mathrm{\Σ}}_{n=1}^N{z}_n{h}_{m,n},m=\mathrm{1,2},...,M$

Here, this check matrix has the capable n row of M, h _{M, n}N capable element of expression check matrix m.

And described tolerance by bit reliability finds the least reliable bit to make realization with the following method:

(1) to having (the d of quadrature parity check _v, d _c) the LDPC sign indicating number sets up one by d _v+ 1 sequence of sets Q that set is formed ₀Q _d, use Q _iStore satisfaction parameter U (v)=bit of i, wherein 0≤i≤d;

(2) find the satisfaction parameter U that deposits (the v) maximum nonempty set Q of value _i, 1＜i≤d wherein;

(3) (v) the bit of value minimum is as the least reliable bit to select weighting parameters T.And, described satisfaction parameter U (v) value is:

$U\left(v\right)=\underset{c}{\mathrm{\Σ}}[(R\left(c\right)+1)/2],\{c\∈M\left(v\right)\}$

Wherein

And, described weighting parameters T (v) value is:

$T\left(v\right)=\underset{c}{\mathrm{\Σ}}R\left(c\right)\underset{v^{\′}}{g\max }\left(U\left(v^{\′}\right)\right),\{v^{\′}\∈N\left(c\right)\backslash v,c\∈M\left(v\right)\}.$

Advantage of the present invention and good effect are:

This interpretation method is at the low density parity check code with quadrature parity check characteristic, seek the least reliable bit by new metric parameter, the LDPC interpretation method that has adopted bit reversal (BF) decoding and majority logic (MLG) decoding to combine, that is: at first through BF decoding, and then using MLG decoding, the iterations that has improved BF decoding is many, decoding performance descends and the problem of calculation of complex.The present invention combines decoding performance, complexity and time delay and considers that whole decode procedure does not relate to floating-point operation, all adopts the integer computing, and it calculates simple, has reduced time delay, has good decoding performance.

Description of drawings

Fig. 1 is a process chart of the present invention;

Fig. 2 is the bigraph (bipartite graph) of (1023,781) of the present invention EG-LDPC sign indicating number;

Fig. 3 the present invention is directed to the performance chart that (1023,781) EG-LDPC adopts different interpretation methods;

Fig. 4 is the performance chart of the present invention when selecting different iterations.

Embodiment

Below in conjunction with accompanying drawing specific embodiments of the invention are described in detail.

The present invention is a hybrid decoding method of the FG-LDPC sign indicating number with quadrature parity check being used bit reversal and majority logic, now with European how much low density parity check codes of the 1st class---(1023,781) the EG-LDPC sign indicating number is an example, the information bit length of 781 expression inputs wherein, the code word size of exporting after the 1023 expression error correction codings.Bit v has participated in 32 verifications, and each verification comprises 32 bits.(v) expression comprises the number of the illegal verification of bit v to definition U.The bigraph (bipartite graph) representation of this (1023,781) EG-LDPC sign indicating number as shown in Figure 2.Definition D (a, the b) distance of node a and node b in the expression bigraph (bipartite graph), in Fig. 2, D (v, v _1.1)=2, D (v, c ₁)=1.

Shown in the bigraph (bipartite graph) of EG-LDPC sign indicating number, it satisfies following definition:

$U\left(v\right)=\underset{c}{\mathrm{\Σ}}[(R\left(c\right)+1)/2],\{c\∈M\left(v\right)\};$

Wherein:

$U_{\max }(c/v)=\underset{v^{\′}}{\max }\left(U\left(v^{\′}\right)\right),\{v^{\′}\∈N\left(c\right)\backslash v\};$

$T\left(v\right)=\underset{c}{\mathrm{\Σ}}R\left(c\right){\mathrm{gU}}_{\max }(c\backslash v),\{c\∈M\left(v\right)\};$

Wherein, N (c) expression participates in all bit nodes of verification c, M (v) represent all verifications that bit node v participates in, N (c) v represent to gather other bit node of removing bit node v among the N (c).

For the 1st class (1023,781) EG-LDPC sign indicating number, by the definition of LDPC sign indicating number as can be known, to any one verification c ₁If, R (c ₁)=1, then N (c ₁) the odd number error bit arranged.When the signal to noise ratio of channel during than good 2-4dB of Shannon limit, N (c ₁) in have the possibility of 3 error bits smaller.So, generally speaking, as R (c ₁N (c generally can be thought in)=1 o'clock ₁) in have only a mistake.One bigger

Mean that unique mistake more similarly is at N (c ₁In the)/v, that is to say, v be an error bit probability along with

Increase and reduce.Similarly, as R (c ₁)=-1 o'clock, this probability along with

Increase and increase.For this probability of quantitative analysis, (this value is described v) with parameter T.Bit v ₁With bit v ₂Satisfy U (v ₁)=U (v ₂) time, and T (v ₁)＜T (v ₂), mean v ₁Compare v ₂More unreliable.

(v) described the degree that the verification that bit participated in is satisfied, each verification is considered as being equal to reliably parameter U.Parameter T (v) then participates in each verification to bit and has carried out weighting, describe the reliability of each verification.(v), T (v), can better describe the reliability of verification and bit, thereby find the least reliable bit associating operation parameter U.Particularly for the FG-LDPC sign indicating number that row is heavy, column weight is all bigger, parameter T (v) more can provide information effectively.In addition, in iterative decoding process, the information that the verification formula passes to variable should not comprise the information that this variable provides, and the WBF iterative process of standard fails to reject the information that variable self provides, and said method has been avoided this problem.

In addition, there is the problem of Infinite Cyclic in decoding at BF, can adopt BF decoding earlier, correct error bit under covering, through after the iteration of some, the error bit in the code word significantly reduces, utilize MLG decoding again, the possibility of bit of correcting a mistake fully is just bigger, and hiding darker error bit can once translate, and avoids Infinite Cyclic problem in the bit reversal process.MLG decoding can be corrected dmin/2 mistake at most.Here can select best iterations according to signal to noise ratio by emulation.The key of this mixed structure interpretation method is to find a kind of measure accurately to seek least reliable bit.

Suppose that check matrix H has the capable N of M row, the signal processing flow graph of the hybrid bitstream upset that the present invention proposes and the LDPC interpretation method of majority logic as shown in Figure 1, step is as follows:

1. calculate the syndrome s=(s of the check matrix of the capable N row of M ₁, s ₂..., s _M), if syndrome is 0 entirely, execution in step (4), the method for the syndrome s of calculation check matrix H is:

$s_m={\mathrm{\Σ}}_{n=1}^N{z}_n{h}_{m,n},m=\mathrm{1,2},...,M$

Here, this check matrix H has the capable N row of M, h _{M, n}N capable element of expression check matrix H m.

2. find the least reliable bit by bit reliability tolerance, its method is:

(1) to having (the d of quadrature parity check _v, d _c) the LDPC sign indicating number sets up one by d _v+ 1 sequence of sets Q that set is formed ₀Q _d, use Q _iStore satisfaction parameter U (v)=bit of i, wherein 0≤i≤d;

(2) find the satisfaction parameter U that deposits (the v) maximum nonempty set Q of value _i, 1＜i≤d wherein;

(3) (v) the bit of value minimum is as the least reliable bit to select weighting parameters T.

Above-mentioned satisfaction parameter U (v) value is:

$U\left(v\right)=\underset{c}{\mathrm{\Σ}}[(R\left(c\right)+1)/2],\{c\∈M\left(v\right)\}$

Wherein

Above-mentioned weighting parameters T (v) be:

$T\left(v\right)=\underset{c}{\mathrm{\Σ}}R\left(c\right)\underset{v^{\′}}{g\max }\left(U\left(v^{\′}\right)\right),\{v^{\′}\∈N\left(c\right)\backslash v,c\∈M\left(v\right)\}$

Wherein, N (c) expression participates in all bit nodes of verification c, M (v) represent all verifications that bit node v participates in, N (c) v represent to gather other bit node of removing bit node v among the N (c).

3. the least reliable bit that finds of upset.

4. if reach the maximum iteration time of setting, execution in step 5 if all syndromes are 0 entirely, stops decoding, exports corresponding code word, and finish decoding and handle, otherwise repeating step 1～3.

5. when the greatest iteration number reached, the syndrome of gained code word correspondence was not 0, and the code word that this moment syndrome is contained non-0 value is delivered to the majority-logic decoding device and deciphered, and exports the code word behind majority-logic decoding at last, finished the decoding processing.

In above-mentioned hybrid decoding method, when the iterative processing each time of decoding, needn't calculate each bit information.Behind 1 the bit v that overturn, the U of not all bit (v) and T (value v) all can change.In fact has only bit set P with the same verification of bit v fellowship ₁In the U of bit (v) value and other participate in bit set P ₁The bit set P of the verification that is participated in ₂In the T of bit (v) value can change, and the value of other bit then need not be calculated.After supposing that bit v is reversed, set P ₂In the T of bit (v) value changes.At this moment only need set of computations P ₂IQ _H(Q _HExpression Q _iIn T (the v) value of bit among the U that deposits (v) value maximum nonempty set).This has significantly reduced operand, and in seeking least the reliable bit process, this method does not relate to floating-point operation, is the integer computing, and insensitive to signal to noise ratio.

At awgn channel, BPSK modulates down, is example with the 1st class (1023,781) EG-LDPC sign indicating number, and relatively the performance of the method for the present invention's proposition and other interpretation method compares, and as shown in Figure 3, these interpretation methods comprise: (1) standard WBF method; (2) (v), T (v) measures the bit reversal method (containing first kind of method that overcomes Infinite Cyclic) of bit reliability to adopt U; (3) the mixing BF/MLG interpretation method of the present invention's proposition.10 ^-4The place, the mixing BF/MLG interpretation method that the present invention proposes is than the gain of the nearly 0.3dB of standard WBF interpretation method.(v), T (v) measures the gain of the bit reversal structure (containing the 1st kind of method that overcomes Infinite Cyclic) of bit reliability than the nearly 0.2dB of standard WBF interpretation method to adopt U.

Fig. 4 provided different iterationses in the mixing BF/MLG decoding architecture that the present invention proposes to Effect on Performance. can see in low signal-to-noise ratio (under the 2-3dB) 10 error rates of iteration (BER) minimum, when 3.5dB, 100 error rates of iteration are minimum, under high s/n ratio 4dB, the error rate is very approaching. and this is because under the low signal-to-noise ratio, the bit reversal interpretation method can not find real error bit, may cause the many more mistakes of iteration many more. than under the high s/n ratio, the new method of measuring bit reliability can find real error bit, thereby the reduction error rate. as can see from Figure 3, because FG-LDPC iterative decoding convergence is good, mixes the BF/MLG decoding architecture and only need select less iteration number just can reach good decoding performance.

Satisfy the LDPC sign indicating number of quadrature parity check at its check matrix, the FG-LDPC sign indicating number that particularly row is heavy, column weight is all bigger the present invention proposes the LDPC interpretation method of a kind of new mixing BF/MLG.Compare with standard WBF interpretation method, do not relate to the floating point multiplication addition computing, and insensitive to signal to noise ratio.Simultaneously the FG-LDPC sign indicating number has good range performance, and the iterative decoding convergence is good, and the interpretation method that the present invention proposes only need carry out seldom that the iteration of number (as 10 times) just can reach better performance.Between decoding performance, complexity and time delay, obtained good compromise.

It is emphasized that; embodiment of the present invention is illustrative; rather than it is determinate; therefore the present invention is not limited to the embodiment described in the embodiment; every other execution modes that drawn by those skilled in the art's technical scheme according to the present invention belong to the scope of protection of the invention equally.

Claims (5)

1. the LDPC interpretation method of hybrid bitstream upset and majority logic is characterized in that: may further comprise the steps:

(1). the syndrome of calculation check matrix and decoding, if syndrome is 0 entirely, execution in step (4);

(2). find the least reliable bit by bit reliability tolerance;

(3). the least reliable bit that upset is found;

(4) if. reach the maximum iteration time of setting, execution in step (5) if all syndromes are 0 entirely, stops decoding, exports corresponding code word, finishes decoding and handles, otherwise repeating step (1)～(3);

(5). the code word that syndrome is contained non-0 value is delivered to the majority-logic decoding device and is deciphered, and exports the code word behind majority-logic decoding at last, finishes decoding and handles.

2. the LDPC interpretation method of hybrid bitstream upset according to claim 1 and majority logic is characterized in that: the method for calculating the syndrome s of check matrix in the described step (1) is:

$s_m={\mathrm{\Σ}}_{n=1}^N{z}_n{h}_{m,n},m=\mathrm{1,2},...,M$

Here, this check matrix has the capable N row of M, h _{M, n}N capable element of expression check matrix m.

3. the LDPC interpretation method of hybrid bitstream upset according to claim 1 and majority logic is characterized in that: described tolerance by bit reliability finds the least reliable bit to make realization with the following method:

(1) to having (the d of quadrature parity check _v, d _c) the LDPC sign indicating number sets up one by d _v+ 1 sequence of sets Q that set is formed ₀Q _d, use Q _iStore satisfaction parameter U (v)=bit of i, wherein 0≤i≤d;

(2) find the satisfaction parameter U that deposits (the v) maximum nonempty set Q of value _i, 1＜i≤d wherein;

(3) (v) the bit of value minimum is as the least reliable bit to select weighting parameters T.

4. the LDPC interpretation method of hybrid bitstream upset according to claim 3 and majority logic is characterized in that: described satisfaction parameter U (v) value is:

$U\left(v\right)=\underset{c}{\mathrm{\Σ}}[(R\left(c\right)+1)/2],\{c\∈M\left(v\right)\}$

Wherein

5. the LDPC interpretation method of hybrid bitstream upset according to claim 3 and majority logic is characterized in that: described weighting parameters T (v) value is:

$T\left(v\right)=\underset{c}{\mathrm{\Σ}}R\left(c\right)g\underset{v^{\′}}{\max }\left(U\left(v^{\′}\right)\right),\{v^{\′}\∈N\left(c\right)\backslash v,c\∈M\left(v\right)\}.$

Images