CN101673336B - Decoding device and decoding method - Google Patents
Decoding device and decoding method Download PDFInfo
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- CN101673336B CN101673336B CN2008101488055A CN200810148805A CN101673336B CN 101673336 B CN101673336 B CN 101673336B CN 2008101488055 A CN2008101488055 A CN 2008101488055A CN 200810148805 A CN200810148805 A CN 200810148805A CN 101673336 B CN101673336 B CN 101673336B
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Abstract
The invention discloses a decoding device and a decoding method, which can effectively avoid the phenomenon of decoding errors easily because the conventional RFID system decodes signals by adopting an association method so as to improve the accuracy of the RFID system in signal decoding. The decoding device is applied to data signals comprising a plurality of bits. The data signals generate a plurality of sampling data after being sampled. The bits have the same bit period. The decoding device comprises a statistical module and a decision module, wherein the statistical module sets a first time section and a second time section of the bit period for a specific bit, generates a first count according to the sampling data corresponding to a first logic level in the first time section, and generates a second count according to the sampling data corresponding to a second logic level in the second time section; and the decision module decides a numerical logic value of the specific bit according to the first count and the second count.
Description
Technical field
The present invention relates to signal decoding, relate in particular to a kind of radio frequency identification (RadioFrequency Identification, RFID) code translator of system and method for being applied to.
Background technology
In recent years, get quite rapidly with the relevant research and development of radio frequency identification (RFID), so-called " RFID technology " simply says a kind of contactless automatic identification technology of promptly being made up of label (tag) and reader (reader).Please with reference to Fig. 1, Fig. 1 is the part synoptic diagram that illustrates traditional high-frequency RF ID receiving trap.As shown in Figure 1, high-frequency RF ID receiving trap 2 sees through the signal that antenna 3 receives from RFID reader or RFID label.This signal will be transferred into code translator 6 to carry out work decoding after the sampling of the processing of passing through mimic channel 4 and sample circuit 5.
Generally speaking, the code translator 6 of high-frequency RF ID receiving trap 2 adopts association (correlation) method to decipher for header (header) section and data (data) section of this signal mostly.Yet when code translator 6 adopted the association method to decipher for the data segments of signal, the situation that often has many decoding errors took place.Probe into the reason that it is easy to generate decoding error; Mainly be because when code translator 6 used the association method to decipher, code translator 6 was whether to judge that greater than critical value this digital logic value is 0 or 1 according to the association peak value (correlation peak value) that a certain position in the data segments is produced actually.Because code translator 6 judges that the result of this digital logic value has inseparable relation with the setting of the critical value of association peak value; Therefore; Must cross when low or too high when this critical value setting, all can cause code translator 6 false judgment and cause the situation of decoding error to take place.
Summary of the invention
Technical matters to be solved by this invention provides and a kind ofly is applied to radio frequency identification (it can promote the accuracy that rfid system carries out signal decoding for RadioFrequency Identification, RFID) code translator of system and method.
In order to solve above technical matters, the invention provides following technical scheme:
First specific embodiment of the present invention is a kind of code translator.In fact, this code translator can be applicable in the rfid system, and comprises a plurality of data signals in order to decoding, and each of this data signals all has identical bit period.This data signals produces a plurality of sampled datas after taking a sample.
In this embodiment, this code translator comprises statistical module and decision module.After statistical module is set the very first time section and the second time section of accomplishing the bit period of a certain bits in this data signals; Statistical module will produce first counting according to these sampled datas in this very first time section corresponding to the accurate position of first logic (logiclevel).In addition, statistical module also can produce second counting according to these sampled datas in this second time section corresponding to the accurate position of second logic.After statistical module had produced first counting and second counting, decision module will be according to the digital logic value of first counting with second this certain bits of counting decision.
In practical application, accurate position of first logic and the accurate position of second logic can be accurate position of high logic or the accurate position of low logic simultaneously.Very first time section is the preceding semiperiod of the bit period of this certain bits; The second time section is the later half cycle of the bit period of this certain bits.
Second specific embodiment of the present invention is a kind of coding/decoding method.In fact, this interpretation method can be applicable to comprise a plurality of data signals in the rfid system and in order to decoding, and each of this data signals all has identical bit period.Before this interpretation method was deciphered this data signals, this data signals produced a plurality of sampled datas via sampling.
At first, the very first time section and the second time section of the bit period of a certain bits in this interpretation method setting data signal.Then, this coding/decoding method will produce first counting according to these sampled datas in this very first time section corresponding to the accurate position of first logic, and according to these sampled datas in this second time section corresponding to the accurate position of second logic, produce second counting.At last, this coding/decoding method will be according to the digital logic value of first counting with the second counting decision certain bits.
In practical application, accurate position of first logic and the accurate position of second logic can be accurate position of high logic or the accurate position of low logic simultaneously.Very first time section is the preceding semiperiod of the bit period of this certain bits; The second time section is the later half cycle of the bit period of this certain bits.
Code translator that the present invention adopts and method be according to the sampling spot number that is positioned at the accurate position of high logic in each preceding semiperiod in the signal whether more than the interim sampling spot number that is positioned at the accurate position of high logic of second half to determine the digital logic value of each.Therefore, with respect to prior art, code translator of the present invention and method cause the phenomenon of decoding error easily in the time of can effectively avoiding traditional rfid system to adopt the association method to carry out signal decoding, can promote the accuracy that rfid system carries out signal decoding.
Description of drawings
Fig. 1 illustrates prior art medium-high frequency RFID receiving trap synoptic diagram.
Fig. 2 is the functional block diagram that illustrates the code translator of first specific embodiment according to the present invention.
Fig. 3 illustrates the example of data signals.
Fig. 4 (A), Fig. 4 (B), Fig. 4 (C), Fig. 4 (D) illustrate the example with the header section of association method detecting data signal.
Fig. 5 is the calcspar that illustrates the detailed functions of statistical module shown in Figure 2.
Fig. 6 (A), Fig. 6 (B), Fig. 7 (A), Fig. 7 (B), Fig. 8 (A), Fig. 8 (B), Fig. 9 (A), Fig. 9 (B), Figure 10 (A), Figure 10 (B) illustrate various signal decoding examples respectively.
Figure 11 is the process flow diagram that illustrates the interpretation method of second specific embodiment according to the present invention.
[primary clustering symbol description]
S10 ~ S16: process step
1: code translator 2: high-frequency RF ID receiving trap
3: antenna 4: mimic channel
5: sample circuit 6: code translator
8: multiplexer 12: statistical module
14: decision module 16: detecting module
120: buffer storage unit 122: the data decoding processing unit
124: 126: the first counters in periodic Control unit
A: best point S: the reference position of data segments
P1: the first peak value P2: second peak value
P3: the 3rd peak value P4: the 4th peak value
Embodiment
First specific embodiment of the present invention is a kind of code translator.In this embodiment, this code translator can be applicable in the rfid system, and comprises a plurality of data signals in order to decoding.This data signals can produce a plurality of sampled datas after sampling.As shown in Figure 3, this data signals comprises header section and data segments, and data segments is next to after the header section and comprises this a plurality of positions.Each position all has the identical bits cycle in these a plurality of positions.
In this embodiment, this data signals can be formed by Manchester's cde method (Manchester encodingmethod), differential type Manchester's cde method (differential Manchester encoding method) or other similar compiling method coding.So-called " Manchester's cde method " is a kind of coded system commonly used in many LANs.Its key property is that the digital logic value of the no matter position of data signals is 0 or 1, near the central authorities in each cycle, all has the conversion of the accurate position of high logic and the accurate interdigit of low logic on the ideal.If be converted to the accurate position of low logic by the accurate position of high logic, the digital logic value of representing this is 1; If by the accurate position of the low logic paramount logic of accurate position conversion, the digital logic value of representing this is 0.
Be as for " differential type Manchester's cde method " and " Manchester's cde method " maximum differential; Near the central authorities in each cycle, have the conversion of the accurate interdigit of logic equally; If the conversion of the accurate interdigit of logic is also arranged at the beginning the time at bit period; The digital logic value of then representing this is 0, otherwise is 1.
In this embodiment, this rfid system can be a high-frequency RF ID receiving trap, but not as limit.Please with reference to Fig. 2, Fig. 2 is the functional block diagram that illustrates the code translator of first specific embodiment according to the present invention.As shown in Figure 2, code translator 1 comprises statistical module 12, decision module 14 and detecting module 16.Detecting module 16 comes the header section of detecting data signal according to the sampling data of gained and based on the association method; When detecting the header section of data signals, the reference position of the data segments that detecting module 16 can the decision data signal also produces detection signal to start statistical module 12.That is to say, for can specified data the reference position of data segments of signal, code translator 1 must be detected for the header section of data signals through detecting module 16 earlier before all decoding of the data segments of formally carrying out data signals.Therefore, have only when detecting module 16 to detect under the situation of data signals header section, code translator 1 just can carry out follow-up decoding action to all positions of data section.
Please with reference to Fig. 4 (A) to Fig. 4 (D), Fig. 4 (A) illustrates through the example of association method detecting header section with the reference position of judgment data section to Fig. 4 (D).Shown in figure four (A), four positions that the header section of tentation data signal is comprised are 1,0,1,0 in regular turn.When detecting module 16 carries out the detecting of header section, can the position that get into detection area be stored in the association buffer storage area (correlation buffer), as in the association buffer storage area, then can fill 0 if run into the position that does not have bit value.Therefore, shown in Fig. 4 (A), when the header section of data signals had only first position 1 to get into detection area, everybody of the header section that the association buffer storage area is stored was 0,0,0,1 in regular turn.
Then, detecting module 16 will be compared four stored positions of association buffer storage area in regular turn and shield four positions (1,0,1,0) that (mask) comprised with comparison, to judge the power of association between the two.In fact, the comparison shielding can be changed according to the header section of different signals.Shown in Fig. 4 (A), both results of comparison have only second identical (being 0), so resulting association peak value (correlation peakvalue) is the first peak value P1.
Shown in Fig. 4 (B), when preceding two positions 1 and 0 of the header section of data signals all got into detection area, the stored position of association buffer storage area was 0,0,1,0 in regular turn.When detecting module 16 carry out the association buffer storage area with the comparison shielding ratio to after, find that both back three positions (0,1,0) are all identical, so resulting association peak value is the second peak value P2.
Shown in Fig. 4 (C), when first three position 1,0 and 1 of data signals header section all got into detection area, the stored position of association buffer storage area was 0,1,0,1 in regular turn.When detecting module 16 carry out the association buffer storage area with the comparison shielding ratio to after, find both all the position all inequality, so resulting association peak value is the 3rd peak value P3.
Shown in Fig. 4 (D), when all positions 1,0,1 and 0 of the header section of data signals all got into detection area, the stored position of association buffer storage area was 1,0,1,0 in regular turn.When detecting module 16 carry out the association buffer storage area with the comparison shielding ratio to after, find both all the position all identical, so resulting association peak value is the 4th peak value P4.
When detecting module 16 detects the 4th peak value P4,, be best point so detecting module 16 will be ordered the A point among Fig. 4 (D), and judge the reference position S of data segments because the 4th peak value P4 is the maximal value of association peak value.At this moment, because detecting module 16 has obtained the reference position S of data segments, therefore, detecting module 16 will produce detection signal to start statistical module 12.
In this embodiment, the major function that statistical module 12 is possessed has two: the bit period of the position of desiring in the data segments to decipher is divided into former and later two sections, and in these two sections, produces first counting and second counting respectively.Statistical module 12 can be set the very first time section and the second time section of the bit period of a certain bits in this data signals earlier.As shown in Figure 3, very first time section is the preceding semiperiod of bit period, and the second time section is the later half cycle of bit period, and the length summation of the very first time section and the second time section equals the length of whole bit period.
Set the very first time section and the second time section of this certain bits when statistical module 12 after; Statistical module 12 will be added up the partial data that these sampling data are arranged in very first time section; Number corresponding to the accurate position of first logic is counted to produce first; And add up the partial data that these sampled datas are arranged in the second time section, count to produce second corresponding to the number of the accurate position of second logic.In this embodiment, the accurate position of first logic equals the accurate position of this second logic, and for example both are accurate position of high logic or the accurate position of low logic.When this statistical module 12 judged that this data signals has finished, statistical module 12 will produce setting signal to detecting module 16, to reset detecting module 16.
Please with reference to Fig. 5, Fig. 5 is the detailed functions calcspar that illustrates statistical module 12.As shown in Figure 5, statistical module 12 comprises buffer storage unit 120, data decoding processing unit 122, periodic Control unit 124, first counter 126, second counter 128 and selected cell 130.Wherein data decoding processing unit 122 is coupled to detecting module 16; Periodic Control unit 124 is coupled to data decoding processing unit 122, selected cell 130 and decision module 14; Selected cell 130 is coupled to buffer storage unit 120, first counter 126 and second counter 128; Buffer storage unit 120 is coupled to multiplexer 8; First counter 126 and second counter 128 all are coupled to decision module 14.
In this embodiment, the function of buffer storage unit 120 is these sampled datas that the storage data signal is produced via sample procedure processing back.These sampled datas can see through the selection of multiplexer 8 and be sent to buffer storage unit 120 or detecting module 16.
At the beginning, when detecting module 16 still was in the state of header section of detecting data signal, detecting module 16 can control multiplexers 8, make it that sampled data is sent to detecting module, to carry out the detecting of header section; And after detecting the header section; Detecting module 16 can switch multiplexer 8; Make it that sampled data is sent to buffer storage unit 120; And this simultaneously, and detecting module 16 will produce detection signal to data decoding processing unit 122, with the translator of designation data decoding processing unit 122 beginning data.Data decoding processing unit 122 will produce the one-period counting according to each cycle of bit period and a sampling frequency of data signals after receiving detection signal.
In more detail, this cycle count is the quotient of this bit period divided by the cycle of this sampling frequency.Whether data decoding processing unit 122 also can finish by the judgment data signal, and when data signals finished, data decoding processing unit 122 can produce setting signal to reset detecting module 16.
The very first time section and the second time section of the bit period that cycle count that the function of periodic Control unit 124 is to be produced according to data decoding processing unit 122 and sampling frequency are set certain bits.More particularly; Periodic Control unit 124 is counted according to sampling frequency, before count value no show cycle count half the, is regarded as the very first time section of bit period; When count value surpasses the half the of cycle count and do not reach the count cycle, be regarded as the second time section of bit period this moment.That is to say that periodic Control unit 124 can be divided into preceding semiperiod (very first time section) and later half cycle (the second time section) with the bit period of each in the data signals, and produces controlling signal, is beneficial to subsequent decoding work.This controlling signal is in order to the indication very first time section or the second time section, and follow-up selected cell 130 promptly can be according to the indication of controlling signal, and these sampled datas in the decision buffer storage unit 120 should pass to first counter 126 or second counter 128.
In practical application, controlling signal will be controlled selected cell 130, in the very first time of bit period section, these sampled datas is passed to first counter 126; And in the second time section of bit period, these sampled datas are passed to second counter 128.Wherein selected cell 130 can come real the work with multiplexer.
After first counter 126 received these sampled datas, first counter 126 will be added up the number of times that in very first time section, belongs to the accurate position of first logic in these sampled datas and count to produce first.In like manner, after second counter 128 received these sampled datas, second counter 128 will be added up the number of times that in the second time section, belongs to the accurate position of second logic in these sampled datas and count to produce second.In this embodiment, the accurate position of first logic all is made as the accurate position of high logic with the accurate position of second logic, but not as limit.Then, first counter 126 and second counter 128 are sent to decision module 14 with first counting and second counting respectively.Decision module 14 also is coupled to periodic Control unit 124; When periodic Control unit 124 judges that the bit period of certain bits finishes; Can produce one and start signal to decision module 14, be 1 or 0 to indicate decision module 14 according to the word logic value of first counting and second this certain bits of counting decision.
Next, will describe with the instance that several pins is deciphered different signals.In following all examples, all with the foundation of the accurate position of high logic as counting, but not as limit.Fig. 6 (A), Fig. 6 (B), Fig. 7 (A), Fig. 7 (B), Fig. 8 (A), Fig. 8 (B), Fig. 9 (A), Fig. 9 (B), Figure 10 (A), Figure 10 (B) illustrate the oscillogram of the sampled data under the various situation and the relation of bit period; Whole housing is promptly represented a bit period among the figure; Middle dotted line by the figure point-like separates; Left side one side of something and right one side of something respectively are the very first time section and the second time section, and remaining dotted line is represented the sample position of sampling frequency.The frequency of sampling frequency is required to be the twice of the frequency of sampled data at least, and each following figure promptly is that example describes with the twice.
Please with reference to Fig. 6 (A) and Fig. 6 (B), Fig. 6 (A) and Fig. 6 (B) illustrate the sampled data under the perfect condition.Shown in Fig. 6 (A), in the very first time of this bit period section, sampled data runs into eight sampling spots altogether, wherein has four sampling spots to be in the accurate position of high logic, and four sampling spots then are in the accurate position of low logic in addition, and therefore, first counting is 4; In the second time section of this bit period, data signals also runs into eight sampling spots, and these eight sampling spots all are in the accurate position of low logic, so second to count be 0.Because first counting is greater than second counting, decision module 14 can be 1 with this digital logic value decision.In like manner, shown in Fig. 6 (B), because first counting is that 0 and second counting is 4, that is first counting is less than second counting, so the digital logic value of position is decided to be 0.
Please with reference to Fig. 7 (A) and Fig. 7 (B), situation that on behalf of sampled data, this example in bit period, move to right avertence.Shown in Fig. 7 (A), in the very first time of this bit period section, have three sampling spots and be in the accurate position of high logic, so first counting is 3; In the second time section of this bit period, have only a sampling spot to be in the accurate position of high logic, so second counting is 1.Because first counting is greater than second counting, the digital logic value of position is decided to be 1.In like manner, shown in Fig. 7 (B), because first counting is that 0 and second counting is 3, that is first counting is less than second counting, so the digital logic value of position is decided to be 0.
Please with reference to Fig. 8 (A) and Fig. 8 (B), situation that on behalf of the sampling data, this example squint left.Shown in Fig. 8 (A), in the very first time of this bit period section, have three sampling spots and be in the accurate position of high logic, so first counting is 3; In the second time section of this bit period, do not have any sampling spot and be in the accurate position of high logic, so second counting is 0.Because first counting is greater than second counting, the digital logic value of position is decided to be 1.In like manner, shown in Fig. 8 (B), because first counting is that 1 and second counting is 3, that is first counting is less than second counting, so the digital logic value of position is decided to be 0.
Even last two example explanations are when sampled data has offset generating, under the little situation of skew, code translator 1 of the present invention still can be made correct decoding.
Please with reference to Fig. 9 (A) and Fig. 9 (B), this example is represented the stronger situation of sampling data intensity.Shown in Fig. 9 (A), in the very first time of this bit period section, all eight sampling spots all are in the accurate position of high logic, so first counting is 8; In the second time section of this bit period, do not have any sampling spot and be in the accurate position of high logic, so second counting is 0.Because first counting is greater than second counting, the digital logic value of position is decided to be 1.In like manner, shown in Fig. 9 (B), because first counting is that 0 and second counting is 6, that is first counting is less than second counting, so the digital logic value of position is decided to be 0.
Please with reference to Figure 10 (A) and Figure 10 (B), this example is represented the more weak situation of sampling data intensity.Shown in Figure 10 (A), in the very first time of this bit period section, have three sampling spots and be in the accurate position of high logic, so first counting is 3; In the second time section of this bit period, do not have any sampling spot and be in the accurate position of high logic, so second counting is 0.Because first counting is greater than second counting, the digital logic value of position is decided to be 1.In like manner, shown in Figure 10 (B), because first counting is that 0 and second counting is 3, that is first counting is less than second counting, so the digital logic value of position is decided to be 0.
Even last two example explanations are when sampled data has the increase and decrease on the intensity, code translator 1 of the present invention still can be made correct decoding.Therefore, can know that by the explanation of Fig. 7 to Figure 10 code translator 1 can be dealt with the situation of various different sampled datas, prove that code translator 1 of the present invention has more elasticity in practical application.
In addition, if first counting equals second counting, this digital logic value will be decided to be 0.Whether correctly will wait until the inspection that follow-up circuit is done all correctness as for everybody decode results in the sampled data, for example utilize the check code of whole string data to judge whether everybody digital logic value is deciphered correctly before.And the numerical value of that less counting is excessive in first counting is counted with second, will be regarded as bump (collision).
The present invention's second specific embodiment is a kind of coding/decoding method.In fact, this interpretation method can be applicable in the rfid system, and can comprise a plurality of data signals in order to decoding.This data signals is to be formed by Manchester's cde method, differential type Manchester's cde method or other similar compiling method coding, and each all has identical bit period in these a plurality of positions.This data signals comprises header section and data segments, and data segments is next to after the header section.It should be noted that this data signals produces a plurality of sampled datas by sample procedure before this interpretation method is deciphered this data signals.
Please with reference to Figure 11, Figure 11 is the process flow diagram that illustrates this coding/decoding method.Shown in figure 11, at first, this interpretation method execution in step S10 detects the header section to judge the reference position of data segments with the association method.Then; This interpretation method execution in step S11; Set the very first time section and the second time section of the bit period of a certain bits in these sampled datas, then in step S12 according to these sampled datas in this very first time section corresponding to the accurate position of first logic, produce first counting; Then, this interpretation method execution in step S13 corresponding to the accurate position of second logic, produces second counting according to these sampled datas in this second time section.
In this embodiment, the accurate position of first logic equals the accurate position of second logic, for example is all the accurate position of accurate position of high logic or low logic.In addition, very first time section is the preceding semiperiod of bit period, and the second time section is the later half cycle of this bit period.The length summation of the very first time section and the second time section equals the length of bit period.
Because first counting produces with second counting, therefore, this interpretation method will execution in step S14, judges whether first counting is counted greater than second.If first counting is greater than second counting, this interpretation method will execution in step S15, and the digital logic value of decision certain bits is 1; If first counting is less than or equal to second counting.At this moment, this interpretation method will execution in step S16, and the digital logic value of decision certain bits is 0.Having this Rule of judgment is because the data signals in the present embodiment is to form via Manchester's cde method, differential type Manchester's cde method or other similar compiling method coding; If data signals is otherwise to encode to form; Only Rule of judgment need be and then adjusted, correct decoding can be made.
In this embodiment, this coding/decoding method can see through the association method and remove the header section of detecting data signal, and uses the reference position of judgment data signal data segments.
In sum, code translator of the present invention and method be according to the sampling data number that is positioned at the accurate position of high logic in each preceding semiperiod in the signal whether more than the interim sampled data number that is positioned at the accurate position of high logic of second half to determine the digital logic value of each.Therefore; Compared to prior art; In the time of can effectively avoiding traditional rfid system to adopt the association method to carry out signal decoding according to code translator of the present invention and method, cause the phenomenon of decoding error easily, to promote the accuracy that rfid system carries out signal decoding.
By the detailed description of above preferred embodiment, be to hope to know more to describe characteristic of the present invention and spirit, and be not to come category of the present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can be encompassed in the arrangement of various changes and tool equality in the scope of claim protection of the present invention.Therefore, claim of the present invention should be done the broadest explanation according to above-mentioned explanation, contains the arrangement of all possible change and tool equality to cause it.
Claims (15)
1. interpretation method; Be applied to adopt the manchester encoded data signal; This data signals comprises a plurality of positions, and each all has an identical bit period in these a plurality of positions, and this data signals produces a plurality of sampled datas after taking a sample; It is characterized in that said interpretation method comprises the following step:
(a), set a very first time section and the one second time section of its bit period for a certain bits;
(b) according to these a plurality of sampled datas in this very first time section corresponding to the accurate position of one first logic, produce one first counting;
(c) according to these a plurality of sampled datas in this second time section corresponding to the accurate position of one second logic, produce one second counting; And
(d) judge whether whether this first counting be 1 greater than this second counting with a digital logic value that determines this certain bits.
2. interpretation method as claimed in claim 1; It is characterized in that wherein accurate position of this first logic and the accurate position of this second logic are all the accurate position of high logic, this very first time section is preceding half of this bit period; This second time section is the later half of this bit period; And in step (d), greater than this second counting, this digital logic value is decided to be 1 as if this first counting.
3. interpretation method as claimed in claim 1 is characterized in that, wherein this data signals is to be encoded by the change type of Manchester's cde method to form.
4. interpretation method as claimed in claim 1 is characterized in that, wherein the accurate position of this first logic equals the accurate position of this second logic.
5. interpretation method as claimed in claim 1 is characterized in that, it is applied to a radio frequency identification (RFID) system.
6. interpretation method as claimed in claim 5 is characterized in that, wherein this data signals is to be formed by Manchester's cde method coding.
7. code translator; Be applied to adopt a data signals of Manchester's cde; This data signals comprises a plurality of positions, and each all has an identical bit period in these a plurality of positions, and this data signals produces a plurality of sampled datas after taking a sample; It is characterized in that said code translator comprises:
One statistics module; A very first time section and one second time section in order to this bit period of setting a certain bits; And according to these a plurality of sampled datas in this very first time section corresponding to the accurate position of one first logic; Produce one first counting, and according to this a plurality of sampled datas in this second time section corresponding to the accurate position of one second logic, produce one second and count; And
One decision module is coupled to this statistical module, and this decision module judges whether whether this first counting be 1 greater than this second counting with a digital logic value that determines this certain bits.
8. code translator as claimed in claim 7; It is characterized in that; Wherein accurate position of this first logic and the accurate position of this second logic are all the accurate position of high logic, this very first time section be this bit period preceding partly, this second time section is the later half of this bit period; If this first counting is greater than this second counting, this this digital logic value of decision module decision is 1.
9. code translator as claimed in claim 7 is characterized in that, wherein this data signals is to be encoded by the change type of Manchester's cde method to form.
10. code translator as claimed in claim 7 is characterized in that, wherein the accurate position of this first logic equals the accurate position of this second logic.
11. code translator as claimed in claim 7 is characterized in that, it is applied to a radio frequency identification system.
12. code translator as claimed in claim 7 is characterized in that, wherein this data signals comprises a header section and a data segments, and this data segments is next to after this header section and comprises this a plurality of positions, and this code translator more comprises:
One detecting module is coupled to this statistical module, and when this detecting module detected this header section according to an association method, this detecting module was judged an initial position of this data segments and produced a detection signal to start this statistical module.
13. code translator as claimed in claim 7 is characterized in that, wherein this statistical module comprises:
One buffer storage unit is in order to store these a plurality of sampled datas;
One data decoding processing unit produces one-period counting in order to the cycle according to this bit period and a sampling frequency;
One-period control module, be coupled to this data decoding processing unit, should very first time section and this second time section in order to set according to this cycle count and this sampling frequency;
One first counter is coupled to this periodic Control unit, this buffer storage unit and this decision module, and the number of times that belongs to the accurate position of this first logic in these these a plurality of sampled datas of first counter system meter is to produce this first counting; And
One second counter is coupled to this periodic Control unit, this buffer storage unit and this decision module, and the number of times that belongs to the accurate position of this second logic in these these a plurality of sampled datas of second counter system meter is to produce this second counting;
Wherein this data signals is to produce these a plurality of sampled datas via this sampling frequency sampling.
14. code translator as claimed in claim 13 is characterized in that, wherein this periodic Control unit produces in order to indicate a controlling signal of this very first time section and this second time section, and this statistical module more includes:
One selected cell is coupled to this buffer storage unit, this periodic Control unit, this first counter and this second counter, and this selected cell optionally transmits these a plurality of sampled datas to this first counter or this second counter according to this controlling signal.
15. code translator as claimed in claim 13; It is characterized in that; Wherein this periodic Control unit more is coupled to this decision module, and this periodic Control unit produces a startup signal according to this cycle count and this sampling frequency, to indicate this digital logic value of this this certain bits of decision module decision.
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| CN2008101488055A CN101673336B (en) | 2008-09-12 | 2008-09-12 | Decoding device and decoding method |
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| CN2008101488055A CN101673336B (en) | 2008-09-12 | 2008-09-12 | Decoding device and decoding method |
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| CN103595421A (en) * | 2012-08-13 | 2014-02-19 | 上海华虹集成电路有限责任公司 | A decoder for TYPE A basic data rate signals transmitted by a decoding card |
| CN102810148A (en) * | 2012-08-13 | 2012-12-05 | 沃谱瑞科技(北京)有限责任公司 | Decoding circuit of non-contact communication integrated circuit |
| CN103595422B (en) * | 2012-08-13 | 2017-12-22 | 上海华虹集成电路有限责任公司 | Decode the decoder for the type A high data rate signals that card is sent |
| TWI536862B (en) | 2012-11-06 | 2016-06-01 | 聯詠科技股份有限公司 | Data transmission system and method |
| CN103812600B9 (en) * | 2012-11-08 | 2017-12-15 | 联咏科技股份有限公司 | Data transmission system and method |
| TWI543623B (en) * | 2013-04-08 | 2016-07-21 | 晨星半導體股份有限公司 | Video signal decoding device and method of decoding video signal |
| CN104424450B (en) * | 2013-08-19 | 2017-05-17 | 福建升腾资讯有限公司 | Magnetic-card decoding method based on ADC pin sampling |
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| US6963295B1 (en) * | 2004-07-02 | 2005-11-08 | Texas Instruments Incorporated | Method of recovering and decoding of Manchester coded data |
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| CN1106081C (en) * | 1996-07-17 | 2003-04-16 | 株式会社三丰 | Code translation circuit |
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| US6963295B1 (en) * | 2004-07-02 | 2005-11-08 | Texas Instruments Incorporated | Method of recovering and decoding of Manchester coded data |
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