CN101667157A - Flash memory data transmission method, flash memory storage system and controller - Google Patents
Flash memory data transmission method, flash memory storage system and controller Download PDFInfo
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- CN101667157A CN101667157A CN200810213777A CN200810213777A CN101667157A CN 101667157 A CN101667157 A CN 101667157A CN 200810213777 A CN200810213777 A CN 200810213777A CN 200810213777 A CN200810213777 A CN 200810213777A CN 101667157 A CN101667157 A CN 101667157A
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Abstract
The invention discloses a flash memory data transmission method, a flash memory storage system and a controller. The data transmission method is applied to data transmission from a cache memory to a plurality of flash memory groups through a single data bus in the flash memory storage system. The data transmission method comprises the step of: taking a logic block as a unit, and orderly arrangingand grouping data which are stored in the cache memory and belongs to continuous logical addresses; and the data transmission method also comprises the step of: transmitting sector data to each flashmemory group respectively through the single data bus according to the grouping in a staggering way, wherein the data belonging to the same logical block are to be transmitted and written into entityblocks of the same flash memory group. On the basis, the data are prevented from being dispersed into a plurality of entity blocks so as to reduce the abrasion of the entity blocks.
Description
Technical field
The flash memory system and the controller thereof that the present invention relates to a kind of data transmission method that is used for flash memory and use the method particularly relate to a kind of being used for to write data to the data transmission method of the flash memory wafer with a plurality of flash memory crystal grain and flash memory system and the controller thereof that uses the method by single data bus.
Background technology
Digital camera, mobile phone camera and MP3 are very rapid in development over the years, make the consumer also increase rapidly the demand of Storage Media.Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., suitable portable use, the most suitable being used on the portable battery-powered product of this class.Solid state hard disc is exactly a kind of with the storage device of nand flash memory as Storage Media.
In general, the flash memory crystal grain (die) in the flash memory wafer (chip) of flash memory system can be divided into a plurality of solid elements (unit), and these unit generally can be made up of a physical blocks or a plurality of physical blocks.These unit can be defined as data field (data area) and spare area (spare area).Classify as and to store in the solid element of data field by writing the valid data that instruction writes, and the unit in the spare area is the solid element in the replacement data district when writing instruction in execution.Specifically, when flash memory system receive host computer system writing the instruction and desire is write fashionable to the solid element of data field, flash memory system can from the spare area, extract solid element and will be in the data field effective legacy data in the solid element that upgrades of desire write to the solid element that from the spare area, extracts with the new data of desiring to write and the solid element that will write new data is associated as the data field, and the solid element of data field is erased and is associated as the spare area originally.In order to allow the solid element of host computer system access successfully with the mode storage data of rotating, flash memory system can configuration logic unit carry out access for host computer system, and wherein logical block is to dispose according to the size of solid element with one or more physical blocks.That is to say, flash memory system can be set up logic-entity mapping, and the mapping relations in this table between the solid element of record and renewal logical block and data field reflect rotating of solid element, so host computer system only need be carried out access and flash memory system can come the solid element that is shone upon is read or write data according to logic-entity mapping at providing logical block.
Yet, when the progress on flash technology makes that the design capacity meeting of each physical blocks is increasing, also cause the above-mentioned relative increase of time meeting of moving effective legacy data, just, the time of flash memory system programming (program) flash memory crystal grain can increase thereupon.For to quicken the flash memory system writing speed, develop at present a plurality of flash memory die package be a flash memory wafer and write data in an interleaved program (interleave program) mode at a plurality of flash memory intercrystalline alternatelies when writing mass data.Specifically, because in order to transmit data to the required time required time of the data bus (data bus) of flash memory crystal grain far below programming flash memory crystal grain, therefore in general can a configuration buffer zone (buffer) in each flash memory crystal grain and when the controller of flash memory system writes data to flash memory crystal grain data can be transmitted earlier so far and programme again behind the buffer zone (, write) to the physical blocks of flash memory crystal grain, wherein flash memory crystal grain is in busy (busy) phase that data also are called this flash memory crystal grain during the physical blocks that writes.Therefore, in the example of the flash memory wafer of a plurality of flash memory crystal grain, the controller of flash memory system can shorten the required time of mass data that writes by the mode that data is divided into a plurality of subdatas, the subdata alternately is transferred to the buffer zone of the flash memory crystal grain that is not in the busy phase and respectively a plurality of subdatas are write to a plurality of physical blocks again with interlace mode.
Yet, in above-mentioned operation, can will belong to the continuous logic address (promptly, same logical blocks) data disperse to write in a plurality of physical blocks that belong to different flash memory crystal grain, therefore follow-up when controller only upgrades the data that belong to one of them logical blocks, controller still must upgrade and the data of moving in a plurality of physical blocks simultaneously, therefore can increase the required time of data that writes.In addition, because when new data more, need erase (erase), therefore can increase the wearing and tearing of physical blocks and life-span of reducing flash memory system to a plurality of physical blocks.
Summary of the invention
In view of this, the invention provides a kind of data transmission method, it can promote efficient that data write and the wearing and tearing that can reduce physical blocks.
In addition, the invention provides a kind of controller, it uses above-mentioned data transmission method to transmit data, and it can promote efficient that data write and the wearing and tearing that can reduce physical blocks.
Moreover, the invention provides a kind of flash memory system, it uses above-mentioned data transmission method to transmit data, and it can promote efficient that data write and the wearing and tearing that can reduce physical blocks.
The present invention proposes a kind of data transmission method, is applicable to flash memory system, and wherein this flash memory system has a plurality of physical blocks, and these physical blocks are grouped into a plurality of flash memory groups and these flash memory groups are connected with same data bus.This data transmission method comprises: a plurality of logic sectors and a plurality of logical blocks are provided, and wherein logic sector is the mapping logic block, and logical blocks is the mapping physical blocks; The sector data that will belong to continuous logic sector is grouped into a plurality of block datas in order, and wherein each block data is corresponding one of them logical blocks; And the sector data that will belong to same block data transmits and writes in the same physical blocks.
In one embodiment of this invention, above-mentioned data transmission method comprises that also be that unit is sent to sector data in the flash memory group respectively with an interlace mode with the block data by data bus, wherein can synchronously write to these flash memory groups to these sector datas of small part.
In one embodiment of this invention, each above-mentioned flash memory group is made up of at least one memory crystal grain, and the part of the physical blocks of each memory crystal grain can be defined as a spare area, and the sector data that wherein belongs to same block data can be written in the physical blocks of being extracted from the spare area of same flash memory crystal grain.
In one embodiment of this invention, above-mentioned data transmission method also is included as each flash memory crystal grain and writes down one logic-entity mapping individually.
In one embodiment of this invention, above-mentioned data transmission method also is included as each flash memory crystal grain and carries out one individually and on average smear the damage program.
In one embodiment of this invention, above-mentioned data transmission method also is included in and carries out a copies back (copyback) instruction in each flash memory crystal grain with copy data between the physical blocks of each flash memory crystal grain.
The present invention also provides a kind of flash memory system and controller thereof, this flash memory system comprises a plurality of physical blocks, at least one data bus, memory cache, connector and controller, and wherein physical blocks is grouped into a plurality of flash memory groups and data bus is to be connected to these flash memory groups.This controller is to be electrically connected to above-mentioned memory cache, data bus and connector, and this controller the flash interface module, memory buffer, host interface module and the memory management module that comprise microprocessor unit and be coupled to microprocessor unit.Particularly, this memory management module has a plurality of machine instructions that can be carried out by above-mentioned microprocessor unit flash memory is finished above-mentioned data transmission method.
In one embodiment of this invention, above-mentioned flash memory system is carry-on dish, flash card or solid state hard disc.
The present invention is that unit arranges and divides into groups because of adopting data in the memory cache with the logical blocks according to logical address, and be sent to interlace mode in a plurality of flash memory crystal grain of flash memory wafer, therefore can carry out interleaved program (interleave program) when pattern writes data at flash memory system, the data centralization that will belong to the continuous logic address in the physical blocks of same flash memory crystal grain, the writing speed when being lifted at follow-up more new data thus and reduce the number of times of erasing of physical blocks.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is the summary calcspar that illustrates flash memory system according to one embodiment of the invention.
Fig. 2 is the calcspar that illustrates the flash memory wafer according to the embodiment of the invention.
Fig. 3 A is the schematic diagram that illustrates the physical blocks of flash memory wafer according to the embodiment of the invention.
Fig. 3 B is the running synoptic diagram that illustrates the physical blocks of flash memory wafer according to the embodiment of the invention.
Fig. 4 A illustrates the example schematic that transfers data to the flash memory wafer from memory cache according to the embodiment of the invention.
Fig. 4 B is the sequential chart that illustrates the interleaved program of Fig. 4 A institute demonstration example.
Fig. 5 is the process flow diagram that illustrates data transmission step according to the embodiment of the invention.
The reference numeral explanation
100: flash memory system
110: controller
110a: microprocessor unit
110b: memory management module
110c: flash interface module
110d: memory buffer
110e: host interface module
120: connector
130: memory cache
140: the flash memory wafer
142,144,146,148: flash memory crystal grain
142-1,144-1,146-1,148-1, PD, SD: physical blocks
149: data bus
200: host computer system
202: system region
204: the data field
206,206a, 206b, 206c, 206d: spare area
210, LB, LB1, LB2, LB3, LB4: logical blocks
300: bus
LS (1)～LS (4n): logic sector
SDATA (1)～(4n): sector data
Transmission: T (1)～T (n)
S501, S503, S505, S507, S509, S511: data transmission step
Embodiment
Fig. 1 is the summary calcspar that illustrates flash memory system according to one embodiment of the invention.Please refer to Fig. 1, flash memory system 100 comprises controller (also claiming controller system) 110, connector 120, memory cache 130 and flash memory wafer (flash memory chip) 140.
Usually flash memory system 100 can use with host computer system 200, so that host computer system 200 can write to data flash memory system 100 or reading of data from flash memory system 100.In the present embodiment, flash memory system 100 be solid state hard disc (Solid State Drive, SSD).But it must be appreciated that flash memory system 100 can also be storage card or coil with oneself in another embodiment of the present invention.
Microprocessor unit 110a in order to cooperative cooperatings such as memory management module 110b, flash interface module 110c, memory buffer 110d and host interface module 110e to carry out the various runnings of flash memory system 100.
Memory management module 110b is coupled to microprocessor unit 110a.Memory management module 110b has a plurality of machine instructions that can be carried out by microprocessor unit 110a with management flash memory wafer 140, for example machine instruction of average abrasion, block management function, service logic-entity mapping (mapping table) function etc.Particularly, in embodiments of the present invention, memory management module 110b comprises the machine instruction that can finish according to the data transmission step of present embodiment.
In the present embodiment, memory management module 110b is embodied in the controller 110 with a firmware pattern, for example write the instruction of program associated mechanical and (for example be stored in program storage with program language, ROM (read-only memory) (Read Only Memory, ROM)) is come the real memory management module 110b that does.When flash memory system 100 runnings, a plurality of machine instructions of memory management module 110b can be loaded on indirectly among the memory buffer 110d and by microprocessor unit 110a and carry out or directly carried out to finish above-mentioned average abrasion function, bad block management function, service logic-physical blocks mapping table function etc. by microprocessor unit 110a.Particularly, controller 110 comes this to finish data transmission step according to the embodiment of the invention by a plurality of mechanical orders of execute store administration module 110b.
In another embodiment of the present invention, the mechanical order of memory management module 110b can also the firmware pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash memory) of flash memory wafer 140.Same, when flash memory system 100 runnings, a plurality of machine instructions of memory management module 110b can be loaded among the memory buffer 110d and by microprocessor unit 110a to be carried out.In addition, memory management module 110b can also a hardware pattern be embodied in the controller 110 in another embodiment of the present invention.
Flash interface module 110c is coupled to microprocessor unit 110a and in order to access flash memory wafer 140.Just, the data of desiring to write to flash memory wafer 140 can be converted to 140 receptible forms of flash memory wafer via flash interface module 110c.
Memory buffer 110d is coupled to microprocessor unit 110a and in order to stocking system data (for example logic-entity mapping) temporarily or data that host computer system 200 read or write.In the present embodiment, memory buffer 110d be static RAM (static random accessmemory, SRAM).Yet, it must be appreciated, the invention is not restricted to this, dynamic RAM (Dynamic Random Access memory, DRAM), reluctance type storer (Magnetoresistive Random Access Memory, MRAM), phase transition storage (PhaseChange Random Access Memory, PRAM) or other storeies that are fit to also can be applicable to the present invention.
Host interface module 110e is the instruction that is coupled to microprocessor unit 110a and is transmitted in order to reception and identification host computer system 200.Just, the instruction and the data that are transmitted of host computer system 200 can be sent to microprocessor unit 110a by host interface module 110e.In the present embodiment, host interface module 110e is a PCI Express interface.Yet, it must be appreciated to the invention is not restricted to this that host interface module 110e can also be USB interface, IEEE 1394 interfaces, SD interface, MS interface, MMC interface, SATA interface, PATA interface, CF interface, ide interface or other data transmission interfaces that is fit to.Particularly, host interface module 110e can be corresponding with connector 120.Just, host interface module 110e must arrange in pairs or groups mutually with connector 120.
In addition, though be not illustrated in present embodiment, controller 110 can comprise also that error correction module and power management module etc. are used to control the general utility functions module of flash memory wafer.
Connector 120 is in order to connect host computer system 200 by bus 300.In the present embodiment, connector 120 is a PCI Express connector.Yet, it must be appreciated to the invention is not restricted to this that connector 120 can also be USB connector, IEEE 1394 connectors, SD connector, MS connector, MMC connector, SATA connector, CF connector, IDE connector, PATA connector or other connectors that is fit to.
Fig. 2 is the calcspar that illustrates the flash memory wafer according to the embodiment of the invention.Flash memory wafer 140 comprises the first flash memory crystal grain (flash memory die), 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146, the 4th flash memory crystal grain 148 and in order to the data bus 149 of transmission data between controller 110 and flash memory wafer 140 in the present embodiment.In the present embodiment, the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146, the 4th flash memory crystal grain 148 are that (chipenable, CE) pin position (not illustrating) comes activation by a wafer activation respectively.Yet, the invention is not restricted to this, can also a plurality of flash memory crystal grain of CE pin position activation in another embodiment of the present invention, this moment, a plurality of flash memory crystal grain with same CE pin position activation were referred to as flash memory group.In the present embodiment, because the 4th flash memory crystal grain 148 of the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 is to come activation with a wafer activation pin position respectively, therefore a flash memory crystal grain is a flash memory group in the present embodiment.
For managerial convenience, the controller 110 of flash memory system 100 can be divided into a plurality of solid elements (physical unit) with the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148.In general, solid element can comprise a physical blocks or a plurality of physical blocks, and is the management that unit carries out physical blocks with the solid element.A solid element is a physical blocks in the present embodiment, is to be that unit manages with the physical blocks in the present embodiment therefore.Yet, the invention is not restricted to this, a flash memory crystal grain can be made up of a plurality of block faces (plane) in another embodiment of the present invention, and solid element is made up of a plurality of physical blocks that belongs to the different blocks face, and can carry out access this moment with multi-tiling face access mode.
Physical blocks is the minimum unit of flash memory of erasing on the circuit.That is each physical blocks contains the storage unit of being erased in the lump of minimal amount.Each physical blocks can be divided into several pages (page) usually, and the page is the minimum unit of programming (program) flash memory.But what specify is in some different flash memory design, and minimum programming unit also can be a sector (sector).That is to say the minimum unit that in page a plurality of sectors is arranged and be programming with a sector.In other words, the page is the minimum unit that writes data or reading of data in the present embodiment.Each page generally includes user data field D and redundant area R.The user data field is in order to storage user's data, and redundant area is in order to data (for example, the error-correcting code (error correcting code, ECC)) of stocking system.
Be sector (sector) size corresponding to disc driver, generally speaking, user data field D is generally 512 bytes, and redundant area R is generally 16 bytes.Just, a page is a sector.Yet, can also form a page in a plurality of sectors.In the present embodiment, flash memory block page is to comprise 4 sectors.
Generally speaking, physical blocks can be made up of the page of arbitrary number, for example 64 pages, 128 pages, 256 pages etc.In the present embodiment, physical blocks is to comprise 256 pages.In addition, physical blocks in the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 also can be grouped into several zones (zone) usually, and coming diode-capacitor storage with the zone is to operate independently of one another with the parallel degree of increase operation execution and the complexity of streamlining management in a way.
Fig. 3 A is the schematic diagram that illustrates the physical blocks of flash memory wafer 140 according to the embodiment of the invention.
It must be appreciated, when this describes the running of flash memory with " extraction ", " moving ", " exchange ", " replacement ", " rotating ", " cut apart ", " division " and etc. speech to operate physical blocks in the flash memory wafer 140 be in logic notion.That is to say that the physical location of the physical blocks of flash memory is not changed, but in logic the physical blocks of flash memory is operated.What deserves to be mentioned is that the running of following physical blocks is that the mechanical order of controller 110 execute store administration module 110b is finished.
Please refer to Fig. 3 A, in embodiments of the present invention, in order to programme (promptly efficiently, write) data, controller 110 can logically be defined as the physical blocks in the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 system region 202, data field 204 and spare area 206.As previously mentioned, the physical blocks of the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 can provide host computer system 200 to come storage data in the mode of rotating, therefore controller 110 can provide a plurality of logical addresses to host computer system 200 carrying out data access, and write down the physical blocks that logical address is shone upon by service logic-entity mapping.
Specifically, flash memory wafer 140 is to be that unit manages with the physical blocks in the present embodiment, so controller 110 is to be that unit comes management logic-entity mapping with logical blocks 210.In addition, host computer system 200 is to be that unit comes access data with the sector, therefore can to provide with the logic sector be that the logical address of unit is carried out access to host computer system 200 to controller 110, and controller 110 can will be that the logical address of unit is converted to the logical blocks access of carrying out data by the logical address of unit thus in the page address according to the next physical blocks at flash memory crystal grain of institute's foundations and the logic-entity mapping of maintenance with the logic sector.
Physical blocks in the system region 202 is in order to the register system data, and this system data comprises the logic-entity mapping (logical-physical mapping table) etc. of page number, record logical address and the physical address mapping relations of the number of regions that is divided about physical blocks in each flash memory crystal grain, physical blocks number that each is regional, each physical blocks.
Physical blocks in the data field 204 is in order to store user's data, in general is exactly the physical blocks that the logical blocks 210 of 200 accesses of host computer system is shone upon.
Therefore physical blocks in the spare area 206 is in order to the physical blocks in the replacement data district 204, and the physical blocks in spare area 206 be sky or spendable block, i.e. no record data or be labeled as invalid data useless.
Particularly, data field 204 can store the data that 200 pairs of flash memory systems 100 of host computer system are write in the mode of rotating with the physical blocks of spare area 206.Specifically, because each physical address only can be programmed once in flash memory, therefore if will write data once more to the address of writing data the time, the action of (erase) of erasing of execution earlier.Yet the flash memory unit of writing is the page as previously mentioned, and it is the unit of erasing (that is physical blocks) less than flash memory.Therefore, if will carry out when action of erasing of physical blocks, must be first the data of the effective page in the physical blocks of desiring to erase be copied to the action of erasing that just can carry out physical blocks after other physical blocks.
Fig. 3 B is the running synoptic diagram that illustrates physical blocks according to the embodiment of the invention.
Please be simultaneously with reference to Fig. 3 A and 3B, for example, when host computer system desires to write data to logical blocks LB, suppose that controller 110 learns that by logic-entity mapping logical blocks LB is the physical blocks PD in the mapping (enum) data district 204 at present.Therefore, flash memory system 100 can carry out reproducting periods to the data among the physical blocks PD, and controller 110 can extract the physical blocks PD that physical blocks SD replaces data field 204 from spare area 206.Yet, when new data is write to physical blocks SD, can at once the whole valid data among the physical blocks PD all not moved to physical blocks SD and the physical blocks PD that erases.Specifically, controller 110 can be with the preceding valid data of desiring to write the page address among the physical blocks PD (promptly, page or leaf P0 and P1) be copied to physical blocks SD (as (a) of Fig. 3 B), and new data is write among the physical blocks SD (that is, page or leaf P2 and the P3 of physical blocks SD) (as (b) of Fig. 3 B).At this moment, the physical blocks SD that contains effective legacy data of part and new data can be in a temporary transient state, and this momentary state can be described as mother and child blocks.Keeping this transient state relation is because the valid data among the physical blocks PD might be in next operation (for example, the next one writes instruction) in become invalidly, therefore at once the whole valid data among the physical blocks PD are moved to physical blocks SD and may be caused meaningless moving.The action of temporarily keeping this kind transient state relation generally can be described as unlatching (open) mother and child blocks.
Afterwards, in the time the content of physical blocks PD and physical blocks SD really need being merged, controller 110 just can be merged into a physical blocks with physical blocks PD and physical blocks SD, promotes the service efficiency of block thus, and the action of this merging can be described as again closes (close) mother and child blocks.For example, shown in Fig. 3 B (c), when closing mother and child blocks, controller 110 can (that is, page or leaf P4～PN) be copied to physical blocks SD erases physical blocks PD then and is associated as spare area 206 with remaining valid data among the physical blocks PD, simultaneously, physical blocks SD is associated as data field 204, and in logic-entity mapping, the mapping of logical blocks LB is changed to physical blocks SD, finish rotate (or exchange) of physical blocks PD and physical blocks SD thus.
Because flash memory system 100 stores the access of the information of this relation for follow-up data when opening mother and child blocks, therefore can open the quantity of mother and child blocks and can set according to the size of memory buffer 110d in the controller 110.For example, flash memory system 100 can safeguard that at most the transient state of five groups of mother and child blocks concerns in the present embodiment.That is to say, opened state and 200 pairs of flash memory systems 100 of host computer system of five groups of mother and child blocks at flash memory system 100 and assigned in the example that writes instruction, if controller 100 can cut out wherein one group of mother and child blocks and finishes this and write instruction to open one group of new mother and child blocks during the mother and child blocks that the logical blocks that host computer system 200 is desired to write not is mapping has opened.
It must be appreciated, be to be that unit manages flash memory wafer 140 with the physical blocks in the present embodiment, and therefore above-mentioned is to be that unit is described with the physical blocks with the mode storage data of rotating (that is, opening and closing mother and child blocks).Yet, in another embodiment of the present invention, when managing flash memory wafer 140, above-mentionedly rotate, extract, running meeting such as exchange is that unit carries out with the solid element with the solid element that comprises a plurality of physical blocks.
Referring again to Fig. 2, in the present embodiment, though controller 110 is to be connected to flash memory wafer 140 with a data bus 149, yet flash memory wafer 140 has a plurality of flash memory crystal grain (promptly, the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148), therefore under time required required time of programming flash memory crystal grain as previously mentioned far above data bus 149 transmission data, the microprocessor unit 110a of controller 110 can write data with interleaved program (interleave program) pattern by the mechanical order of execute store administration module 110b, and the data that promote flash memory system 100 thus write efficient.
For example, controller 110 can be with the unit of writing (for example, the page) the data DATA that desires to write is divided into a plurality of subdata DATA1, DATA2, DATA3 and DATA4, the subdata alternately is write in the different flash memory crystal grain by data bus 149 with interlace mode then.That is to say, after controller 110 can transfer to the buffer zone of the first flash memory crystal grain 142 with subdata DATA1 earlier, by the programme running of subdata DATA1 of the first flash memory crystal grain 142.Then, when the first flash memory crystal grain 142 is in busy phase, after controller 110 can transfer to the buffer zone of the second flash memory crystal grain with data DATA2, by the programme running of subdata DATA2 of the second flash memory crystal grain 144.Then, when the first flash memory crystal grain 142 and the second flash memory crystal grain 144 all are in busy phase, after controller 110 can transfer to the buffer zone of the 3rd flash memory crystal grain 146 with data DATA3, by the programme running of subdata DATA3 of the 3rd flash memory crystal grain 146.At last, when the first flash memory crystal grain 142, the second flash memory crystal grain 144 and the 3rd flash memory crystal grain 146 all are in the phase of having much to do, after controller 110 can transfer to the buffer zone of the 4th flash memory crystal grain 148 with data DATA4, by the programme running of subdata DATA4 of the 4th flash memory crystal grain 148.Therefore, can writing down synchronously at partial data, shortening flash memory system 100 writes the required time of data.
What deserves to be mentioned is, in the present embodiment, when controller 110 belongs to the data of continuous logic address to flash memory wafer 140 in a large number from memory cache 130 transmission, and when carrying out interleaved program (interleaveprogram) pattern, controller 110 can transfer to flash memory wafer 140 with the data that (or staggered) mode at interval reads in the memory cache 130.
Specifically, controller 110 can will belong to the continuous logic address (promptly in the memory cache 130, logic sector) sector data (promptly, with the sector is the data of unit) arrange in order, and the size that the sector data of being arranged is grouped into logical blocks in order is the block data of unit.Then, the sector data that controller 110 can read from memory cache 130 with interlace mode and be that unit is sent in the flash memory crystal grain of flash memory wafer 140 with the page, wherein a page comprises 4 sector datas in the present embodiment.
Fig. 4 A illustrates the example schematic that transfers data to the flash memory wafer from memory cache according to the embodiment of the invention, and Fig. 4 B is the sequential chart that illustrates the interleaved program of Fig. 4 A institute demonstration example.This example only illustrates the part sevtor address, yet it must be appreciated in the memory cache 130 of Fig. 4 A for convenience of description, and memory cache 130 also can comprise other sevtor address.Similarly, in the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 of Fig. 4 A, only illustrate the part physical blocks, yet it must be appreciated that the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 also comprise other physical blocks.
Please refer to Fig. 4 A and Fig. 4 B, from host computer system 200, received the sector data SDATA (1)～(4n) that desires to write the continuous logic address at this hypothesis flash memory system 100, and be temporary in the memory cache 130.Controller 110 can be arranged sector data SDATA (1)～(4n) in order according to the order of logic sector LS (1)～LS (4n), and is the grouping sector data SDATA (1)～(4n) of unit with the logical blocks, wherein to belong to discriminably be 4 logical blocks LB1～LB4 to sector data SDATA (1)～(4n).
When controller 110 transmits sector data SDATA (1)～(4n) to flash memory wafer 140 by data bus 149, controller 110 can be (the transmission T (1) shown in Fig. 4 B) in the buffer zone of the physical blocks 142-1 that the data among logic sector LS (1)～LS (4) (that is sector data SDATA (1)～(4)) is sent to the first flash memory crystal grain 142 of unit with the page.Then, be in the busy phase (promptly at the first flash memory crystal grain 142, write during the data) time controller 110 data among logic sector LS (n+1)～LS (n+4) (, sector data SDATA (n+1)～(n+4)) can be sent in the buffer zone of physical blocks 144-1 of the second flash memory crystal grain 144 (the transmission T (2) shown in Fig. 4 B).Then, when the first flash memory crystal grain 142 and the second flash memory crystal grain 144 are in busy phase, controller 110 can be with the data among logic sector LS (2n+1)～LS (2n+4) (promptly, sector data SDATA (2n+1)～(2n+4)) is sent in the buffer zone of physical blocks 146-1 of the 3rd flash memory crystal grain 146 (the transmission T (3) shown in Fig. 4 B), and at the first flash memory crystal grain 142, when the second flash memory crystal grain 144 and the 3rd flash memory crystal grain 146 are in the phase of having much to do, data among logic sector LS (3n+1)～LS (3n+4) (that is sector data SDATA (3n+1)～(3n+4)) are sent in the buffer zone of physical blocks 148-1 of the 4th flash memory crystal grain 148 (the transmission T (4) shown in Fig. 4 B).
Then, controller 110 can confirm whether the first flash memory crystal grain 142 has finished writing of sector data SDATA (1)～(4), if the first flash memory crystal grain 142 has been finished writing (promptly of sector data SDATA (1)～(4), be in the non-busy phase) time, controller 110 can be sent to the data among logic sector LS (2)～LS (8) (that is sector data SDATA (2)～(8)) in the buffer zone of physical blocks 142-1 of the first flash memory crystal grain 142 (the transmission T (5) shown in Fig. 4 B) again.Then, controller 110 can judge whether the second flash memory crystal grain 144 has finished writing of sector data SDATA (n+1)～(n+4), if it is fashionable that the second flash memory crystal grain 144 has been finished writing of sector data SDATA (n+1)～(n+4), controller 110 can be sent to the data among logic sector LS (n+5)～LS (n+8) (that is sector data SDATA (n+5)～(n+8)) in the buffer zone of physical blocks 144-1 of the second flash memory crystal grain 144 (the transmission T (6) shown in Fig. 4 B) again.Then, controller 110 can judge whether the 3rd flash memory crystal grain 146 has finished writing of sector data SDATA (2n+1)～(2n+4), if it is fashionable that the 3rd flash memory crystal grain 146 has been finished writing of sector data SDATA (2n+1)～(2n+4), controller 110 can be sent to the data among logic sector LS (2n+5)～LS (2n+8) (that is sector data SDATA (2n+5)～(2n+8)) in the buffer zone of physical blocks 146-1 of the 3rd flash memory crystal grain 146 (the transmission T (7) shown in Fig. 4 B) again.Then, controller 110 can judge whether the 4th flash memory crystal grain 148 has finished writing of sector data SDATA (3n+1)～(3n+4), if it is fashionable that the 4th flash memory crystal grain 148 has been finished writing of sector data SDATA (3n+1)～(3n+4), controller 110 can be sent to the data among logic sector LS (3n+5)～LS (3n+8) (that is sector data SDATA (3n+5)～(3n+8)) in the buffer zone of physical blocks 148-1 of the 4th flash memory crystal grain 148 (the transmission T (8) shown in Fig. 4 B) again.Afterwards, till controller 110 all transfers to flash memory wafer 140 with the data among logic sector LS (1)～LS (4n) (that is, finish the transmission T (1) shown in Fig. 4 B～T (n) till) by that analogy.
Based on above-mentioned, by using the interleaved program pattern, sector data SDATA (1)～(4n) is sent in the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 of flash memory wafer 140 with the recycle design alternately with staggered by data bus 149.Therefore, controller 110 can transfer to the sector data that belongs in the same block data in the physical blocks of same flash memory crystal grain.
Fig. 5 is the process flow diagram that illustrates data transmission step according to the embodiment of the invention, and wherein these steps are that the mechanical order of the microprocessor unit 110a execute store administration module 110b of controller 110 is finished.It must be appreciated that data transmission step proposed by the invention is not limited to execution sequence shown in Figure 5, these those skilled in the art can change the order of data transmission step according to spirit of the present invention arbitrarily.In addition, because the emphasis of present embodiment is to describe to use the interleaved program pattern to write the data transfer mode of data to flash memory wafer 140, so the step that Fig. 5 illustrated is only described at the processing that writes instruction.Processing for reading command or other instructions then can be carried out according to general known technology, is not described in detail at this.
Please refer to Fig. 5, after flash memory system 100 is connected to host computer system 200 and starts, step S501 middle controller 110 can provide with the logic sector be the logical address of unit to host computer system 200 to carry out the access of data.As mentioned above, providing with the logic sector at this is that the logical address of unit is that to cooperate host computer system 200 be the access features of unit with the sector.
Can provide logical blocks at step S503 middle controller 110, and logic sector is converted to the logical blocks of mapping.As mentioned above, flash memory wafer 140 is to be that unit carries out access with the physical blocks in the present embodiment, so controller 110 need be converted to the logic sector of host computer system 200 accesses the logical blocks based on the size of physical blocks.
Then, wait for the data that write instruction and desire to write that transmitted from host computer system 200 with reception in 110 meetings of step S505 middle controller.Afterwards, the data that received can be temporary in the memory cache 130 at step S507 middle controller 110.
When controller 110 desires will be temporary in the memory cache 130 data programing (promptly, write) during to flash memory wafer 140, can will be stored in the sector data that belongs to the continuous logic sector in the memory cache 130 at step S509 middle controller 110 and arrange and be grouped into a plurality of block datas in order.Particularly, controller 110 can be with the corresponding above-mentioned logical blocks that provides of each block data when the grouping sector data.If the block data that is divided into groups is not enough to fill up pairing logical blocks (promptly, only upgrade a part of data in this logical blocks) time, controller 110 can be merged into a complete block data with the desire data updated with effective legacy data of institute's counterlogic block, the action shown in Fig. 3 B just, wherein the whole process also of data can be finished in the memory buffer 110d in memory cache 130 or the controller 110.
At last, can by data bus 149 sector data in institute's packet zone blocks of data be sent to flash memory wafer 140 respectively and write sector data with the interleaved program pattern in flash memory crystal grain 142,144,146 and 148 with interlace mode at step S511 middle controller 110.Behind step S511, the data transmission flow process can be back to waits among the step S505 that the next one writes instruction.Though be not illustrated among Fig. 5, the data transmission step that skill person can understand Fig. 5 is easily known in this field can receive shutdown or power interruption instruction back is finished.
What deserves to be mentioned is, the physical blocks of flash memory wafer 140 is to store the data that host computer system 200 writes to logical blocks in the mode of rotating as mentioned above, therefore in order can in the process that physical blocks is constantly rotated, institute's data updated to be dispersed in a plurality of flash memory crystal grain fifty-fifty, when controller 110 extracts physical blocks and replaces physical blocks in the logical blocks institute mapped data district of desiring to write 204 from spare area 206, controller 110 can judge that the physical blocks of desiring to be updated is to belong to that flash memory crystal grain (promptly in data field 204, the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148) in physical blocks, and only from spare area 206, extract corresponding under the physical blocks of flash memory crystal grain carry out the running of above-mentioned replacement.
Specifically, spare area 206a, spare area 206b, spare area 206c and spare area 206d can be divided into respectively according to the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 in spare area 206.When the physical blocks of desiring to be updated is the physical blocks of the first flash memory crystal grain 142, then from spare area 206a, extract physical blocks, when the physical blocks of desiring to be updated is the physical blocks of the second flash memory crystal grain 144, then from spare area 206b, extract physical blocks, when the physical blocks of desiring to be updated is the physical blocks of the 3rd flash memory crystal grain 146, then from spare area 206c, extract physical blocks, and when the physical blocks of desiring to be updated is the physical blocks of the 4th flash memory crystal grain 148, then from spare area 206d, extract physical blocks.
Particularly, open mother and child blocks, so controller 110 might be opened sub-block for five female blocks that belong to same flash memory crystal grain simultaneously owing to only can extract the physical blocks of corresponding spare area in the present embodiment.Therefore, in the present embodiment, in each spare area (that is, spare area 206a, spare area 206b, spare area 206c and spare area 206d), all must dispose the physical blocks number of enough handling five groups of mother and child blocks.In addition, controller 110 can be set up respectively with logic-entity mapping of maintenance for the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 of flash memory wafer 140 and write down above-mentioned mapping relations.That is to say, can write down in the present embodiment and upgrade 4 logic-entity mapping.
In addition, because the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148 have independently logic-entity mapping, therefore in another embodiment of the present invention, also can average damage (wear-leveling) program of smearing respectively at the first flash memory crystal grain 142, the second flash memory crystal grain 144, the 3rd flash memory crystal grain 146 and the 4th flash memory crystal grain 148.The average abrasion program is the technology that this field is known, and omits the description of its detailed operation at this.
In addition, because controller 110 is when opening mother and child blocks, therefore mother and child blocks all can be to belong to same flash memory crystal grain, and in another embodiment of the present invention, controller 110 can use copies back (copyback) instruction to quicken data-moving (shown in Fig. 3 B) between the mother and child blocks.
In sum, data transmission method proposed by the invention is when using the interleaved program pattern, be unit and discontinuous mode with the logical blocks with the data interlace in the memory cache be sent in the flash memory crystal grain of flash memory wafer, therefore the data that can avoid belonging to the continuous logic address are dispersed in the different flash memory crystal grain, the writing speed when being lifted at follow-up more new data thus and reduce the number of times of erasing of physical blocks.In addition, using under the transmission mode of the present invention, the physical blocks of the storage data of rotating all can belong to same flash memory crystal grain, therefore can use copies back to instruct writing of expedited data.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (19)
1. data transmission method, be applicable to a flash memory system, wherein this flash memory system has a plurality of physical blocks, and these physical blocks are grouped into a plurality of flash memory groups and these flash memory groups are connected with same data bus, and this data transmission method comprises:
A plurality of logic sectors and a plurality of logical blocks are provided, and wherein these logic sectors are these logical blocks of mapping, and these logical blocks are these physical blocks of mapping;
A plurality of sector datas that will belong to continuous these logic sectors are grouped into a plurality of block datas in order, and wherein each described block data is corresponding one of them described logical blocks; And
These sector datas that will belong to same these block datas transmit and write in same these physical blocks.
2. data transmission method as claimed in claim 1, comprise that also be that unit respectively be sent to these sector datas in these flash memory groups by this data bus with these block datas with an interlace mode, wherein can synchronously write to these flash memory groups to these sector datas of small part.
3. data transmission method as claimed in claim 2, wherein each flash memory group is made up of at least one memory crystal grain, and the part of the physical blocks of each memory crystal grain can be defined as a spare area,
These sector datas that wherein belong to same these block datas can be written in the physical blocks of being extracted from this spare area of same these flash memory crystal grain.
4. data transmission method as claimed in claim 3 also is included as each described flash memory crystal grain and writes down one logic-entity mapping individually.
5. data transmission method as claimed in claim 3 also is included as each described flash memory crystal grain and carries out one individually and on average smear the damage program.
6. data transmission method as claimed in claim 3 also is included in and carries out copies back instruction in each described flash memory crystal grain, with copy data between these physical blocks of each described flash memory crystal grain.
7. a controller is applicable to a flash memory system, and wherein this flash memory system has a plurality of physical blocks, and these physical blocks are grouped into a plurality of flash memory groups and these flash memory groups are connected with same data bus, and this controller comprises:
One microprocessor unit;
One flash interface is coupled to this microprocessor unit;
One memory buffer is coupled to this microprocessor unit; And
One memory management module is coupled to this microprocessor unit, and has a plurality of machine instructions that can be carried out by this microprocessor unit, and so that this flash memory system is finished a plurality of data transmission step, these data transmission step comprise:
A plurality of logic sectors and a plurality of logical blocks are provided, and wherein these logic sectors are these logical blocks of mapping, and these logical blocks are these physical blocks of mapping;
A plurality of sector datas that will belong to continuous these logic sectors are grouped into a plurality of block datas in order, and wherein each described block data is corresponding one of them described logical blocks; And
These sector datas that will belong to same these block datas transmit and write in same these physical blocks.
8. controller as claimed in claim 7, wherein these data transmission step comprise that also be that unit respectively be sent to these sector datas in these flash memory groups by this data bus with these block datas with an interlace mode, wherein can synchronously write to these flash memory groups to these sector datas of small part.
9. controller as claimed in claim 8, wherein each flash memory group is made up of at least one memory crystal grain, and the part of the physical blocks of each memory crystal grain can be defined as a spare area, and these sector datas that wherein belong to same these block datas can be written in the physical blocks of being extracted from this spare area of same these flash memory crystal grain.
10. controller as claimed in claim 9, wherein these data transmission step also are included as each described flash memory crystal grain and write down one logic-entity mapping individually.
11. controller as claimed in claim 9, wherein these data transmission step also are included as each described flash memory crystal grain and carry out one individually and on average smear the damage program.
12. controller as claimed in claim 9, wherein these data transmission step also are included in and carry out copies back instruction in each described flash memory crystal grain with copy data between these physical blocks of this each flash memory crystal grain.
13. controller as claimed in claim 7, wherein this flash memory system is dish, a flash card or a solid state hard disc with oneself.
14. a flash memory system comprises:
A plurality of physical blocks, these physical blocks are grouped into a plurality of flash memory group;
At least one data bus is connected to these flash memory groups;
One memory cache;
A connector; And
One controller is electrically connected to this at least one data bus, this memory cache and this connector, and this controller can be carried out a plurality of machine instructions of a memory management module to finish a plurality of data transmission step, and these data transmission step comprise:
A plurality of logic sectors and a plurality of logical blocks are provided, and wherein these logic sectors are these logical blocks of mapping, and these logical blocks are these physical blocks of mapping;
A plurality of sector datas that will belong to continuous these logic sectors are grouped into a plurality of block datas in order, and wherein each described block data is corresponding one of them described logical blocks; And
These sector datas that will belong to same these block datas transmit and write in same these physical blocks.
15. flash memory system as claimed in claim 14, wherein these data transmission step comprise that also be that unit respectively be sent to these sector datas in these flash memory groups by this data bus with these block datas with an interlace mode, wherein can synchronously write to these flash memory groups to these sector datas of small part.
16. flash memory system as claimed in claim 15, wherein each flash memory group is made up of at least one memory crystal grain, and the part of the physical blocks of each memory crystal grain can be defined as a spare area, and these sector datas that wherein belong to same these block datas can be written in the physical blocks of being extracted from this spare area of same these flash memory crystal grain.
17. flash memory system as claimed in claim 16, wherein these data transmission step also are included as each described flash memory crystal grain and write down one logic-entity mapping individually.
18. flash memory system as claimed in claim 16, wherein these data transmission step also are included as each described flash memory crystal grain and carry out one individually and on average smear the damage program.
19. flash memory system as claimed in claim 16, wherein these data transmission step also are included in and carry out copies back instruction in each described flash memory crystal grain with copy data between these physical blocks of this each flash memory crystal grain.
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