CN101616047B - Dispatching method of WorldFIP distributed intelligent control network - Google Patents
Dispatching method of WorldFIP distributed intelligent control network Download PDFInfo
- Publication number
- CN101616047B CN101616047B CN200910089946A CN200910089946A CN101616047B CN 101616047 B CN101616047 B CN 101616047B CN 200910089946 A CN200910089946 A CN 200910089946A CN 200910089946 A CN200910089946 A CN 200910089946A CN 101616047 B CN101616047 B CN 101616047B
- Authority
- CN
- China
- Prior art keywords
- functional block
- instruction
- starting point
- terminal region
- fan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a dispatching method of WorldFIP distributed intelligent control network in the technical field of autocontrol. The dispatching method comprises: before a control system starts to run, manufacturing variables corresponding to each basic node consumption variable are established on a link scheduler; compel data CD is written into the manufacturing variables; the scheduling items of variable exchange are added into a bus scheduling table; when the network starts, the variable exchange of each basic node is generated in the network according to a timing sequence specified by the scheduling table; after receiving the compel data CD from the consumption variable, the basic node performs the current order pointed by a pointer of an instruction area, and the next order is pointed after performing the current order. The invention solves the problem of the design and realization of a fully-distributed intelligent system based on a functional block and a functional block application process in a field-level intelligent control network, and realizes real-time fully-distributed intelligent control with high reliability.
Description
Technical field
The invention belongs to the automatic control technology field, relate in particular to a kind of dispatching method of WorldFIP distributed intelligent control network.
Background technology
In recent years, field bus technique, distributed intelligence network have obtained increasingly extensive application in the process control field.Along with the continuous expansion of the continuous complicated and capacity of controlled process, the reliability of control system there has been higher, harsher requirement.In the overwhelming majority field bus technique, irredundant this fact of field level becomes the major obstacle that limiting control system field level reliability improves in the field bus technique application.WorldFIP (World Factory Instrumentation Protocol) is one of international standard for Fieldbus; It is a kind of fieldbus towards Industry Control; The fieldbus that its unique double-bus redundancy system is other types is incomparable, and forward-looking and historical meaning makes it be highly suitable for high reliability process control field; Also, obtained attention and application more and more widely in the process control field for the problems referred to above provide desirable solution.The WorldFIP field bus technique has all obtained extremely successful application in power station control systems such as Chinese mountain range nuclear power plant difficult to understand, army provisions city power plant, shown powerful development trend.At present, product that technological development goes out based on WorldFIP in the world and system still are being on the level more than the controlled stage, also are unrealized based on the full distributed intelligent control network of site intelligent node.Communicate by letter with field level based on the site intelligent node, it is a kind of most important mode that distributed intelligent control network is realized distributed process control that functional block and functional block are used, and is the key problem that distributed intelligent control network is realized.
Summary of the invention
The objective of the invention is to, propose a kind of dispatching method of WorldFIP distributed intelligent control network, in order to realize full distributed intelligent control network based on the site intelligent node to the problems referred to above.This method is the basis with the functional block application model, and the functional block application model comprises data partition model and the agreement client layer data model in the network service in the field level intelligent node.
Technical scheme of the present invention is that a kind of dispatching method of WorldFIP distributed intelligent control network is characterized in that said method comprises the following steps:
Step 1: before control system starts operation, on the link scheduling device, set up manufacturing variables corresponding to each fundamental node consumption variable;
Step 2: will force data CD to be written in the said manufacturing variables;
Step 3: the schedule entries of variable exchange is added in the bus scheduling table;
Step 4: after network startup,, on network, produce the variable exchange of each fundamental node according to the sequential of dispatch list regulation;
Step 5: fundamental node is after receiving pressure data CD from the consumption variable, the present instruction of the current sensing of execution command district's pointer is pointed to next bar and instructed after being finished.
Said fundamental node comprises functional block, and said functional block is divided into 4 districts, is respectively: instruction area, input terminal region, output terminal region, include parameter region; Wherein, said instruction area is used to store all instructions; Said input terminal region is used to store all fan-in certificates; Said output terminal region is used to store all fan-out certificates; The said parameter region that includes is used to store containing parameter in all.
Said instruction comprises the functional block instruction; Comprising 5 fields in its structure, is respectively that instruction sign, functional block type, functional block fan-in certificate starting point index value, the functional block fan-out in this functional block input terminal region includes the starting point byte offsets in the parameter region according to the starting point index value in this functional block output terminal region and the interior containing parameter of functional block in this functional block.
Said instruction comprises link order; Comprising 4 fields in its structure, is respectively the address and the starting point index value of terminal point functional block in this functional block input terminal region of the fundamental node at starting point index value in this functional block output terminal region of link order sign, starting point functional block, terminal point functional block place.
Said input terminal region and output terminal region all use 4 bytes as data storage cell.
Containing parameter uses byte as data storage cell in said, and adjacent arrangement between a plurality of parameters is discerned each parameter with side-play amount and data length.
Said functional block instruction and link order are the mixed in equal amounts storage in the instruction area.
When said present instruction was the functional block instruction, said step 5 comprised the following steps:
Step 51: fundamental node according to the starting point index value in this functional block input terminal region, takes out all fan-in certificates by this functional block fan-in in the functional block instruction from input terminal region;
Step 52: fundamental node includes the starting point byte offsets in the parameter region by the interior containing parameter of this functional block in the functional block instruction in this functional block, from including the interior containing parameter that parameter region takes out;
Step 53: fundamental node uses the fan-in certificate and includes calculation of parameter to obtain the fan-out certificate by the functional block algorithm;
Step 54: fundamental node, is written to the fan-out certificate in the functional block output terminal region according to the starting point index value in this functional block output terminal region by functional block fan-out;
Step 55: the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district.
When said present instruction was local link order, said step 5 comprised the following steps:
Step 51 ': in link order,, obtain the fan-out certificate of starting point functional block output terminal region according to the starting point index value of starting point functional block in this functional block output terminal region.
Step 52 ': according to the starting point index value of terminal point functional block in this functional block input terminal region, with the fan-out of starting point functional block output terminal region according to copying in the terminal point functional block input terminal region;
Step 53 ': the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district.
When said present instruction was long-range link order, said step 5 comprised the following steps:
Step 51 ": in link order,, obtain the fan-out certificate of starting point functional block output terminal region according to the starting point index value of starting point functional block in its fundamental node output terminal region;
Step 52 ": the fan-out certificate of starting point functional block output terminal region is written in the message, and is packaged into message frame;
Step 53 ": the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district;
Step 54 ": the network scheduling node sends message inquiry frame to the fundamental node of starting point functional block;
Step 55 ": the fundamental node of starting point functional block sends to message frame on the network;
Step 56 ": after the fundamental node of terminal point functional block is received message frame, message frame is unpacked, read the message in the message frame, by the terminal point functional block input terminal region index that indicates in the message, float type data are written in the terminal point functional block input terminal region then.
The form of message comprises three fields in the said message frame, is respectively: be respectively: purpose identification code, input index and float type data; Wherein, the purpose identification code takies 1 byte, and the input index takies 2 bytes, 4 bytes of float type data occupancy; The input index field is used to store the input index of the terminal point functional block of long-range connection at its base node; The data format of float type The data floating point type is used to store the fan-out certificate of starting point functional block at the output terminal region of its fundamental node.
What said message frame adopted is the mode of destination address addressing.
Effect of the present invention is; A kind of dispatching method of WorldFIP distributed intelligent control network is proposed through the present invention; Solved in the field level intelligent control network full distributed design of intellectual system and problem of implementation effectively, and then realized the real-time full distributed Based Intelligent Control of high reliability based on functional block and functional block application process.
Description of drawings
Fig. 1 is based on fundamental node " passive type " the scheduling sketch map of forcing data;
Fig. 2 is the functional block order structure figure in the fundamental node;
Fig. 3 is the link order structure chart in the fundamental node;
Fig. 4 is fundamental node functional block partitioned organization figure;
Fig. 5 is local connection of single task functional module and scheduling sketch map; Wherein, (a) being the local sketch map that connects of single task functional module, (b) is the local scheduling sketch map that connects of single task functional module;
Fig. 6 is a WorldFIP message frame form;
Fig. 7 is the client layer data model in the WorldFIP communication protocol;
Fig. 8 is long-range connection of single task functional module and scheduling sketch map; Wherein, (a) being the long-range connection sketch map of single task functional module, (b) is the long-range connection scheduling of single task functional module sketch map;
Fig. 9 is local connection of multitask function module and scheduling sketch map; Wherein, (a) being the local sketch map that connects of multitask function module, (b) is the local scheduling sketch map that connects of multitask function module;
Figure 10 is long-range connection of multitask function module and scheduling sketch map; Wherein, (a) being the long-range connection sketch map of multitask function module, (b) is the long-range connection scheduling of multitask function module sketch map.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment is elaborated.Should be emphasized that following explanation only is exemplary, rather than in order to limit scope of the present invention and application thereof.
In the application process dispatching algorithm that the present invention designed; Used for reference FF fieldbus functional block process scheduling algorithm; Consider WorldFIP and the difference of FF fieldbus on traffic model; Adopt the execution pattern of " passive type " fully, be different from the long-range connection passive type of FF fieldbus and be connected active dispatching algorithm with this locality.Under this pattern; From the link scheduling device to fundamental node; Have only and force data CD transmitting, these CD data may be defined as a normal value, and it is dispatched by the link scheduling device that the instruction of fundamental node is carried out; Only behind the pressure data CD that receives from the link scheduling device, could carry out present instruction, after executing present instruction, wait for being scheduled once more by the instruction pointer indication; The data of between each fundamental node, transmitting then are the data that long-range or local need exchange between each functional block in the functional block application process, are not normal value.It is repeatably that functional block is carried out, and repeat is a grand cycle at every turn, and the execution of any control command of primary mental ability intranodal is complete scheduled in the grand cycle all.
This based on " passive type " scheduling of forcing data, its algorithm can be described as:
Network link scheduler mode with the exchange of periodicity variable on the time point that dispatch list is confirmed is sent pressure data CD to the primary mental ability node, after fundamental node is received this CD, carries out present instruction.
Specifically be embodied as:
Step 1: before control system starts operation, on the link scheduling device, set up manufacturing variables corresponding to each fundamental node consumption variable.
Fig. 1 is based on fundamental node " passive type " the scheduling sketch map of forcing data.Among Fig. 1, the consumption variable of fundamental node N1 is 0x0501, and the consumption variable of fundamental node N2 is 0x0502, then on the link scheduling device, sets up two manufacturing variables 0x0501,0x0502, the consumption variable of respectively corresponding two fundamental nodes.
Fundamental node among the present invention is a kind of site intelligent node, comprises functional block.Functional block is divided into 4 districts, is respectively: instruction area, input terminal region, output terminal region, include parameter region; Wherein, the instruction area is used to store all instructions; Input terminal region is used to store all functions piece fan-in certificate; Output terminal region is used to store all functions piece fan-out certificate; Include parameter region and be used to store containing parameter in all functions piece.Functional block input terminal region and functional block output terminal region all use 4 bytes as data storage cell.
Functional block instruction area instructions stored comprises the functional block instruction, and Fig. 2 is the functional block order structure in the fundamental node.Among Fig. 2, the functional block order structure comprises 5 fields, and its meaning is respectively:
Flag: instruction flag;
FB_type: functional block type;
In_index: this functional block fan-in is according to the starting point index value in this functional block input terminal region;
Out_index: this functional block fan-out is according to the starting point index value in this functional block output terminal region;
Offset: the interior containing parameter of this functional block includes the starting point byte offsets in the parameter region in this functional block.Containing parameter uses byte as data storage cell in the functional block, and adjacent arrangement between a plurality of parameters is discerned each parameter with side-play amount and data length.
Functional block instruction area instructions stored also comprises link order, and Fig. 3 is the link order structure chart in the fundamental node.Among Fig. 3, the link order structure comprises 4 fields, and its meaning is respectively:
Flag: link order sign;
Out_index: the starting point index value of the starting point functional block of connection in the functional block output terminal region;
Addr: the address of the terminal point functional block place fundamental node of connection;
In_index: the starting point index value of the terminal point functional block of connection in the functional block input terminal region.
Functional block instruction and link order are the mixed in equal amounts storage in the functional block instruction area.
Fig. 4 is fundamental node functional block partitioned organization figure.Among Fig. 4, shown a functional block instruction storage structure in the functional block instruction area 41.In the functional block order structure of storage, first and second is respectively instruction sign and functional block type in the functional block instruction area 41.The 3rd memory function piece fan-in is according to the starting point index value in this functional block input terminal region, the respective data storage district of the direct direction-pointing function piece of this index value input terminal region 42 (4 bytes).The 4th memory function piece fan-out is according to the starting point index value in this functional block output terminal region, the respective data storage district of the direct direction-pointing function piece of this index value output terminal region 43 (4 bytes).The starting point byte offsets of the interior containing parameter of the 5th memory function piece in this functional block includes parameter region 44.
Step 2: will force data CD to be written in the above-mentioned manufacturing variables in storage and the bus arbitration equipment.
Step 3: with the schedule entries of variable exchange (for this example be 0x0501, ID_DAT}, { 0x0502 ID_DAT}) adds in the bus scheduling table;
Step 4: after network startup,, on network, produce the variable exchange of each fundamental node according to the sequential of dispatch list regulation;
Step 5: fundamental node is after receiving pressure data CD from the consumption variable, the present instruction of the current sensing of execution command district's pointer is pointed to next bar and instructed after being finished.
Said step 5 realizes through the functional block in the base node.Functional block is used and is divided into application of single task functional block and the application of multitask function piece.In the single task functional block was used, whole application process only comprised one and is called one " functional block application task " from the breast the tape complete connection of functional block of starting point functional block at this, and connectionless functional block is not regarded as the functional block application task; In the multitask function piece was used, whole application process comprised plural functional block application task, and has concurrency between each task.Functional block application process dispatching algorithm under the execution pattern of " passive type " is divided into the scheduling of single task functional block application and the scheduling that the multitask function piece is used fully.Any kind functional block is used and always can be decomposed into following four kinds of embodiment or its combination.
Embodiment one:
Fig. 5 is local connection of single task functional module and scheduling sketch map; Wherein, (a) being the local sketch map that connects of single task functional module, (b) is the local scheduling sketch map that connects of single task functional module.
Among Fig. 5 (a), N1 represents base node, and FB1 and FB2 represent starting point functional block and the terminal point functional block in the fundamental node respectively, and the single task functional module is local to be connected and be meant being connected of starting point functional block that fundamental node is interior and terminal point functional block.
Among Fig. 5 (b), CD (N1) representative is sent to fundamental node N1 and is forced data CD, and the instruction of starting point functional block is carried out in FB1 (N1) representative, and link order is carried out in LN (N1) representative, and the instruction of terminal point functional block is carried out in FB2 (N1) representative; Transverse axis is represented scheduling time, and the scale on the transverse axis is represented chronomere, and a chronomere can be 5 milliseconds, also can be 10 milliseconds, and this depends on bus scheduling equipment.In conjunction with Fig. 5 (b), step 5 of the present invention specifically realizes through following embodiment:
101: zero hour scheduling time (0 on time transverse axis is located), the scheduling node on the bus network sends one to this fundamental node N1 and forces data CD, i.e. CD (N1);
102: in second moment of scheduling time (20 on time transverse axis is located), fundamental node N1 carries out present instruction after receiving and forcing data CD.Present instruction is functional block instruction, and promptly during FB1 (N1), concrete implementation is:
1021: fundamental node N1 takes out all fan-in certificates by the starting point index value of this functional block input in this functional block input terminal region in the functional block instruction from input terminal region.
1022: fundamental node includes the starting point byte offsets in the parameter region by the interior containing parameter of this functional block in the functional block instruction in this functional block, from including the interior containing parameter that parameter region takes out.
1023: fundamental node uses the fan-in certificate and includes calculation of parameter to obtain the fan-out certificate by the functional block algorithm.
1024: fundamental node is written to the fan-out certificate in the functional block output terminal region by the starting point index value of this functional block output in this functional block output terminal region.
1025: the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district.
103: scheduling time next (60 on time transverse axis is located) constantly, the instruction of FB1 (N1) starting point functional block is finished, and bus network is sent one to this fundamental node N1 again and forced data CD.
104: scheduling time next (80 on time transverse axis is located) constantly, fundamental node N1 begins to carry out new present instruction, i.e. LN1 (N1) after receiving and forcing data CD.If new present instruction is local link order, then its concrete implementation is:
1041: in link order,, obtain the fan-out certificate of starting point functional block output terminal region according to the starting point index value of starting point functional block in this functional block output terminal region.
1042: the fan-out certificate of starting point functional block output terminal region is copied in the terminal point functional block input terminal region; The instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district.
105: scheduling time next (100 on time transverse axis is located) constantly, link order LN1 (N1) is finished, and link scheduling sent to fundamental node N1 once more and forced data CD this moment, ordered about it and carried out next instruction.
106: when next (100 on time transverse axis is located) constantly arrival of scheduling time; Fundamental node N1 begins to carry out present instruction, and present instruction is again functional block instruction, i.e. a FB2 (N1); Its implementation is identical with the implementation of FB1 (N1), can be referring to step 1021-1025.
The white hollow arrow is depicted as the scheduling of non-periodic variable exchange or message communication among Fig. 5.
Embodiment two:
When node adopted the MicroFIP communication chip of relative low price, the exchanges data between each fundamental node can't directly be carried out through the exchange of periodicity variable, can only pass through the transfer of link scheduling equipment, causes the reduction of communication efficiency.In the present invention,, adopted internodal periodically packet exchanged form, will data packets for transmission be contained in the message frame and transmit for addressing this problem, promptly guaranteed data can be between node directly exchange guarantee the real-time of communication again.
Its reference model of WorldFIP field bus technique has also adopted physical layer, data link layer and the application layer in seven layers of the ISO/OSI reference models, all follows the WorldFIP standard for every layer.
The WorldFIP network communication protocol is a kind of communication protocol of master-slave mode.Adopt two kinds of transfer of data exchanged forms on the network: based on the transfer of data of variable switch type with based on the transfer of data of the message formula of physical addressing.On the WorldFIP network, use the frame of following type to carry out exchanges data.
Exchange based on variable:
ID_DAT: send by bus arbiter, be used to start the data transmission procedure that once exchanges based on variable;
RP_DAT: send by slave unit, be used to respond ID_DAT, realize transfer of data based on the variable exchange;
Based on message transmissions:
ID_MSG: send by bus arbiter, be used to start once data transmission procedure based on message;
RP_MSG: send by slave unit, be used to respond ID_MSG, realize transfer of data based on message;
RP_MSG_ACK: send by bus arbiter, be used to inform that the slave unit message receives;
RP_FIN: send by slave unit, be used to respond RP_MSG_ACK, accomplish once transfer of data based on message.
In the present invention; In view of the WorldFIP bus has high transmission reliability; For improving communication efficiency, adopted the form of session of the most succinct " inquiry+answer " in the data transmission procedure based on message, do not re-use the form of session of affirmation (RP_MSG_ACK).
Fig. 6 is a WorldFIP message frame form.In the WorldFIP of Fig. 6 frame format, other fields except that " message " all are the appointments of WorldFIP communication protocol, and are irrelevant with client layer; It is " message " field that the user can control with what freely use.Though WorldFIP field bus communication reference model all is standardized on physical layer, data link layer and application layer; But it should be noted that; The notion that does not also have at present client layer in the WorldFIP traffic model; Lack the client layer standard, the user data of being packed by application layer in the message frame does not also form a unified data standard, is being in the starting stage in the research of this problem both at home and abroad at present.To " message " field among Fig. 6, is that application target propose client layer data model in a kind of WorldFIP field bus communication agreement with the process control at this.
Fig. 7 is the client layer data model in the WorldFIP communication protocol.Fig. 7 in fact is exactly the form of the message of the present invention's proposition.Among Fig. 7, the form of message comprises three fields in the message frame, is respectively: purpose identification code, input index and float type data; Wherein, the purpose identification code takies 1 byte, and the input index takies 2 bytes, 4 bytes of float type data occupancy; The input index field is used to store the input index of the terminal point functional block of long-range connection at its base node; The data format of float type The data floating point type is used to store the fan-out certificate of starting point functional block at the output terminal region of its fundamental node.
Fig. 8 is long-range connection of single task functional module and scheduling sketch map; Wherein, (a) being the long-range connection sketch map of single task functional module, (b) is the long-range connection scheduling of single task functional module sketch map.
Among Fig. 8 (a); N1 and N2 represent base node respectively; FB1 and FB2 represent starting point functional block and the terminal point functional block in fundamental node N1 and the fundamental node N2 respectively, and the long-range connection of single task functional module is meant being connected of starting point functional block and the interior terminal point functional block of fundamental node N2 in the fundamental node N1.
Among Fig. 8 (b); CD (N1) representative is sent to fundamental node N1 and is forced data CD; The instruction of starting point functional block is carried out in FB1 (N1) representative, and long-range link order is carried out in LN (N1) representative, and ID_MSG (N1) expression is sent message inquiry frame to fundamental node N1; The message frame RP_MSG that RP_MSG (N1-N2) representative will have been packed sends on the network, and the instruction of terminal point functional block is carried out in FB2 (N1) representative; Transverse axis is represented scheduling time, and the scale on the transverse axis is represented chronomere, and a chronomere can be 5 milliseconds, also can be 10 milliseconds, and this depends on bus scheduling equipment.In conjunction with Fig. 8 (b), step 5 of the present invention specifically realizes through following embodiment:
201: zero hour scheduling time (0 on time transverse axis is located), the scheduling node on the bus network sends one to this fundamental node N1 and forces data CD, i.e. CD (N1);
202: in second moment of scheduling time (20 on time transverse axis is located), fundamental node N1 carries out present instruction after receiving and forcing data CD.Present instruction is functional block instruction, and promptly during FB1 (N1), concrete implementation is identical with step 1021-1025.
203: scheduling time next (60 on time transverse axis is located) constantly, the instruction of FB1 (N1) starting point functional block is finished, and bus network is sent one to this fundamental node N1 again and forced data CD.
204: scheduling time next (80 on time transverse axis is located) constantly, fundamental node N1 begins to carry out new present instruction, i.e. LN1 (N1) after receiving and forcing data CD.At this moment, new present instruction is long-range link order, and then its concrete implementation is:
2041: in link order,, obtain the fan-out certificate of starting point functional block output terminal region according to the starting point index value of starting point functional block in its fundamental node N1 output terminal region.
2042: the fan-out certificate of starting point functional block output terminal region is written in the message, and is packaged into message frame.The message format that the form of message indicates with reference to Fig. 7.The WorldFIP message frame form that message frame indicates with reference to Fig. 6.
2043: the instruction pointer of starting point functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district.
2044: scheduling time next (100 on time transverse axis is located) constantly, scheduling node sends message inquiry frame ID_MSG (N1) to the fundamental node N1 of starting point functional block.
2045: scheduling time next (120 on time transverse axis is located) constantly, the fundamental node N1 of starting point functional block sends to message frame on the network.
2046: because message transmission employing is the mode of destination address addressing; So after sending end, fundamental node N2 has just received this message frame, unpacks then; Read the float type data in the message; Index address by the terminal point functional block input terminal region that indicates in the message is written to float type data in the terminal point functional block input terminal region, promptly is written in the functional block input terminal region of base node N2.
205: scheduling time next (140 on time transverse axis is located) constantly, link scheduling sends to fundamental node N2 and forces data CD, orders about it and carries out next instruction.
206: when next (160 on time transverse axis is located) constantly arrival of scheduling time; Fundamental node N2 begins to carry out present instruction, and present instruction is again functional block instruction, i.e. a FB2 (N2); Its implementation is identical with the implementation of FB1 (N1), can be referring to step 1021-1025.
The white hollow arrow is depicted as the scheduling of non-periodic variable exchange or message communication among Fig. 8.
Embodiment three:
Fig. 9 is local connection of multitask function module and scheduling sketch map; Wherein, (a) being the local sketch map that connects of multitask function module, (b) is the local scheduling sketch map that connects of multitask function module.
Among Fig. 9 (a); N1 represents base node; FB1 and FB2 represent one group of starting point functional block and the terminal point functional block in the fundamental node N1 respectively; FB3 and FB4 represent another group starting point functional block and terminal point functional block in the fundamental node N1 respectively, and the multitask function module is local to connect being connected of the starting point functional block more than two groups or two groups that is meant in the fundamental node and terminal point functional block.
Among Fig. 9 (b), CD (N1) representative is sent to fundamental node N1 and is forced data CD, and the instruction of starting point functional block is carried out in FB1 (N1) and FB3 (N1) representative, and link order is carried out in LN1 (N1) and LN2 (N1) representative, and the instruction of terminal point functional block is carried out in FB2 (N1) and FB4 (N1) representative; Transverse axis is represented scheduling time, and the scale on the transverse axis is represented chronomere, and a chronomere can be 5 milliseconds, also can be 10 milliseconds, and this depends on bus scheduling equipment.In conjunction with Fig. 9 (b), step 5 of the present invention specifically realizes through following embodiment:
301: the bus scheduling node sends to N1 and forces data CD.
302: after fundamental node N1 receives and forces data CD, carry out current functional block instruction FB1; The same 1021-1025 of detailed process.
303: the bus scheduling node sends to N1 and forces data CD;
304: after fundamental node N1 receives and forces data CD, carry out current functional block instruction FB3; The same 1021-1025 of detailed process.
305: the bus scheduling node sends to N1 and forces data CD;
306: fundamental node N1 carries out current link order LN1 after receiving and forcing data CD; The same 1041-1042 of detailed process.
307: the bus scheduling node sends to N1 and forces data CD;
308: fundamental node N1 carries out current link order LN2 after receiving and forcing data CD; The same 1041-1042 of detailed process.
309: the bus scheduling node sends to N1 and forces data CD.
310: after fundamental node N1 receives and forces data CD, carry out current functional block instruction FB2; The same 1021-1025 of detailed process.
311: the bus scheduling node sends to N1 and forces data CD;
312: after fundamental node N1 receives and forces data CD, carry out current functional block instruction FB4; The same 1021-1025 of detailed process.
Embodiment four:
Figure 10 is long-range connection of multitask function module and scheduling sketch map; Wherein, (a) being the long-range connection sketch map of multitask function module, (b) is the long-range connection scheduling of multitask function module sketch map.
Among Figure 10 (a); N1, N2, N3 and N4 represent base node; FB1 and FB2 represent one group of starting point functional block and the terminal point functional block in the fundamental node N1, N2 respectively; FB3 and FB4 represent another group starting point functional block and the terminal point functional block in fundamental node N3, the N4 respectively, and the long-range connection of multitask function module is meant the starting point functional block of fundamental node and being connected of terminal point functional block more than two groups or two groups.
Among Figure 10 (b), CD (N1) representative is sent to fundamental node N1 and is forced data CD, and the instruction of starting point functional block is carried out in FB1 (N1) and FB3 (N3) representative, and link order is carried out in LN1 (N1) and LN2 (N3) representative, and the instruction of terminal point functional block is carried out in FB2 (N2) and FB4 (N4) representative; Transverse axis is represented scheduling time, and the scale on the transverse axis is represented chronomere, and a chronomere can be 5 milliseconds, also can be 10 milliseconds, and this depends on bus scheduling equipment.In conjunction with Figure 10 (b), step 5 of the present invention specifically realizes through following embodiment:
401: the scheduling node on the bus sends to fundamental node N1 and forces data CD.
402: the scheduling node on the bus sends to fundamental node N3 and forces data CD.
403: after fundamental node N1 receives and forces data CD, carry out functional block instruction FB1; The same 1021-1025 of detailed process.
404: after fundamental node N3 receives and forces data CD, carry out functional block instruction FB3; The same 1021-1025 of detailed process.
Here, CD (N3) and FB1 (N1) can walk abreast and dispatch and carry out, because CD (N3) is based on the data communication of bus; FB1 (N1) then is based on the inner instruction of node N1 and carries out, and is irrelevant with bus communication, the scheduling so the two can walk abreast; Thereby the raising dispatching efficiency, the cycle of shortening total activation.
405: the scheduling node on the bus sends to fundamental node N1 and forces data CD.
406: fundamental node N1 carries out long-range link order LN1, the same 2041-2046 of detailed process after receiving and forcing data CD.
407: the scheduling node on the bus sends to fundamental node N3 and forces data CD.
At this moment: CD (N3) and LN1 (N1) can walk abreast and dispatch and carry out, because CD (N3) is based on the data communication of bus, LN1 (N1) then is based on the inner instruction of node N1 and carries out, and is irrelevant with bus communication, the scheduling so the two can walk abreast.
408: fundamental node N3 carries out long-range link order LN2, the same 2041-2046 of detailed process after receiving and forcing data CD.
409: the scheduling node on the bus sends to fundamental node N2 and forces data CD.
410: the scheduling node on the bus sends to fundamental node N4 and forces data CD.
411: after fundamental node N2 receives and forces data CD, carry out functional block instruction FB2; The same 1021-1025 of detailed process.
At this moment: CD (N4) and FB2 (N2) can walk abreast and dispatch and carry out, because CD (N4) is based on the data communication of bus, FB2 (N2) then is based on the inner instruction of node N2 and carries out, and is irrelevant with bus communication, the scheduling so the two can walk abreast.
412: after fundamental node N4 receives and forces data CD, carry out functional block instruction FB4; The same 1021-1025 of detailed process.
The present invention proposes the data partition structure of field level intelligent node, defined the client layer data submodel in the WorldFIP communication protocol, provided the network scheduling algorithm of the distributed function piece application model that is applicable to WorldFIP Fieldbus Control network.The present invention has solved in the field level intelligent control network full distributed design of intellectual system and the problem of implementation based on functional block and functional block application process effectively; And then the real-time full distributed Based Intelligent Control of realization high reliability; This model is easy to realize to have strong control real-time, certainty and portable preferably.
The above; Be merely the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (5)
1. the dispatching method of a WorldFIP distributed intelligent control network is characterized in that said method comprises the following steps:
Step 1: before control system starts operation, on the link scheduling device, set up manufacturing variables corresponding to each fundamental node consumption variable;
Said fundamental node comprises functional block, and said functional block is divided into 4 districts, is respectively: instruction area, input terminal region, output terminal region, include parameter region; Wherein, said instruction area is used to store all instructions; Said input terminal region is used to store all fan-in certificates; Said output terminal region is used to store all fan-out certificates; The said parameter region that includes is used to store containing parameter in all;
Said input terminal region and output terminal region all use 4 bytes as data storage cell;
Containing parameter uses byte as data storage cell in said, and adjacent arrangement between a plurality of parameters is discerned each parameter with side-play amount and data length;
Step 2: will force data CD to be written in the said manufacturing variables;
Step 3: the schedule entries of variable exchange is added in the bus scheduling table;
Step 4: after network startup,, on network, produce the variable exchange of each fundamental node according to the sequential of dispatch list regulation;
Step 5: fundamental node is after receiving pressure data CD from the consumption variable, the present instruction of the current sensing of execution command district's pointer is pointed to next bar and instructed after being finished;
When said present instruction was the functional block instruction, said step 5 comprised the following steps:
Step 51: fundamental node according to the starting point index value in this functional block input terminal region, takes out all fan-in certificates by this functional block fan-in in the functional block instruction from input terminal region;
Step 52: fundamental node includes the starting point byte offsets in the parameter region by the interior containing parameter of this functional block in the functional block instruction in this functional block, from including the interior containing parameter that parameter region takes out;
Step 53: fundamental node uses the fan-in certificate and includes calculation of parameter to obtain the fan-out certificate by the functional block algorithm;
Step 54: fundamental node, is written to the fan-out certificate in the functional block output terminal region according to the starting point index value in this functional block output terminal region by functional block fan-out;
Step 55: the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district;
When said present instruction was local link order, said step 5 comprised the following steps:
Step 51 ': in link order,, obtain the fan-out certificate of starting point functional block output terminal region according to the starting point index value of starting point functional block in this functional block output terminal region;
Step 52 ': according to the starting point index value of terminal point functional block in this functional block input terminal region, with the fan-out of starting point functional block output terminal region according to copying in the terminal point functional block input terminal region;
Step 53 ': the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district;
When said present instruction was long-range link order, said step 5 comprised the following steps:
Step 51 ": in link order,, obtain the fan-out certificate of starting point functional block output terminal region according to the starting point index value of starting point functional block in its fundamental node output terminal region;
Step 52 ": the fan-out certificate of starting point functional block output terminal region is written in the message, and is packaged into message frame; The form of message comprises three fields in the said message frame, is respectively: purpose identification code, input index and float type data; Wherein, the purpose identification code takies 1 byte, and the input index takies 2 bytes, 4 bytes of float type data occupancy; The input index field is used to store the input index of the terminal point functional block of long-range connection at its base node; Float type data are used to store the fan-out certificate of starting point functional block at the output terminal region of its fundamental node;
Step 53 ": the instruction pointer of functional block instruction area is moved backward next bar instruction in direction-pointing function block instruction district;
Step 54 ": the network scheduling node sends message inquiry frame to the fundamental node of starting point functional block;
Step 55 ": the fundamental node of starting point functional block sends to message frame on the network;
Step 56 ": after the fundamental node of terminal point functional block is received message frame, message frame is unpacked, read the message in the message frame, by the terminal point functional block input terminal region index that indicates in the message, float type data are written in the terminal point functional block input terminal region then.
2. the dispatching method of a kind of WorldFIP distributed intelligent control network according to claim 1; It is characterized in that said instruction comprises the functional block instruction; Comprising 5 fields in its structure, is respectively that instruction sign, functional block type, functional block fan-in certificate starting point index value, the functional block fan-out in this functional block input terminal region includes the starting point byte offsets in the parameter region according to the starting point index value in this functional block output terminal region and the interior containing parameter of functional block in this functional block.
3. the dispatching method of a kind of WorldFIP distributed intelligent control network according to claim 1; It is characterized in that said instruction comprises link order; Comprising 4 fields in its structure, is respectively the address and the starting point index value of terminal point functional block in this functional block input terminal region of the fundamental node at starting point index value in this functional block output terminal region of link order sign, starting point functional block, terminal point functional block place.
4. according to the dispatching method of claim 2 or 3 described a kind of WorldFIP distributed intelligent control networks, it is characterized in that said functional block instruction and link order are the mixed in equal amounts storages in the instruction area.
5. the dispatching method of a kind of WorldFIP distributed intelligent control network according to claim 1, what it is characterized in that said message frame employing is the mode of destination address addressing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910089946A CN101616047B (en) | 2009-07-28 | 2009-07-28 | Dispatching method of WorldFIP distributed intelligent control network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910089946A CN101616047B (en) | 2009-07-28 | 2009-07-28 | Dispatching method of WorldFIP distributed intelligent control network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101616047A CN101616047A (en) | 2009-12-30 |
| CN101616047B true CN101616047B (en) | 2012-08-29 |
Family
ID=41495472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910089946A Expired - Fee Related CN101616047B (en) | 2009-07-28 | 2009-07-28 | Dispatching method of WorldFIP distributed intelligent control network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101616047B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106909343B (en) * | 2017-02-23 | 2019-01-29 | 北京中科睿芯科技有限公司 | A kind of instruction dispatching method and device based on data flow |
| CN110209482B (en) * | 2019-05-28 | 2021-09-14 | 北京国电智深控制技术有限公司 | Scheduling method and device of periodic message and computer readable storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477362A (en) * | 2007-12-31 | 2009-07-08 | 费舍-柔斯芒特系统股份有限公司 | Automatic configuration of synchronous block execution for control modules in fieldbus networks |
-
2009
- 2009-07-28 CN CN200910089946A patent/CN101616047B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477362A (en) * | 2007-12-31 | 2009-07-08 | 费舍-柔斯芒特系统股份有限公司 | Automatic configuration of synchronous block execution for control modules in fieldbus networks |
Non-Patent Citations (2)
| Title |
|---|
| 梁庚.基于IEC61131-3标准的分布式智能系统策略组态软件包开发研究.《中国博士学位论文全文数据库》.2005, * |
| 翟伟翔.WorldFIP现场总线分布式控制系统的研究与开发.《中国博士学位论文全文数据库》.2008, * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101616047A (en) | 2009-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105657639B (en) | Dual-mode equipment and its method realized while communicated | |
| CN102833141B (en) | CAN (control area network) open slave station system based on DSP (digital signal processor) 28335 | |
| CN101976074B (en) | Industrial control system based on field bus and control network | |
| CN107707447B (en) | Slave station system based on EtherCAT and control method | |
| CN104734980B (en) | Industrial field bus MPR and multi protocol conversion method | |
| CN102253657B (en) | Implementation method for networked system structure of numerical control system | |
| CN100524122C (en) | Bus controller for numerical control system of full digital ring bus | |
| CN105592119B (en) | Communication method and device of network equipment | |
| CN113093658A (en) | Multi-axis servo system architecture design method based on EtherCAT | |
| CN103117933A (en) | Method and system for transmitting data in multipoint communication network | |
| CN100504688C (en) | Private chip for implementing bus controller function in ring bus numerical control system | |
| CN201479158U (en) | Multi-interface gateway | |
| CN101631394A (en) | Multi-interface coordinator of wireless sensor network | |
| CN106982222A (en) | The multi-protocol data cut-in method and device that can configure under a kind of industrial 4.0 environment | |
| CN101616047B (en) | Dispatching method of WorldFIP distributed intelligent control network | |
| CN104243172A (en) | Expanded input/output device of decentralized control system, and method thereof | |
| CN102263709A (en) | Gateway for realizing communication transformation between EtherCAT (Ethernet for control and automation technology) and RS485 and communication method thereof | |
| CN200947617Y (en) | Zigbee short distance wireless gateway | |
| CN101855615A (en) | Use the FLEXRAY system of powerful instruction storage | |
| CN103997450A (en) | Implementation method of CANopen master station based on DSP 28335 | |
| CN109327818B (en) | Scheduling algorithm of wireless networked control system based on IEEE 802.15.4 protocol | |
| CN200997072Y (en) | Bus controller for digital ring bus digital-controlled system | |
| CN202353595U (en) | Gateway for EtherCAT (Ethernet for control and automation technology) and RS485 communication switching | |
| CN101533554B (en) | A sending method for wireless instructions, receiving nodes and a system | |
| Hao et al. | Development for protocol conversion gateway of industrial field bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120829 Termination date: 20140728 |
|
| EXPY | Termination of patent right or utility model |