CN101609349B - Clock generator - Google Patents

Abstract

The invention relates to a clock generator comprising a current generator, an oscillator and a voltage regulator, wherein the current generator is used for generate a first current and a second current according to a control voltage; the oscillator is coupled with the current generator and used for generating a clock signal according to the first current; the voltage regulator is coupled with the current generator and the oscillator and used for regulating the control voltage according to the clock signal and the second current, wherein when the signal frequency of the clock signal is changed, the voltage regulator relatively regulates the control voltage to change the first current.

Description

Clock generator

Technical field

The present invention relates to a kind of clock generator, refer to a kind of clock generator that is not subjected to processing procedure, operating voltage and temperature effect in fact especially.

Background technology

In integrated circuit, clock signal is an indispensable reference signal, can be used as the reference signal of sampling input data or as the reference sequential of computing circuit etc.

In general, Generation of Clock Signal in the integrated circuit, produce a reference clock signal by the quartz (controlled) oscillator that is arranged at the integrated circuit outside, again by the phase-locked loop in the integrated circuit according to this reference clock signal, use for inner electronic circuit with the clock signal of exporting a higher-frequency.Yet, by the method for quartz (controlled) oscillator clocking, though can produce one more accurately clock signal use for integrated circuit, this kind method still needs pin by integrated circuit to receive reference clock signal, thus, higher pin cost will be spent.

Summary of the invention

Therefore, one of purpose of the present invention is to provide a kind of clock generator, and the clock signal that can save pin and generation is not subjected to processing procedure, operating voltage in fact, influences with temperature etc.

Therefore, one of purpose of the present invention is to provide a kind of clock generator, is applied in the network service integrated circuit.

One of embodiments of the invention disclose a kind of clock generator, and this clock generator includes a current generator, an oscillator and a voltage adjuster.Current generator is used for according to control voltage to produce first electric current and second electric current.Oscillator is coupled to current generator, is used for according to first electric current with clocking.Voltage adjuster is coupled to current generator and oscillator, is used for according to this clock signal and this second electric current to adjust this control voltage.Wherein, when the signal frequency of clock signal changed, voltage adjuster was adjusted control voltage accordingly according to the change of this frequency, to change first electric current.

Wherein this current generator comprises: an operational amplifier, have a reverse input end, a non-inverting input and an output terminal, and this non-inverting input receives this control voltage; One resistance is coupled to this reverse input end; One transistor is coupled to this amplifier and this resistance, is used for voltage according to this output terminal to export a Control current; And a current mirroring circuit, be coupled to this transistor, be used for according to this Control current to produce this first electric current and one second electric current.

Wherein this voltage adjuster comprises: one first electric capacity, be coupled to this current generator, and be used to receive this second electric current to export this control voltage; One the first transistor, its grid is coupled to this oscillator, and its drain electrode is coupled to this first electric capacity, is used for according to this first clock signal to adjust this control voltage on this first electric capacity; One second electric capacity is coupled to the source electrode of this first transistor, is used for by this first transistor to share one first quantity of electric charge that this first electric capacity is stored; And a transistor seconds, its grid is coupled to this oscillator, and its drain electrode is coupled to this second electric capacity, is used for one second quantity of electric charge of being stored with this second electric capacity that discharges according to a second clock signal; Wherein, this first clock signal and this second arteries and veins signal reverse signal each other.

Description of drawings

Fig. 1 is the synoptic diagram of an embodiment of clock generator of the present invention.

Fig. 2 is the synoptic diagram of an embodiment of clock generator of the present invention.

Fig. 3 is the synoptic diagram of an embodiment of correcting circuit of the present invention.

[main element symbol description]

100: clock generator

101: current generator

102: oscillator

103: voltage adjuster

104: correcting circuit

302,304: comparer

306: logic control circuit

OP: amplifier

Mr, M1, M2, Q1, Q2, Q3: transistor

R1, Rx1, Rx2, Rx3, Rd: resistance

C1, C2: electric capacity

I3, I4: current source

Embodiment

At first, please consult Fig. 1 earlier, Fig. 1 illustrates the synoptic diagram of first embodiment of clock generator of the present invention, and as shown in the figure, clock generator 100 includes a current generator 101, an oscillator 102 and a voltage adjuster 103.Clock generator 100 is applied in the network service integrated circuit, for example according to an embodiment: 10M/100M/1000M Ethernet, and in the integrated circuit such as 802.11a/b/g/n.Current generator 101 is according to controlling voltage Vc to produce first electric current I 1 and second electric current I 2.Oscillator 102 is to be coupled to current generator 101, and according to first electric current I 1, with clocking clk and reverse clock signal

Voltage adjuster 103 then is coupled to current generator 101 and oscillator 102.Wherein, 103 of voltage adjusters are according to clock signal clk, reverse clock signal

The clock frequency and second electric current I 2 adjust control voltage Vc.Palpus attention person, the relation that couples of each element for the sake of clarity, is not given unnecessary details at this as shown in FIG. in addition.

Below will describe the principle of operation of clock generator of the present invention in detail.See also Fig. 1, the output terminal of operational amplifier OP is coupled to the grid of nmos pass transistor Q1, non-inverting input receives the control voltage Vc that is exported by voltage adjuster 103, the output one output voltage V o of reverse input end system, and be coupled to resistance R 1, make output voltage V o produce Control current Ic when resistance R 1, wherein, output voltage V o size in fact is equal to control voltage Vc.

As known in the figure, Control current Ic flow to current mirroring circuit 101a, and wherein, transistor M1 system produces first electric current I 1, and transistor M2 system produces second electric current I 2.When the breadth length ratio (aspect ratio) of transistor M1 is designed to b times of transistor Mr, then first electric current I 1 is equal to b Control current Ic doubly in fact, in like manner, when the breadth length ratio (aspect ratio) of transistor M2 was designed to a times of transistor Mr, then second electric current I 2 was equal to a Control current Ic doubly in fact.As shown in Figure 1, the source terminal of transistor M1 is coupled to oscillator 102, and first electric current I 1 that oscillator 102 can be exported according to transistor M1 is to produce the first clock signal clk and second clock signal clk.According to an embodiment, the first clock signal clk and this second clock signal clk are essentially reverse signal.

Please consult again to voltage adjuster 103.According to one embodiment of the invention, voltage adjuster 103 comprises transistor Q2, transistor Q3, capacitor C 1 and capacitor C 2.It couples relation as shown in the figure, and the grid of transistor Q2 is coupled to oscillator 102, and drain electrode is coupled to first capacitor C 1, wherein transistor Q2 decide transistor Q2 according to the first clock signal clk conducting whether; And the grid of transistor Q3 is coupled to oscillator 102, and drain electrode is coupled to the source terminal and second capacitor C 2 of transistor Q2, wherein transistor Q3 decide transistor Q3 according to second clock signal clk conducting whether.

When first phase place, promptly the first clock signal clk is a logical zero, and when second clock signal clk was logical one, transistor Q2 was a closed condition, and transistor Q3 is a conducting state.At this moment, the charged state of 2 pairs of capacitor C 1 of second electric current I is as follows:

$\mathrm{aI}=C_1\frac{\mathrm{dv}}{\mathrm{dt}}\⇒{\∫}_0^{V1}\mathrm{dv}=\frac{\mathrm{aI}}{C_1}{\∫}_0^{\frac{1}{2f}}\mathrm{dt}\⇒V_1=\frac{\mathrm{aI}}{C_1}\frac{1}{2f}$

Wherein, aI is the magnitude of current of second electric current I 2, and V1 is the voltage that is increased on the capacitor C 1, and f is the signal frequency of first and second clock signal.

When second phase place, promptly the first clock signal clk is output as and is logical one, and when second clock signal clk was logical zero, transistor seconds Q2 was a conducting state, and the 3rd transistor Q3 is a closed condition.Because transistor seconds Q2 is switched on, electrostatic capacitor C1 and capacitor C 2 will take place to share effect, and relevant derivation formula is as follows:

$V_1{C}_1=V_x(C_1+C_2)\⇒V_X=\frac{C_1}{C_1+C_2}{V}_1$

Wherein, Vx is subjected to electric charge to share the voltage that is reduced under the effects on the capacitor C 1.Therefore, when second phase place, the charged state of 2 pairs of capacitor C 1 of second electric current I can be expressed as:

$\mathrm{aI}=(C_1+C_2)\frac{\mathrm{dv}}{\mathrm{dt}}\⇒{\∫}_{v_x}^{v_2}\mathrm{dv}=\frac{\mathrm{aI}}{C_1+C_2}{\∫}_{\frac{1}{2f}}^{\frac{1}{f}}\mathrm{dt}\⇒V_2-V_x=\frac{\mathrm{aI}}{C_1+C_2}\frac{1}{2f}$

$V_2=V_x+\frac{\mathrm{aI}}{C_1+C_2}\frac{1}{2f}=\frac{C_1}{C_1+C_2}{V}_1+\frac{\mathrm{aI}}{C_1+C_2}\frac{1}{2f}$

Wherein, V2 is when second phase place, the voltage that is increased on the capacitor C 1.Because phase place 1 can constantly repeat with phase place 2, can suppose:

$\mathrm{\β}=\frac{C_1}{C_1+C_2}$ With $V_C=\frac{\mathrm{aI}}{C_1+C_2}\frac{1}{2f}$

Therefore, the control voltage Vc of voltage adjuster 103 outputs can push away as followsly:

$V_{2n}=(\mathrm{\β}{V}_1+V_C)({\mathrm{\β}}^{n-1}+{\mathrm{\β}}^{n-2}+\·\·\·+1)\⇒V_C=\frac{\mathrm{aI}}{{\mathrm{fC}}_2}---\left(1\right)$

Again, the relation between Control current I and the control voltage Vc is shown as follows:

$I=\frac{V_C}{R_1}---\left(2\right)$

In conjunction with formula (1) and formula (2), can push away the signal frequency f that wins with the second clock signal and be:

$f=\frac{a}{R_1{C}_2}$

By above-mentioned derivation result clearly as can be known, the signal frequency f of first and second clock signal of being produced of oscillator 102 is relevant with the breadth length ratio a of resistance R 1, capacitor C 2, transistor M2; Irrelevant in fact with operating voltage VDD.

For instance, when supposing that operating voltage VDD drifts about downwards, first electric current I 1 and second electric current I 2 will reduce (because Vgs reduces), and at this moment, first clock signal clk that oscillator 102 is exported and the signal frequency of second clock signal clk also descend thereupon.Because the cause that the first clock signal clk and second clock signal clk signal frequency descend makes voltage adjuster 103 will adjust upward control voltage Vc, to compensate first electric current I 1.Thus, first clock signal clk that oscillator 102 is exported and the signal frequency of second clock signal clk will be adjusted, to keep the stability of clock signal.

Then, please consult Fig. 2 again, Fig. 2 shows the synoptic diagram of second embodiment of clock generator of the present invention, and different second embodiment that are with first embodiment have increased by a correcting circuit 104.Owing to need consider the factor of processing procedure and temperature drift in the integrated circuit, the more newly-increased correcting circuit 104 of the second embodiment of the present invention is with school capacitor C 1, capacitor C 2 and resistance R 1, and it couples relation as shown in the figure.When processing procedure or temperature drift generation, by correcting circuit 104 corrective capacity C1, capacitor C 2 or resistance R 1, make that R1 * C2 is a certain value, thus, the clock signal that can make oscillator 102 be exported is more stable.The specific embodiment of correcting circuit 104 can be consulted Fig. 3, comprise current source I3, current source I4, resistance R x1, resistance R x2, resistance R x3, resistance R d, comparer 302, comparer 304 and logic control circuit 306, wherein resistance R d is used for the variable quantity of inspection process or temperature drift.With the embodiment of Fig. 3, current source I3 produces electric current to resistance R x1, resistance R x2, resistance R x3, and produces not reference voltage V1 and reference voltage V2 with processing procedure or temperature drift; Current source I4 produces electric current to resistance R d, and produces the detection voltage Vd along with processing procedure or temperature drift.Then, relatively detect voltage Vd and reference voltage V1, reference voltage V2 compare by comparer 302 and comparer 304, and export a comparative result to logic control circuit 306.This comparative result has reflected the variable quantity of inspection process or temperature drift, and is last, and logic control circuit 306 produces correction signal to resistance R 1 accordingly according to above-mentioned comparative result again and proofreaies and correct to carry out resistance.In addition, the principle of operation of correcting circuit 104 also can be used to corrective capacity C1 and capacitor C 2, does not repeat in addition to give unnecessary details at this.

In sum, clock generator of the present invention is by the mechanism of current generator 101, oscillator 102 and voltage adjuster 103 three's FEEDBACK CONTROL, can make the clock signal of oscillator 102 outputs not be subjected to processing procedure, operating voltage and temperature effect, and clock generator does not need more can save the pin of integrated circuit with reference to outside clock signal.

The above only is the preferred embodiments of the present invention, and all equalizations of making according to claims of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims (7)

1. clock generator comprises:

One current generator is used for according to a control voltage to produce one first electric current and one second electric current;

One oscillator is coupled to this current generator, is used for according to this first electric current to produce a clock signal; And

One voltage adjuster is coupled to this current generator and this oscillator, is used for according to this clock signal and this second electric current to adjust this control voltage;

Wherein, when the change of the signal frequency of this clock signal, this voltage adjuster is adjusted this control voltage accordingly according to this frequency variation, changing this first electric current,

Wherein this current generator comprises:

One operational amplifier has a reverse input end, a non-inverting input and an output terminal, and this non-inverting input receives this control voltage;

One resistance is coupled to this reverse input end;

One transistor is coupled to this amplifier and this resistance, is used for voltage according to this output terminal to export a Control current; And

One current mirroring circuit is coupled to this transistor, is used for according to this Control current producing this first electric current and one second electric current,

Wherein this voltage adjuster comprises:

One first electric capacity is coupled to this current generator, is used to receive this second electric current to export this control voltage;

One the first transistor, its grid is coupled to this oscillator, and its drain electrode is coupled to this first electric capacity, is used for according to this first clock signal to adjust this control voltage on this first electric capacity;

One second electric capacity is coupled to the source electrode of this first transistor, is used for by this first transistor to share one first quantity of electric charge that this first electric capacity is stored; And

One transistor seconds, its grid is coupled to this oscillator, and its drain electrode is coupled to this second electric capacity, is used for one second quantity of electric charge of being stored with this second electric capacity that discharges according to a second clock signal;

Wherein, this first clock signal and this second arteries and veins signal reverse signal each other.

2. clock generator as claimed in claim 1 also comprises:

One correcting circuit is coupled to this resistance, this first electric capacity and this second electric capacity, is used to proofread and correct the resistance value of this resistance and the capacitance of this first electric capacity and this second electric capacity.

3. clock generator as claimed in claim 1, wherein this voltage adjuster by the electric charge sharing mode to adjust this control voltage.

4. clock generator as claimed in claim 1, wherein when this first transistor was switched on, this transistor seconds system was closed; And when this first transistor was closed, this transistor seconds was switched on.

5. clock generator as claimed in claim 1, wherein the signal frequency of this clock signal is corresponding with the capacitance of this second electric capacity.

6. clock generator as claimed in claim 1, wherein this first with this transistor seconds be nmos pass transistor.

7. clock generator as claimed in claim 1 is applicable in the network communication device.

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