CN101599808B - Method and system for testing cross board - Google Patents
Method and system for testing cross board Download PDFInfo
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- CN101599808B CN101599808B CN 200810085927 CN200810085927A CN101599808B CN 101599808 B CN101599808 B CN 101599808B CN 200810085927 CN200810085927 CN 200810085927 CN 200810085927 A CN200810085927 A CN 200810085927A CN 101599808 B CN101599808 B CN 101599808B
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Abstract
The embodiment of the invention provides a method and a system for testing a cross board and a high level cross chip. A test device sends service data to an input port of a primary input/output port of the cross board; the cross board loops back the received service data among a plurality of secondary input/output ports and finally sends the received service data to the primary output port, and the cross board enables a frame head of the service data sent from the input port to the output port to be level to a system frame head in the loopback process; the test device receives test data from the primary input port and compares whether the received test data is consistent with the sent test data or not, if the received test data is consistent with the sent test data, the cross board is judged to be normal, and otherwise, the cross board is judged to be unnormal. The test cost can be lowered because no service board needs to be arranged fully.
Description
Technical field
The present invention relates to the single-board testing technology, particularly a kind of cross board method of testing, system and high-order cross chips.
Background technology
The cross board of transmission product; SDH (Synchronous Digital Hierarchy) (SDH for example; Synchronous DigitalHierarchy), Synchronous Optical Network (SONET; Synchronous Optical Network Synchronou) etc. cross board; be mainly used to realize the scheduling of high and low rank business, professional protection such as switches at the function.In typical cross board, the high-order cross matrix is used for the high-order cross processing of business datum, and the input/output port of cross board is provided.Generally on the high price cross matrix, can also connect the low order interlace algorithm matrix, be used for that business datum is carried out low order interlace algorithm and process.Cross processing described here refers to that the business datum that cross board receives each input port is dispatched to respectively corresponding output port output, and then realizes the scheduling of business datum.The granularity of high-order cross processing dispatching services data is large, very flexible namely, and the granularity that low order interlace algorithm is processed the dispatching services data is little, and namely flexibility is high.Wherein, the high-order cross matrix is comprised of the high-order cross chips, and the low order interlace algorithm matrix is comprised of the low order interlace algorithm chip.
The structure of high-order cross chips comprises input processing unit, output processing unit and cross processing unit as shown in Figure 1.Input processing unit is sent to the cross processing unit with the data that receive, and is crossed to corresponding output processing unit through the cross processing unit.Wherein input processing unit comprises input port, and namely input processing unit provides the input port of cross board, and described input port is used for receiving the business datum that is sent to cross board; The output processing unit comprises output port, namely exports the output port that processing unit provides cross board, and described output port is used for the business datum after the output cross plate is processed.
Along with the extensive use of transmission product, the important means during the single-board testing technology has become a kind of veneer exploitation and used.Whether at present, it is normal to test cross board, need to be at the full configuration service plate of cross board.Described full configuration is put and referred to: the every a pair of input/output port of business board all links to each other with corresponding business board.In the cross board test, cross board returns by each business board the business datum that receives behind every a pair of input/output port loopback, whether the business datum that is sent to more at first cross board is consistent with the business datum that cross board finally returns, thereby judges whether cross board is normal.
Traditional cross board test macro is as shown in Figure 2: comprise SDH/SONET tester, cross board and business board 1, and business board 2 ..., business board n.Wherein, n is the integer more than or equal to 1, and each business board all links to each other with a pair of input/output port of cross board.
The cross board test macro of the below in Fig. 2 illustrates existing cross board method of testing as example:
A, SDH/SONET tester send business datum to business board 1.
B, cross board return by each business board the business datum that receives behind every a pair of input/output port loopback.
This step is specially: be sent to the input port 1 of cross board from the business datum of SDH/SONET tester through business board 1, be sent to cross board by input port 1; Be crossed to corresponding output port 2 through cross board, export business board 2 to through output port 2, through the business board loopback to input port 2, wherein, after being sent to business board from the business datum of output port 2, can also can return business board by external fiber through behind the business board in the business board internal loopback to input port 2, be sent to input port 2 through business board again; Input port 2 is crossed to corresponding output port 3 with the data that receive through cross board, by that analogy, until business datum is back to the SDH/SONET tester through behind all cross boards through output port 1.Like this, business datum has realized the loopback at every a pair of input/output port of cross board.
Whether the business datum that c, the analysis of SDH/SONET tester are sent to business board 1 is consistent with the business datum that business board 1 returns, and if so, judges that then cross board is normal, otherwise, judge that cross board is undesired.
In existing cross board method of testing, business datum need to be implemented in through each business board the every a pair of input/output port loopback of cross board, namely need to be at the full configuration service plate of cross board.Suppose the transmission product that has to support the 720G crossing, each professional groove position, namely every a pair of input/output port is supported the 20G Business Processing, the business board that just needs to reach 36 20G is finished test.To large batch of production test, can cause testing cost high.
Summary of the invention
The embodiment of the invention provides a kind of cross board method of testing, can reduce the cost of cross board test.
The embodiment of the invention provides a kind of cross board test macro, can reduce the cost of cross board test.
The embodiment of the invention provides a kind of high-order cross chips, can reduce the cost of cross board test.
Below the technical scheme that provides for the embodiment of the invention:
A kind of cross board method of testing is used for cross board is tested, and described cross board is provided with a pair of elementary input/output port, and a plurality of secondary input/output ports, and described cross board method of testing comprises the steps:
The elementary input/output port of described cross board is linked to each other with testing apparatus, and the input port of each secondary input/output port of cross board is connected with output port;
By the input port transmission business datum of described testing apparatus to the elementary input/output port of described cross board;
Described cross board also finally sends to the business datum loopback between described a plurality of secondary input/output ports that receives the output port of described elementary input/output port, and in the process of loopback, described cross board will be sent to from input port frame head and system's frame head alignment of the business datum of output port;
Described testing apparatus receives test data from the output port of described elementary input/output port, and relatively whether its received test data is consistent with its test data that sends, if so, judge that then described cross board is normal, otherwise judge that described cross board is undesired.
A kind of cross board test macro, this system comprises: testing apparatus and cross board;
Described testing apparatus is used for sending business datum to cross board, receive the business datum that cross board returns, whether the business datum that relatively is sent to cross board is consistent with the business datum that described cross board returns, if, judge that then described cross board is normal, otherwise judge that described cross board is undesired;
Described cross board comprises many to input/output port and data processing module, wherein a pair of input/output port is elementary input/output port, described elementary input/output port links to each other with the data input and data output port of testing apparatus, other are to being secondary input/output port, and input port and the output port of described a plurality of secondary input/output ports then interconnect; Cross board receives the business datum from testing apparatus, the business datum that receives is back to testing apparatus behind every a pair of input/output port loopback, in loopback each time, cross board is sent to data processing module with business datum through input port first, by data processing module with the frame head of business datum with export by output port again after the system frame head aligns.
A kind of high-order cross chips, this equipment comprises: input processing unit, output processing unit, cross processing unit and reset frame unit;
Described input processing unit be used for to receive business datum, and the business datum that receives is carried out input processing, and the input port of the business datum after the input processing by described input processing unit is sent to the cross processing unit.
Described cross processing unit is used for receiving the business datum from input processing unit, and the business datum that receives is crossed to the corresponding frame unit that resets;
The described frame unit that resets be used for to receive business datum from the cross processing unit, and the frame head of the business datum that receives is alignd with the system frame head, the business datum after the alignment is sent to the output processing unit of correspondence;
Described output processing unit is used for receiving from the business datum that resets frame unit, and the business datum that receives is exported processing, with the output port output of the business datum after processing by described output processing unit.
From technique scheme, can find out, the cross board method of testing that the embodiment of the invention provides, system and high-order cross chips, business datum directly at the every a pair of input/output port loopback of cross board, do not need full configuration service plate, therefore, can reduce the cost of cross board test.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do one to the accompanying drawing of required use in embodiment or the description of the Prior Art and introduce simply, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structure chart of high-order cross chips in the prior art;
Fig. 2 is the structure chart of existing cross board test macro;
The structure chart of the cross board test macro that Fig. 3 provides for the embodiment of the invention;
Fig. 4 is the schematic diagram of the data processing module in the embodiment of the invention;
Fig. 5 is the structural representation of the first execution mode that resets frame unit of the data processing module of the embodiment of the invention;
Fig. 6 is the schematic diagram of the second execution mode that resets frame unit of the data processing module of the embodiment of the invention;
Fig. 7 is the schematic diagram of the third execution mode that resets frame unit of the data processing module of the embodiment of the invention;
Fig. 8 is the schematic diagram of the 4th kind of execution mode that resets frame unit of the data processing module of the embodiment of the invention;
Fig. 9 is the cross board method of testing flow chart of the cross board test macro of the application embodiment of the invention;
The further flow chart of the cross board method of testing that Figure 10 provides for the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention express clearlyer, the present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
The structure chart of the cross board test macro that Fig. 3 provides for the embodiment of the invention.As shown in Figure 3:
The cross board test macro that the embodiment of the invention provides comprises: testing apparatus 501 and cross board 502.
Described testing apparatus 501 is used for sending business datum to cross board 502, receive the business datum that cross board 502 returns, whether the business datum that relatively is sent to cross board is consistent with the business datum that described cross board returns, if, judge that then described cross board is normal, otherwise judge that described cross board is undesired.In embodiments of the present invention, the above testing apparatus can be the SDH/SONET tester.
Described elementary input/output port 5021 links to each other with the data input and data output port of described testing apparatus 501, is used for sending the test business datums from described testing apparatus 501 receptions with to described testing apparatus 501.Input port 5022a and the output port 5022b of the defeated port 5022 of described a plurality of secondary input then interconnect.
Also be provided with data processing module 5023 on the cross board 502, be used for business datum is processed so that the frame head of business datum aligns with the system frame head, and realize the intersection transmission of business datum between described a plurality of data FPDP.
In actual applications, testing apparatus 501 sends the test business datum to the input port 5021a of described elementary input/output port 5021, and described test is sent to described data processing module 5023 after with the input port 5021a of business datum by described elementary input/output port 5021; After 5023 pairs of described tests of described data processing module are processed with business datum, with one the output port 5022b of described business datum in described a plurality of secondary input/output ports 5022; Described test then is sent to corresponding input port 5022a and again is sent to data processing module 5023 through described input port 5022a after by described output port 5022b with business datum and processes, so circulation repeatedly, until described test with business datum through behind all secondary input/output ports 5022, described data processing module 5023 can be sent to the output port 5021b of described elementary input/output port 5021 with business datum with described test, and described test is sent to testing apparatus 501 with business datum through behind the output port 5021b of described elementary input/output port 5021.Relatively whether its business datums that are sent to cross board 502 are consistent with the business datum that described cross board returns for described testing apparatus 501, if unanimously then judge that cross board 502 is normal, otherwise judge that cross board 502 is undesired.
In the present embodiment, can adopt bus or simple jockey to substitute traditional business board with the every a pair of input/output port connection of cross board, so that the business datum signal can be transmitted by loopback between every a pair of input/output port.
It will be appreciated that, when cross board 502 is provided with the low order interlace algorithm matrix, need to produce the multichannel pseudo-random code stream owing to be directed to the test of low order interlace algorithm matrix, and each road pseudo-random code stream is carried out determination and analysis, therefore can between testing apparatus 501 and cross board 502, add a business board 503, testing apparatus 501 can send to business datum first business board 503 when sending test with business datum, and then will send to cross board 502 with business datum through the test that business board 503 was processed, thereby reduce the design cost of testing apparatus 501.Certainly, easily full of beard and be also the disposal ability of above-mentioned business board 503 for business datum can be integrated on the described testing apparatus 501.
Please together with reference to Fig. 4, Figure 4 shows that the schematic diagram of embodiment of the invention data processing module 5023.
Described data processing module 5023 comprises: input processing unit 01, cross processing unit 02, reset frame unit 03 and output processing unit 04.
Reset frame unit 03 and be used for receiving business datum from cross processing unit 02, the frame head of the business datum that receives is alignd with the system frame head, the business datum after the alignment is sent to the output processing unit 04 of correspondence.
By resetting frame unit 03 business datum of chip internal is alignd with the system frame head, business datum and then can be at the every a pair of input/output port loopback of cross board 502 need to just can not realize test to cross board 502 at cross board 502 full configuration service plates.
From technique scheme, can find out, the cross board test macro that the embodiment of the invention provides, business datum directly at the every a pair of input/output port loopback of cross board, does not need full configuration service plate, therefore, can reduce the cost of cross board test.
Please refer to Fig. 5, Figure 5 shows that the structural representation of the first execution mode that resets frame unit 03 of the data processing module 5023 of the embodiment of the invention.The described frame unit 03 that resets comprises: control unit 501 and dual port RAM 502.
Described dual port RAM is used for the buffer memory business datum.
Please refer to Fig. 6, is the schematic diagram of the second execution mode that resets frame unit 03 of the data processing module 5023 of the embodiment of the invention such as Fig. 6.In the present embodiment, the described frame unit 03 that resets comprises: pointer interpreter unit 601, the first frame regeneration unit 602 and memory cell 603.
The first frame regeneration unit 602 is used for the receiving system frame head, when receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes, reading payload according to agreement from memory cell 603 is added in the described new traffic frame, from described new traffic frame, calculate pointer value according to the payload that adds, the pointer value of described pointer value as described new traffic frame is added in the described new traffic frame, the business datum of described new traffic frame after as alignment sent.
Please refer to Fig. 7, Figure 7 shows that the schematic diagram of the third execution mode that resets frame unit 03 of the data processing module 5023 of the embodiment of the invention.In the present embodiment, the described frame unit 03 that resets comprises: extraction unit 701, pointer computing unit 702, the second frame regeneration unit 703 and memory cell 704.
The second frame regeneration unit 703 is used for the receiving system frame head and from the new pointer value of pointer computing unit, when receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes, from memory cell 704, read the payload that writes, the payload that reads is added in the described new traffic frame, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, the business datum of described new traffic frame after as alignment is sent to corresponding output processing unit 04.
Please refer to Fig. 8, Figure 8 shows that the schematic diagram of the 4th kind of execution mode that resets frame unit 03 of the data processing module 5023 of the embodiment of the invention.In the present embodiment, the described frame unit 03 that resets comprises: pointer positioning unit 801, the 3rd frame regeneration unit 802 and memory cell 803.
Pointer positioning unit 801 is used for receiving the business datum from cross processing unit 02, determine the position of j1 byte in payload position in the described traffic frame and the payload according to the pointer value of traffic frame in the described business datum, for making the J1 sign in the position of described j1 byte, with described payload and J1 sign write storage unit 803.
The 3rd frame regeneration unit 802 is used for the receiving system frame head, when receiving described system frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes, from memory cell 803, read the payload and the J1 home position that write, the payload that reads is added in the described new traffic frame, J1 home position and system frame head position are subtracted each other, obtain new pointer value, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, the business datum of described new traffic frame after as alignment is sent to corresponding output processing unit 04.
Memory cell 803 is used for the buffer memory business datum.
Resetting in the execution mode of frame unit above-mentioned second, third, the 4th kind, memory cell 603, memory cell 704 and memory cell 803 can be synchronization fifo.
Wherein, in the situation that the pointer value that sends business datum to described cross board remains unchanged, can adopt above-mentioned third and fourth kind of execution mode.
The data processing module that the embodiment of the invention provides, the business datum of chip internal can be alignd with the system frame head, and then so that business datum can directly at the every a pair of input/output port loopback of cross board, not need full configuration service plate, therefore, can reduce the cost of cross board test.
Easily full of beard and be the processing unit 01 described in the embodiment of the invention, cross processing unit 02, to reset frame unit 03 and all can be integrated in output processing unit 04 and realize identical function in one or more chips and reach similar effect.
Please refer to Fig. 9, Fig. 9 is the flow chart of cross board method of testing of having used the cross board test macro of the embodiment of the invention, and described cross board method of testing comprises the steps:
Step 300: the elementary input/output port of cross board is linked to each other with the input/output port of testing apparatus, and the input port of each secondary input/output port of cross board is connected with output port.
Easily full of beard and be in step 300, can adopt bus or simple jockey to realize that the input port of secondary input/output port is connected connection with output port.
Step 301: send business datum to cross board by testing apparatus.
Step 302: cross board returns the business datum that receives behind the direct loopback of every a pair of input/output port, in described loopback, in the high-order cross chips of cross board, adopt measurability (DFT, Design ForTestability) design will be sent to output port business datum frame head with export by output port again after the system frame head aligns.
This is because cross chips has strict restriction to the deviation between the business datum frame head of each input/output port, requires the business datum frame head of each input/output port substantially to align.But cross chips is when processing business datum, and the deviation between each business datum frame head is much larger than the requirement of cross chips self.That is to say, from the business datum of an input port, by the cross processing of high-order cross chips, behind an output port, when directly being looped back to another input port again, can not satisfy the high-order cross chips to the requirement of frame head alignment.Therefore in the method for testing that the embodiment of the invention provides, employing DFT method for designing realizes the alignment of each input/output port business datum frame head in the high-order cross chips, to satisfy the high-order cross chips to the requirement of business datum frame head alignment.
In this step, describedly in the high-order cross chips, adopt the DFT method for designing that the frame head of business datum is alignd with the system frame head can to adopt following arbitrary execution mode realization:
Execution mode one:
Receive described business datum and system's frame head.
When receiving the frame head of described business datum, 0 beginning writes described business datum in twoport random-access memory (RAM, Random-Access Memory) from the address.
When receiving system's frame head, begin to read the business datum that writes from the address 0 of described dual port RAM, with the business datum that the reads business datum after as alignment.
Execution mode two:
Receive described business datum and system's frame head.
From the traffic frame of described business datum, parse pointer value.
Determine payload position in the described traffic frame according to the pointer value that parses, described payload is write synchronous first in first out buffering (FIFO, First In First Out).
When receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes.
From synchronization fifo, read the payload that writes, the payload that reads is added in the described new traffic frame.
From described new traffic frame, calculate new pointer value according to the payload that adds, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, with the business datum of described new traffic frame after as alignment.
Execution mode three:
Receive described business datum and system's frame head.
Calculate the difference of frame head and system's frame head of traffic frame in the described business datum.
Pointer value according to traffic frame in the difference that calculates and the described business datum is calculated the pointer value that makes new advances.
Determine payload position in the described traffic frame described payload to be write synchronization fifo according to the pointer value of traffic frame in the described business datum.
When receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes.
From synchronization fifo, read the payload that writes according to the SDH/SONET agreement, the payload that reads is added in the described new traffic frame, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, with the business datum of described new traffic frame after as alignment.
Execution mode four:
Receive described business datum and system's frame head.
Determine j1 byte position in payload position in the described traffic frame and the payload according to the pointer value of traffic frame in the described business datum, for making the J1 sign in described j1 byte position, described payload and J1 sign are write synchronization fifo.For example, in eight payload, determine first the position of j1 byte in payload position and the payload, will make the J1 sign to the position of j1 byte again, payload and J1 sign has 9 like this, and this 9 bit data is write synchronization fifo.
When receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes.
From synchronization fifo, read the payload and the J1 home position that write, the payload that reads is added in the described new traffic frame.
By described J1 home position and system frame head position are subtracted each other, obtain new pointer value, described new pointer value is added in the described new traffic frame as the pointer value of described new traffic frame, with the business datum of described new traffic frame after as alignment.
Wherein, in the situation that the pointer value that sends business datum to described cross board remains unchanged, can adopt execution mode three and execution mode four.
Step 303: described testing apparatus receives test data from the output port of described elementary input/output port, and relatively whether its received test data is consistent with its test data that sends, if so, judge that then described cross board is normal, otherwise judge that described cross board is undesired.
Can find out that from technique scheme according to the cross board method of testing that the embodiment of the invention provides, business datum directly at the every a pair of input/output port loopback of cross board, does not need full configuration service plate, therefore, can reduce the cost of cross board test.
The further flow chart of the cross board method of testing that Figure 10 provides for the embodiment of the invention.As shown in figure 10:
Step 400: the elementary input/output port of cross board is linked to each other with the input/output port of testing apparatus, and the input port of each secondary input/output port of cross board is connected with output port.
Easily full of beard and be in step 400, can adopt bus or simple jockey to realize that the input port of secondary input/output port is connected connection with output port.
Step 401: by the input port transmission business datum of described testing apparatus to the elementary input/output port of cross board.
Step 402: cross board returns to testing apparatus with the business datum that receives behind every direct loopback of a pair of secondary input/output port, in described loopback, in the high-order cross chips of cross board, adopt the DFT method for designing will be sent to output port business datum frame head with export by output port again after the system frame head aligns.
Please together with reference to Fig. 3, in the present embodiment, testing apparatus will be tested with stating the input port 5021a that business datum is sent to the elementary input/output port 5021 of cross board, and the input port 5021a by described elementary input/output port 5021 is sent to cross board 502 again; Described business datum is crossed to the output port 5022b of corresponding secondary input/output port 5022 through cross board 502, exports its corresponding input port 5022a to through the output port 5022b of described secondary input/output port 5022; The input port 5022a of the secondary input/output port 5022 of described thorn is crossed to the data that receive the output port 5022b of next secondary input/output port 5022 through cross board; By that analogy, until business datum is through behind all secondary input/output ports 5022, be crossed to the output port 5021b of elementary input/output port 5021 through cross board 502, and return by described output port 5021b.Finished the touring transmission of test with business datum.
Step 403: whether the business datum that relatively is sent to cross board is consistent with the business datum that described cross board returns, and if so, then execution in step 406, otherwise, execution in step 407.
Step 404: judge that cross board is normal.
Step 405: judge that cross board is undesired.
Can find out that from technique scheme according to the cross board method of testing that the embodiment of the invention provides, business datum directly at the every a pair of input/output port loopback of cross board, does not need full configuration service plate, therefore, can reduce the cost of cross board test.
From technique scheme, can find out, the cross board method of testing that the embodiment of the invention provides, system and high-order cross chips, business datum directly at the every a pair of input/output port loopback of cross board, do not need full configuration service plate, therefore, can reduce the cost of cross board test.
In addition, owing to do not need full configuration service plate just can realize test to cross board, simplified the test environment that cross board is tested.
In sum, more than be preferred embodiment of the present invention only, be not for limiting protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. cross board method of testing is used for cross board is tested, and described cross board is provided with a pair of elementary input/output port, and manyly secondary input/output port be is characterized in that described cross board method of testing comprises the steps:
The elementary input/output port of described cross board is linked to each other with testing apparatus, and the input port of every pair of secondary input/output port of cross board is connected with output port;
The input port of the elementary input/output port of described cross board receives the business datum from described testing apparatus;
Described cross board is processed the business datum that receives so that the frame head of business datum aligns with the system frame head, the again output of the output port from a pair of secondary input/output port, by being sent to this behind this output port to the input port of secondary input/output port, after input, again business datum is processed so that the frame head of business datum aligns with the system frame head, so circulation repeatedly, until described business datum is passed through all secondary input/output ports, and finally send to the output port of described elementary input/output port;
Described cross board sends the business datum of described frame head and system's frame head alignment to described testing apparatus from the output port of described elementary input/output port.
2. method according to claim 1, described cross board are alignd the frame head of business datum and are comprised with the system frame head:
Receive described business datum and system's frame head;
When receiving the frame head of described business datum, 0 beginning writes described business datum to twoport random-access memory RAM from the address;
When receiving system's frame head, begin to read the business datum that writes from the address 0 of described dual port RAM, with the business datum that the reads business datum after as alignment.
3. method according to claim 1 is characterized in that, described cross board aligns the frame head of business datum and comprises with the system frame head:
Receive described business datum and system's frame head;
From the traffic frame of described business datum, parse pointer value;
Determine payload position in the described traffic frame according to the pointer value that parses, described payload is write synchronous first in first out buffering FIFO;
When receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes;
From synchronization fifo, read the payload that writes, the payload that reads is added in the described new traffic frame;
From described new traffic frame, calculate new pointer value according to the payload that adds, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, with the business datum of described new traffic frame after as alignment.
4. method according to claim 1 is characterized in that, the pointer value that sends business datum to described cross board remains unchanged, and described cross board aligns the frame head of business datum and comprises with the system frame head:
Receive described business datum and system's frame head;
Calculate the difference of frame head and system's frame head of traffic frame in the described business datum;
Pointer value according to traffic frame in the difference that calculates and the described business datum is calculated the pointer value that makes new advances;
Determine payload position in the described traffic frame described payload to be write synchronization fifo according to the pointer value of traffic frame in the described business datum;
When receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes;
From synchronization fifo, read the payload that writes, the payload that reads is added in the described new traffic frame, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, with the business datum of described new traffic frame after as alignment.
5. method according to claim 1 is characterized in that, the pointer value that sends business datum to described cross board remains unchanged, and described cross board aligns the frame head of business datum and comprises with the system frame head:
Receive described business datum and system's frame head;
Determine the position of j1 byte in payload position in the described traffic frame and the payload for making the J1 sign in the position of described j1 byte, described payload and J1 sign to be write synchronization fifo according to the pointer value of traffic frame in the described business datum;
When receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes;
From synchronization fifo, read the payload and the J1 sign that write, the payload that reads is added in the described new traffic frame;
By described J1 home position and system frame head position are subtracted each other, obtain new pointer value, described new pointer value is added in the described new traffic frame as the pointer value of described new traffic frame, with the business datum of described new traffic frame after as alignment.
6. a cross board test macro is characterized in that, this system comprises: testing apparatus and cross board;
Described testing apparatus is used for sending business datum to cross board, receive the business datum that cross board returns, whether the business datum that relatively is sent to cross board is consistent with the business datum that described cross board returns, if, judge that then described cross board is normal, otherwise judge that described cross board is undesired;
Described cross board comprises a pair of elementary input/output port, many to secondary input/output port and a data processing module, described elementary input/output port links to each other with the data input and data output port of testing apparatus, and described many input port and output ports to secondary input/output port then interconnect; Cross board receives business datum from testing apparatus from the input port of elementary input/output port, be sent to data processing module, processed so that the frame head of business datum aligns with the system frame head by data processing module, again with the output port output of described business datum from a pair of secondary input/output port, by being sent to this behind this output port to the input port of secondary input/output port, after input, again process so that the frame head of business datum aligns with the system frame head through data processing module, so circulation repeatedly, until described business datum is passed through all secondary input/output ports, and finally send to the output port of described elementary input/output port; Send the business datum of described frame head and system's frame head alignment to described testing apparatus by the output port of described elementary input/output port.
7. test macro according to claim 6 is characterized in that, described data processing module comprises: input processing unit, output processing unit, cross processing unit and reset frame unit;
Described input processing unit be used for to receive business datum, and the business datum that receives is carried out input processing, and the input port of the business datum after the input processing by described input processing unit is sent to the cross processing unit;
Described cross processing unit is used for receiving the business datum from input processing unit, and the business datum that receives is crossed to the corresponding frame unit that resets;
The described frame unit that resets be used for to receive business datum from the cross processing unit, and the frame head of the business datum that receives is alignd with the system frame head, the business datum after the alignment is sent to the output processing unit of correspondence;
Described output processing unit is used for receiving from the business datum that resets frame unit, and the business datum that receives is exported processing, with the output port output of the business datum after processing by described output processing unit.
8. test macro according to claim 7 is characterized in that, the described frame unit that resets comprises: control unit and dual port RAM;
Described control unit is used for receiving business datum and the system's frame head from the cross processing unit, when receiving the frame head of described business datum, 0 beginning writes described business datum to dual port RAM from the address, when receiving system's frame head, begin to read the business datum that writes from the address 0 of dual port RAM, the business datum that reads is sent to corresponding output processing unit as the business datum after aliging;
Described dual port RAM is used for the buffer memory business datum.
9. test macro according to claim 7 is characterized in that, the described frame unit that resets comprises: pointer interpreter unit, memory cell and the first frame regeneration unit;
Described pointer interpreter unit be used for to receive the business datum from the cross processing unit, parses pointer value from the traffic frame of described business datum, determines payload position in the described traffic frame according to the pointer value that parses, with described payload write storage unit;
Described the first frame regeneration unit is used for the receiving system frame head, when receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes, reading payload from memory cell is added in the described new traffic frame, from described new traffic frame, calculate pointer value according to the payload that adds, the pointer value of described pointer value as described new traffic frame is added in the described new traffic frame, the business datum of described new traffic frame after as alignment is sent to corresponding output processing unit;
Described memory cell is used for the buffer memory business datum.
10. test macro according to claim 7 is characterized in that, the described frame unit that resets comprises: extraction unit, pointer computing unit, the second frame regeneration unit and memory cell;
Described extraction unit is used for receiving the business datum from the cross processing unit, frame head position and the pointer value of traffic frame in the described business datum are sent to the pointer computing unit, determine payload position in the described traffic frame according to the pointer value of traffic frame in the described business datum, with described payload write storage unit;
Described pointer computing unit is used for the receiving system frame head and from frame head and the pointer value of the traffic frame of extraction unit, calculate the difference of frame head and system's frame head of described traffic frame, pointer value according to the difference that calculates and described traffic frame is calculated the pointer value that makes new advances, and described new pointer value is sent to the second frame regeneration unit;
Described the second frame regeneration unit is used for the receiving system frame head and from the new pointer value of pointer computing unit, when receiving system's frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes, from memory cell, read the payload that writes, the payload that reads is added in the described new traffic frame, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, the business datum of described new traffic frame after as alignment is sent to corresponding output processing unit;
Described memory cell is used for the buffer memory business datum.
11. test macro according to claim 7 is characterized in that, the described frame unit that resets comprises: pointer positioning unit, the 3rd frame regeneration unit and memory cell;
Described pointer positioning unit is used for receiving the business datum from the cross processing unit, determine j1 byte position in payload position in the described traffic frame and the payload according to the pointer value of traffic frame in the described business datum, for making the J1 sign in the position of described j1 byte, with described payload and J1 sign write storage unit;
Described frame regeneration unit is used for the receiving system frame head, when receiving described system frame head, generate new traffic frame, the frame head of described new traffic frame and system-frame is first causes, from memory cell, read the position of the payload that writes and J1 sign, the payload that reads is added in the described new traffic frame, J1 home position and system frame head position are subtracted each other, obtain new pointer value, the pointer value of described new pointer value as described new traffic frame is added in the described new traffic frame, the business datum of described new traffic frame after as alignment is sent to corresponding output processing unit;
Described memory cell is used for the buffer memory business datum.
12. arbitrary described test macro is characterized in that according to claim 9～11, described memory cell is synchronization fifo.
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| CN101958763B (en) * | 2010-10-11 | 2015-09-16 | 中兴通讯股份有限公司 | The method and system of time-slot cross multi-channel aligning |
| KR102516027B1 (en) * | 2016-07-20 | 2023-03-31 | 삼성전자주식회사 | Header processing device, processor and electronic device |
| CN111488114B (en) * | 2019-01-28 | 2021-12-21 | 北京灵汐科技有限公司 | Reconfigurable processor architecture and computing device |
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| WO2004054187A3 (en) * | 2002-12-05 | 2004-09-23 | Cisco Tech Ind | Method for verifying function of redundant standby packet forwarder |
| CN1734271A (en) * | 2004-08-11 | 2006-02-15 | 华为技术有限公司 | TPS protection plate detection method |
| CN1838619A (en) * | 2005-03-24 | 2006-09-27 | 中兴通讯股份有限公司 | Method for realizing bare board test using false module and its device |
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| WO2004054187A3 (en) * | 2002-12-05 | 2004-09-23 | Cisco Tech Ind | Method for verifying function of redundant standby packet forwarder |
| CN1734271A (en) * | 2004-08-11 | 2006-02-15 | 华为技术有限公司 | TPS protection plate detection method |
| CN1838619A (en) * | 2005-03-24 | 2006-09-27 | 中兴通讯股份有限公司 | Method for realizing bare board test using false module and its device |
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