CN101592976B - Method for synchronizing clock of on-chip emulator to microprocessor clock domain - Google Patents
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Abstract
The invention relates to a method for synchronizing a clock of an on-chip emulator clock of a C core C310 embedded microprocessor chip to a microprocessor clock domain. In testing, a test clock signal j_tclk is latched sequentially by a first register and a second register of the microprocessor clock domain; after a signal of the output end of the second register is reversed, the signal and a signal of the output end of the first register are subjected to logic and calculation to obtain a first pulse to allow a signal j_tclk_rise to be used for controlling the sampling of a test mode selection signal j_tms and a test data input signal j_tdi by a register of the emulator; and simultaneously, after the test clock signal j_tclk is reversed, the test clock signal j_tclk and the signal of the output end of the second register are subjected to logic and calculation to obtain a second pulse to allow a signal j_tclk_fall to be used for controlling the sampling of a test data output signal j_tdo by the register of the emulator, therefore, a microprocessor chip structure with the on-chip emulator is realized under a single clock domain.
Description
Technical field
The present invention relates to a kind of SOC (system on a chip) SOC (System On Chip) clock synchronizing method, be specifically related to the method that a kind of clock (JTAG clock) with C core C310 embedded microprocessor (hereinafter to be referred as C310) chip on-chip emulator is synchronized to the microprocessor clock territory.
Background technology
The C310 chip is C Core Technology (Suzhou) Co., Ltd. improves exploitation based on the M310 of Motorola Inc. a high-performance microprocessor.This microprocessor is that the embedded Control that aims at high-performance and the bright sense of power consumption is used and designed, and emphasizes to reduce the power consumption of system.This microprocessor has 32 load/store Reduced Instruction Set Computer (RISC) framework; Fix 16 bit instruction length; 16 32 general-purpose register files; 4 grades of execution pipelines efficiently; The most instructions monocycle carries out, and the branch instruction visit only needs 2 cycles; Support the memory access of three types of byte, half-word and words; Support vector and from the interruption of moving vector; Design features such as hardware integer multiplier array.
The C310 chip internal mainly comprises two modules: microprocessor (MPU) module and on-chip emulator (On Chip Emulator, Once) module.
Microprocessor module is mainly finished reading of instruction, carries out functions such as data input and output.The on-chip emulator module is mainly the software developer and designs, and is convenient to develop the state that the commissioning staff in time observes functional module on microprocessor internal and the microprocessor outer plate.The on-chip emulator module provides the interactive mode between software developer and microprocessor and the peripherals thereof, and the developer can detected register, peripherals on storer and the sheet, accelerates based on the hardware and software development on the C310 chip.Come the work of emulator module on the control strip by industrial standard jtag interface access register.
Fig. 1 is a complete software development environment.High order end among the figure is exploitation PC (PC), be connected to EBDI (Enhanced Background Debug Interface) debugging box by serial line interface, linking to each other with the on-chip emulator module among the C310 of jtag interface standard and SOC (System On Chip) inside then.On-chip emulator arrives microprocessor by scan chain technique input and output instruction and data.Also comprising EMC (External Memory Controller) module and USB (the Universal Serial Bus) module that is integrated on CLB (the China Local Bus) bus on the SOC shown in this example, and be integrated in SCI (SerialCommunicate Interface) module on IPB (the Intellectual Property Bus) bus, PIT (Program Interrupt Timer) module and TIM (TIMER) module.
Jtag interface mainly comprises 5 pins: the TMS pin is used for test transmission mode select signal j_tms, TCK pin and is used for test transmission clock signal j_tclk, TDI pin and is used for that transmitting test data input signal j_tdi, TDO pin are used for transmitting test data output signal j_tdo, the TRST pin is used for test transmission reset signal j_trst_b.So in the SOC structure that with C310 is core, the clock of other modules on the clock of on-chip emulator module and the SOC is different.The clock of on-chip emulator module is j_tclk, and it directly comes from the EBDI debugging box that is attached thereto; The clock of other modules generally comes from the outer crystal circuit of sheet on microprocessor and the sheet.And these two clocks are without any incidence relation.
In the FPGA of C310 microprocessor implementation procedure, because the existence of the inner multi-clock zone of the singularity of FPGA structure and C310, make the overall performance of the C310 that realizes with FPGA all be limited in a lower level sometimes even be difficult to realize.The clock network that a special use is arranged in FPGA inside, this network can guarantee in the skew of the rising edge clock of inner each register of FPGA not too large.If a design has only a clock, so as long as directly use FPGA clock internal network to realize that the clock of this design can make design reach its maximum rated frequency to greatest extent.If but a design has plural clock, just exist the problem that realizes the design clock with non-clock network, even exist a plurality of clocks of a plurality of independently clock networks in can a plurality of special clock networks realizing respectively designing in some high-end FPGA inside, but the problem that also can have the transmission signals cross clock domain, these problems all can cause the performance of the whole design that realizes with FPGA uncontrollable or reduce sometimes greatly even can't realize such design.If but can a plurality of clocks are unified to same clock zone, just can reduce the difficulty that realizes with FPGA.
For the C310 chip, the clock of on-chip emulator module and microprocessor module is different, and these two clock zones have following two characteristics:
The first, according to the JTAG agreement, all JTAG signals all are to sample when the j_tclk rising edge.
The second, people are in the design and use microprocessor, and The faster the better always to wish speed, so the clock of microprocessor all can be in a higher frequency range (tens megahertzes are to megahertzes up to a hundred).In based on the microprocessor software performance history, need carry out man-machine conversation.And the existence of people's physical endurance has determined the exploitation debugging that speed is not had extra high requirement, so general commissioning staff only need just can satisfy the frequency configuration of emulator the needs of debugging to the speed of 1MHz.So in the process that reality is used, the clock frequency of the emulator of debugging usefulness all can be significantly less than the clock frequency of microprocessor.Utilize two above characteristics just two clocks can be united.
Summary of the invention
The object of the invention provides a kind of with the method for C310 chip on-chip emulator clock synchronization to C310 microprocessor clock territory, its objective is two clocks of on-chip emulator module and microprocessor module use are unified under same clock zone, make the FPGA of this microprocessor realize becoming simple, improve the performance of the C310 microprocessor of realizing with FPGA.
For achieving the above object, the technical solution used in the present invention is: a kind of with the method for on-chip emulator clock synchronization to the microprocessor clock territory, this method triggers the first register REG1 with the negative edge of microprocessor clock signal cpu_clk and latchs test clock signals j_tclk, data output end at the first register REG1 produces a clock negative edge latch signal j_tclk_delf, trigger the second register REG2 with the rising edge of microprocessor clock signal cpu_clk and come latch clock negative edge latch signal j_tclk_delf, rising edge clock of data output end generation at the second register REG2 latchs signal j_tclk_dly, carry out logic and operation with clock negative edge latch signal j_tclk_delf after then rising edge clock being latched signal j_tclk_dly negate, produce one and follow the first pulse enable signal j_tclk_rise that test clock signals j_tclk rising edge takes place, carry out logic and operation with latching signal j_tclk_dly with rising edge clock after the test clock signals j_tclk negate, produce one and follow the second pulse enable signal (j_tclk_fall) that test clock signals j_tclk negative edge takes place;
Be used to latch each register clock end input microprocessor clock signal cpu_clk of test mode select signal j_tms in the emulator, Enable Pin is imported the first pulse enable signal j_tclk_rise, when the first pulse enable signal j_tclk_rise effectively and microprocessor clock signal cpu_clk when being in rising edge, sampling test mode select signal j_tms;
Be used to latch each register clock end input microprocessor clock signal cpu_clk of input signal of test data j_tdi in the emulator, Enable Pin is imported the first pulse enable signal j_tclk_rise, when the first pulse enable signal j_tclk_rise effectively and microprocessor clock signal cpu_clk when being in rising edge, sampling input signal of test data j_tdi;
Be used in the emulator to latch and each register clock end input microprocessor clock signal cpu_clk of the output signal j_tdo that outputs test data, Enable Pin is imported the second pulse enable signal j_tclk_fall, when the second pulse enable signal j_tclk_fall effectively and microprocessor clock signal cpu_clk when being in rising edge, upgrade and the output signal j_tdo that outputs test data;
The frequency of microprocessor clock signal cpu_clk is greater than three times of test clock signals j_tclk frequency.
Related content in the technique scheme is explained as follows:
1, in the such scheme, described test mode select signal j_tms, input signal of test data j_tdi, test data output signal j_tdo and test clock signals j_tclk adopt the JTAG agreement, the JTAG agreement is a kind of international standard test protocol, is mainly used in the chip internal test and system is carried out emulation, debugging.The jtag interface of standard mainly comprises 5 pins: the TMS pin is used for test transmission mode select signal j_tms, TCK pin and is used for test transmission clock signal j_tclk, TDI pin and is used for that transmitting test data input signal j_tdi, TDO pin are used for transmitting test data output signal j_tdo, the TRST pin is used for test transmission reset signal j_trst_b.
2, in the such scheme, during the rising of certain the microprocessor clock signal cpu_clk of these two input signals of test mode select signal j_tms and the input signal of test data j_tdi rising edge of test clock signals j_tclk near by emulator in relevant register sampling; Upgrade output during the rising edge of certain microprocessor clock signal cpu_clk of the test data output signal j_tdo negative edge of test clock signals j_tclk near.
3, in the such scheme, described " frequency of microprocessor clock signal cpu_clk is greater than three times of test clock signals j_tclk frequency ", wherein the implication of " greater than three times " is meant that integral multiple or little several times more than three times all can, for example, the microprocessor clock frequency is 3.1 times of testing clock frequency, 3.8 doubly, 4 times etc.
4, in the such scheme, test clock signals j_tclk directly comes from EBDI debugging box; Microprocessor clock signal cpu_clk comes from the outer crystal circuit of sheet.
5, in the such scheme, first register and second register are to be the register of realizing the special setting of the inventive method (rather than the interior register of emulator), and wherein first register is the negative edge trigger register, and second register is the rising edge trigger register.
6, in the such scheme, the first pulse enable signal j_tclk_rise is a register enable signal with test clock j_tclk rising edge basic synchronization, and the second pulse enable signal j_tclk_fall is a register enable signal with test clock j_tclk negative edge basic synchronization.
Principle of work of the present invention is: utilize the series connection of first register and second register, under triggering, microprocessor clock signal cpu_clk latchs test clock signals j_tclk, with after the data output signal negate of second register and the data output signal of first register carry out logic and operation, obtain the first pulse enable signal j_tclk_rise; With after the test clock signals j_tclk negate and the data output signal of second register carry out logic and operation, obtain the second pulse enable signal j_tclk_fall; Cpu_clk replaces the test clock signals j_tclk that acts on each register input end of clock in the emulator originally with the microprocessor clock signal, control all data transfer directions in the emulator with the first pulse enable signal j_tclk_rise and be the register Enable Pin from the emulator to the microprocessor, test mode select signal j_tms and input signal of test data j_tdi are sampled, control all data transfer directions in the emulator for the register Enable Pin from the microprocessor to the emulator with the second pulse enable signal j_tclk_fall, upgrade and the output signal j_tdo that outputs test data.The present invention to the chip microprocessor work clock, has realized the microprocessor architecture of emulator on the strap in single clock territory with the on-chip emulator clock synchronization, makes the FPGA of this microprocessor chip realize that simple possible and its performance also have a distinct increment.
Description of drawings
Accompanying drawing 1 is C310 chip development environment synoptic diagram of the present invention;
Accompanying drawing 2 is the unified front and back of emulator of the present invention and microprocessor clock territory sequential chart;
Accompanying drawing 3 is the unified electrical schematic diagram to the microprocessor clock territory of register in the emulator of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment: a kind of with the method for on-chip emulator clock synchronization to the microprocessor clock territory
As shown in Figure 3, the first register REG1 is the negative edge trigger register, the second register REG2 is the rising edge trigger register, the clock end input microprocessor clock signal cpu_clk of the first register REG1 and the second register REG2, the first register REG1 uses the negative edge of microprocessor clock signal cpu_clk to trigger and latchs test clock signals j_tclk, data output end at the first register REG1 produces a clock negative edge latch signal j_tclk_delf, the data output end of the first register REG1 is connected with the data input pin of the second register REG2, the second register REG2 uses the rising edge of microprocessor clock signal cpu_clk to trigger latch clock negative edge latch signal j_tclk_delf, rising edge clock of data output end generation at the second register REG2 latchs signal j_tclk_dly, the rising edge clock of the second register REG2 data output end latch signal j_tclk_dly after the first not gate INV1 negate and the clock negative edge latch signal j_tclk_delf of the first register REG1 data output end carry out logic and operation by first with a door AND1, thereby produce one first with door AND1 output terminal and follow the first pulse enable signal j_tclk_rise that test clock signals j_tclk rising edge takes place, simultaneously with test clock signals j_tclk after the second not gate INV2 negate and the rising edge clock of the second register REG2 data output end latch signal j_tclk_dly and carry out logic and operation with a door AND2 by second, produces second a pulse enable signal j_tclk_fall who follows the generation of test clock signals j_tclk negative edge.
First is connected with the Enable Pin of door AND1 output terminal with the interior first registers group REGS1 of emulator, the first registers group REGS1 clock end input microprocessor clock cpu_clk in the emulator, when the first pulse enable signal j_tclk_fall effectively and microprocessor clock cpu_clk be in rising edge, first registers group REGS1 sampling test mode select signal j_tms in the emulator then.The first registers group REGS1 is exactly each register that is used to latch test mode select signal j_tms in the emulator, and its data transfer direction is to on-chip emulator from EBDI debugging box.
First is connected with the Enable Pin of door AND1 output terminal with the interior second registers group REGS2 of emulator, the second registers group REGS2 clock end input microprocessor clock cpu_clk in the emulator, when the first pulse enable signal j_tclk_fall effectively and microprocessor clock cpu_clk be in rising edge, second registers group REGS2 sampling input signal of test data j_tdi in the emulator then.The second registers group REGS2 is exactly each register that is used to latch input signal of test data j_tdi in the emulator, and its data transfer direction is to on-chip emulator from EBDI debugging box.
Second is connected with the Enable Pin of door AND2 output terminal with interior the 3rd registers group REGS3 of emulator, the 3rd registers group REGS3 clock end input microprocessor clock cpu_clk in the emulator, when the second pulse enable signal j_tclk_fall effectively and microprocessor clock cpu_clk be in rising edge, then the 3rd registers group REGS3 upgrades and the output signal j_tdo that outputs test data in the emulator.The 3rd registers group REGS3 is used in the emulator to latch and each register of the output signal j_tdo that outputs test data, and its data transfer direction is for debugging box from the on-chip emulator to EBDI.
The frequency of microprocessor clock signal cpu_clk equals four times of test clock signals j_tclk frequency in the present embodiment, in fact as long as greater than three times of test clock signals j_tclk frequency, and 3.1 times, 3.8 times or 4.32 times etc.
As shown in Figure 2, the first half is the on-chip emulator and the unified preceding sequential chart of microprocessor module clock of C310 chip, and wherein, j_trst_b is a test reset signal, and low level is effective.So when phase0, emulator module is reset.All input/output signals all change at the falling edge of j_tclk, and are sampled at the rising edge place of j_tclk.So, at phasel, phase2, phase3, the data of these four j_tclk rising edge place samplings of phase4 are as shown in table 1:
Table 1JTAG sampled result
| Phase1 | Phase2 | | Phase4 | |
| j_tms | ||||
| 1 | 1 | 0 | 0 | |
| |
0 | 0 | 1 | 0 |
| |
0 | 0 | 0 | 1 |
The Lower Half of Fig. 2 is the on-chip emulator of C310 chip and the sequential chart that microprocessor module clock first, second pulse enable signal after reunification produces, from Fig. 2 Lower Half as can be seen, clock zone after reunification, postponed the time in one and half microprocessor clock cycles before the sampling instant ratio for test mode select signal j_tms, input signal of test data j_tdi, in like manner the output time of test data output signal j_tdo is also than the time that postponed for one and half microprocessor clock cycles before.But as long as microprocessor clock frequency cpu_clk is greater than three times test clock j_tclk frequency, no matter be test mode select signal j_tms and the input signal of test data j_tdi that the registers group sampling derives from EBDI debugging box in the emulator, still the sampling of EBDI debugging box comes from the test data output signal j_tdo of registers group output in the on-chip emulator, does not all change.For j_tms and j_tdi input signal, at phase1, phase2, effectively the data of sampling are as shown in table 2 constantly for phase3, these four cpu_clk rising edges of phase4 and j_tclk_rise:
Emulator sampled result on the synchronous rear panel of table 2
| Phase1 | Phase2 | | Phase4 | |
| j_tms | ||||
| 1 | 1 | 0 | 0 | |
| |
0 | 0 | 1 | 0 |
At phase1, phase2, phase3, these four cpu_clk rising edges of phase4 and j_tclk_fall be j_tdo renewal constantly and output effectively.EBDI debugging box is as shown in table 3 in the result of above four j_tclk rising edges sampling j_tdo signal.
Table 3 is back EBDI sampled result synchronously
| Phase1 | Phase2 | | Phase4 | |
| j_tdo | ||||
| 0 | 0 | 0 | 1 |
Can find with table 1 and table 2, table 3, no matter be the data of on-chip emulator sampling EBDI, or the data of EBDI sampling on-chip emulator, deviation does not all take place in data.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (1)
- One kind with the on-chip emulator clock synchronization to the method in microprocessor clock territory, it is characterized in that:This method triggers first register (REG1) with the negative edge of microprocessor clock signal (cpu_clk) and latchs test clock signals (j_tclk), data output end at first register (REG1) produces a clock negative edge latch signal (j_tclk_delf), trigger second register (REG2) with the rising edge of microprocessor clock signal (cpu_clk) and come latch clock negative edge latch signal (j_tclk_delf), rising edge clock of data output end generation at second register (REG2) latchs signal (j_tclk_dly), carry out logic and operation with clock negative edge latch signal (j_tclk_delf) after then rising edge clock being latched signal (j_tclk_dly) negate, produce one and follow the first pulse enable signal (j_tclk_rise) that test clock signals (j_tclk) rising edge takes place, carry out logic and operation with latching signal (j_tclk_dly) with rising edge clock after test clock signals (j_tclk) negate, produce one and follow the second pulse enable signal (j_tclk_fall) that test clock signals (j_tclk) negative edge takes place;Be used to latch each register clock end input microprocessor clock signal (cpu_clk) of test mode select signal (j_tms) in the emulator, Enable Pin is imported the first pulse enable signal (j_tclk_rise), when the first pulse enable signal (j_tclk_rise) effectively and microprocessor clock signal (cpu_clk) when being in rising edge, sampling test mode select signal (j_tms);Be used to latch each register clock end input microprocessor clock signal (cpu_clk) of input signal of test data (j_tdi) in the emulator, Enable Pin is imported the first pulse enable signal (j_tclk_rise), when the first pulse enable signal (j_tclk_rise) effectively and microprocessor clock signal (cpu_clk) when being in rising edge, sampling input signal of test data (j_tdi);Be used in the emulator to latch and each register clock end input microprocessor clock signal (cpu_clk) of the output signal that outputs test data (j_tdo), Enable Pin is imported the second pulse enable signal (j_tclk_fall), when the second pulse enable signal (j_tclk_fall) effectively and microprocessor clock signal (cpu_clk) when being in rising edge, upgrade and the output signal that outputs test data (j_tdo);The frequency of microprocessor clock signal cpu_clk is greater than three times of test clock signals j_tclk frequency.
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| CN103019303B (en) * | 2012-12-26 | 2016-02-10 | 上海新储集成电路有限公司 | The regulating device of retention time on time sequence path and method |
| CN107908418B (en) * | 2017-12-12 | 2021-03-30 | 上海赛治信息技术有限公司 | Method for upgrading logic program of fiber channel node card and fiber channel bus equipment |
| FR3088125A1 (en) | 2018-11-06 | 2020-05-08 | Stmicroelectronics (Rousset) Sas | METHOD FOR MONITORING A TASK, IN PARTICULAR A GRAPHIC TASK, FOR AN ELECTRONIC MODULE, PARTICULARLY A MULTIMEDIA INTERFACE, AND CORRESPONDING DEVICE. |
| FR3088124A1 (en) * | 2018-11-06 | 2020-05-08 | Stmicroelectronics (Rousset) Sas | METHOD FOR PRODUCING TRIGGERING SIGNALS FOR CONTROLLING A MULTIMEDIA INTERFACE, AND CORRESPONDING INTEGRATED CIRCUIT |
| CN112036106B (en) * | 2020-08-17 | 2021-08-24 | 成都海光微电子技术有限公司 | Signal processing method, device, platform, storage medium and electronic equipment |
| CN112114831B (en) * | 2020-09-16 | 2023-08-01 | 天津津航计算技术研究所 | Firmware programming realization method based on UART interface |
| CN112055157B (en) * | 2020-09-21 | 2021-06-29 | 中国科学院长春光学精密机械与物理研究所 | Camera synchronization control system for multi-group TDI imaging |
| CN112416054B (en) * | 2020-10-30 | 2022-11-08 | 山东浪潮科学研究院有限公司 | Method for testing cross-clock-domain signal synchronization of FPGA design |
| CN114296510B (en) * | 2022-01-05 | 2024-05-07 | 深圳国微福芯技术有限公司 | On-chip clock controller |
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Address after: Room C2031, Suzhou Pioneer Park, 209 Zhuyuan Road, Suzhou High-tech Zone, Jiangsu Province Patentee after: Suzhou Guoxin Technology Co., Ltd. Address before: Room C2031, Suzhou Pioneer Park, 209 Zhuyuan Road, Suzhou High-tech Zone, Jiangsu Province Patentee before: C*Core Technology (Suzhou) Co., Ltd. |