CN101567871B - Method and device for improving ACLR index - Google Patents
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Abstract
The invention provides a method for improving an ACLR index, comprising the following steps: presetting a primary phase of a digital intermediate-frequency oscillator (NCO) in a digital frequency conversion chip; and synchronizing the NCO of each carrier wave digital frequency conversion channel again to form same phase. The invention also provides a device for improving an ACLR index. By adoptingthe method and the device, the invention eliminates the carrier wave error brought by aliquant control words of the NCO, solves the problem that the peak-to-average power ratio of baseband data fluct uates in each subframe, thereby further achieving the aim of improving the ACLR index; in addition, the invention can sufficiently exert the performance of a digital intermediate-frequency chip so that the digital interpolating times are not limited.
Description
Technical field
The present invention relates to the mobile communication technology field, relate in particular to the method and the device of multicarrier ACLR index in a kind of TD-SCDMA of the improvement system.
Background technology
At existing TD-SCDMA (Time Division Synchronous CDMA, Time Division-Synchronous Code Division Multiple Access) in the system, ACLR (Adjacent Channel Leakage Ratio, Adjacent Channel Leakage Power Ratio) be a important indicator in the base station radio radio-frequency (RF) index, this index shows that the working signal channel transmitting power falls the ratio of adjacent channel radiant power with it; Wherein, the most critical factor that influences ACLR is the peak-to-average force ratio of the linearity and the data of power amplifier, promptly increases the rated power of power amplifier and the peak-to-average force ratio of reduction base band data and all can improve the ACLR index.
Wherein, be the means of improving the ACLR index commonly used at present by the peak-to-average force ratio that reduces base band data; Stipulate in the standard of TD-SCDMA that at present each frequency all uses same midamble in the sub-district, and the same signal of a plurality of frequencies is superimposed and can causes the midamble peak value very high, much larger than data (data) part, promptly caused the peak-to-average force ratio of midamble too high, the peak-to-average force ratio that therefore will reduce base band data at first will consider to reduce the peak-to-average force ratio of midamble, two kinds of Peak-to-Average Power Ratio methods that improve midamble are arranged in the prior art usually: a kind of is phase place rotation between the carrier wave under the multicarrier, and a kind of is user's phase place rotation under the multicarrier; But, adopt when using above-mentioned two kinds of methods to improve the peak-to-average force ratio of midamble, can there be the situation of the data peak-to-average force ratio of severe exacerbation multicarrier by the slight errors of NCO (digital intermediate frequency oscillator), concrete reason is as follows:
Fig. 1 shows multi-carrier digital up-conversion structure, Fig. 2 shows multi-carrier digital down-conversion structure; As shown in the figure, when Digital IF Processing, for the corresponding NCO of each carrier wave of multicarrier operational environment, and the frequency computation part formula of NCO is:
NCO frequency control word=required NCO frequency/reference clock * 2
48
Wherein, required NCO frequency=rf frequency-local oscillator-reference clock,
Reference clock=1.28MHz (system's chip clock) * digital interpolation multiple (integer)
Wherein, when digital interpolation multiple (integer) can not be divided exactly by required NCO frequency, the NCO frequency control word was not an integer just, need round processing, and the part that will not eliminate abandons; And be 200Hz according to the carrier wave stepping of standard definition, therefore required NCO frequency is the integral multiple of 200Hz, this frequency frequency of utilization control word is controlled generation, after frequency control word rounds, can produce a very little frequency error, cause corresponding carriers not divided exactly by 200Hz, can cause using the first phase of time cycle (being that observing frequency is 200Hz) observed carrier signal of every 5ms when observing this carrier signal of 5ms all different like this, comprised an integer carrier signal cycle when only dividing exactly in each 5ms, the first phase of the carrier signal of every 5ms is just identical; Therefore, the peak-to-average force ratio difference of the data after the first phase difference of the NCO of a plurality of carrier waves of every subframe can cause every subframe multicarrier synthetic in continuous many sub-frame datas when aliquant, being equivalent to NCO has added a rotatable phase for each carrier signal, just changed carrier wave or user's rotatable phase, worsen algorithm performance and then worsened the base band data peak-to-average force ratio, thereby also just worsened the ACLR index.
At this, the method for existing head it off is to guarantee that the digital interpolation multiple is 2 N power, thereby can eliminate the frequency error of NCO; But, in the clock ranges that chip allows, require digital interpolation times speed to be the bigger the better at present, and this solution just can not guarantee that the digital interpolation multiple is enough big, thereby also just can not effectively utilize the performance of digital intermediate frequency chip when assurance digital interpolation multiple is N power of 2.
Summary of the invention
In view of this, method and device that the problem that the present invention solves provides a kind of ACLR of improvement index have effectively improved the ACLR index.
For addressing the above problem, technical scheme provided by the invention is as follows:
A kind of method of improving the ACLR index comprises:
Digital intermediate frequency oscillator NCO first phase in the preset number frequency conversion chip;
With the NCO first phase of each carrier wave numeral frequency conversion channel is same phase heavily synchronously.
Wherein, described default first phase is specially:
Value to the NCO first phase register in the digital frequency conversion chip sets in advance.
Wherein, described heavyly be specially synchronously:
Produce the heavy synchronizing signal of phase place according to the system synchronization signal;
The NCO first phase of each carrier wave numeral frequency conversion channel in the digital frequency conversion chip is re-set as the value of described first phase register according to this heavy synchronizing signal.
Wherein, described system synchronization signal is the 5ms pulse synchronous signal in the system.
Wherein, described digital frequency conversion chip is a Digital Up Convert DUC chip.
Wherein, described digital frequency conversion chip is Digital Up Convert DUC chip and Digital Down Convert DDC chip.
Wherein, the value of the described first phase register that sets in advance is 0.
A kind of device that improves the ACLR index comprises: default unit and heavy lock unit; Wherein,
Described default unit is used for: the digital intermediate frequency oscillator NCO first phase of preset number frequency conversion chip;
Described heavy lock unit is used for: with the heavy synchronous same phase that is of the NCO first phase of each carrier wave numeral frequency conversion channel.
Wherein, described default unit is further used for the value of the NCO first phase register in the digital frequency conversion chip is set in advance.
Wherein, described heavy lock unit also comprises: receiving element is put the unit with reseting; Wherein,
Described receiving element is used for: the receiving system synchronizing signal;
Described reseting put the unit and is used for: produce heavy synchronizing signal according to the system synchronization signal that receives, and utilize this heavy synchronizing signal the NCO first phase of each carrier wave numeral frequency conversion channel in the digital frequency conversion chip to be re-set as the value of described first phase register.
Wherein, described system synchronization signal is the 5ms pulse synchronous signal in the system.
Wherein, described digital frequency conversion chip is a Digital Up Convert DUC chip; Perhaps,
Described digital frequency conversion chip is Digital Up Convert DUC chip and Digital Down Convert DDC chip.
As can be seen, adopt method and apparatus of the present invention, reset by first phase the NCO of all carrier waves, first phase in the digital frequency conversion passage of each carrier wave heavily is synchronized to same phase, eliminated the aliquant carrier wave error of bringing of NCO control word with this, solve the problem that the base band data peak-to-average force ratio fluctuates in each subframe, and then realized improving the purpose of ACLR index; Can also give full play to simultaneously the performance of digital intermediate frequency chip, make the digital interpolation multiple unrestricted.
Description of drawings
Fig. 1 is a multi-carrier digital up-conversion structural representation in the prior art;
Fig. 2 is a multi-carrier digital down-conversion structural representation in the prior art;
Fig. 3 is the method flow schematic diagram of the embodiment of the invention 1;
Fig. 4 is the schematic diagram that the method for the embodiment of the invention 1 realizes in a single aerial system;
Fig. 5 is the schematic diagram that the method for the embodiment of the invention 1 realizes in antenna system;
Fig. 6 is the apparatus structure schematic diagram of the embodiment of the invention 4.
Embodiment
Basic thought of the present invention is to reset by the first phase to the NCO of all carrier waves, first phase in the digital frequency conversion passage of each carrier wave heavily is synchronized to same phase, eliminated the aliquant carrier wave error of bringing of NCO control word with this, solve the problem that the data peak-to-average force ratio fluctuates in each subframe, and then realized improving the purpose of ACLR index.
In order to make those skilled in the art better understand the present invention, method of the present invention is elaborated below in conjunction with the drawings and specific embodiments.
The embodiment of the invention 1 has proposed a kind of method of the ACLR of improvement index, and as shown in Figure 3, this method comprises:
Step 301: the NCO first phase in the preset number frequency conversion chip;
Wherein, mainly set in advance the setting of finishing first phase by value to the first phase register;
If a single aerial system then mainly by setting in advance the value of the NCO first phase register in Digital Up Convert (DUC) chip, is finished the setting of NCO first phase with this, need not to consider the situation of the NCO first phase in Digital Down Convert (DDC) chip this moment;
If antenna system, the value of the NCO first phase register in need setting in advance Digital Up Convert (DUC) chip, for the consideration that guarantees the antenna calibration result, also need to set in advance the value of the NCO first phase register in Digital Down Convert (DDC) chip, finish the setting of NCO first phase with this;
Step 302: with the NCO first phase of each carrier wave numeral frequency conversion channel is same phase heavily synchronously.
Concrete, at first producing a heavy synchronizing signal according to the system 5ms synchronizing signal that receives (can be easy to a synchronous conversion of signals is become another synchronizing signal in the chip usually, this paper repeats no more), according to this heavy synchronizing signal the NCO first phase in the numeral of each carrier wave in digital frequency conversion chip frequency conversion channel is re-set as the value of first phase register then, it is synchronously heavy that just every 5ms carries out a NCO phase place.Entry-into-force time is the die response time, is no more than the time of 1 chip usually; Can weigh the NCO first phase in all carrier wave numeral frequency conversion channel synchronously like this be same phase, and this same phase is the value of default first phase register, synchronous with this weight of having realized the NCO first phase; Certainly, wherein also comprised several different situations, for example:
If a single aerial system, then described digital frequency conversion chip is the DUC chip; And be chosen in ascending time slot and produce heavy synchronizing signal, to eliminate influence to downlink data;
If antenna system, then described digital frequency conversion chip is respectively DUC chip and DDC chip; And be chosen in ascending time slot and produce heavy synchronous DUC signal,, be chosen in descending time slot and produce heavy synchronous DDC signal, to eliminate influence to upstream data to eliminate influence to downlink data.
Those skilled in the art understand, when there is slight errors in the NCO frequency, such as carrier wave 1 deviation is 0.1Hz, carrier wave 2 deviation 0.2Hz or the like, this moment, the NCO frequency was 200Hz (frequency of a 5ms correspondence) integral multiple no longer just, and the first phase of each carrier wave is different among at this moment every 5ms, and changes and dynamic change in time, therefore cause the base band data peak-to-average force ratio to change and dynamic change in time, can't control; And the embodiment of the invention is every subframe is carried out again synchronously to the first phase of the NCO of all carrier waves after, each carrier wave first phase is forced to be changed to identical value (promptly heavy is same phase synchronously) at each 5ms, identical first phase is convenient to use other means to reduce the base band data peak-to-average force ratio, at this moment the first phase of each carrier wave is identical among every 5ms, and the peak-to-average force ratio of base band data will can not be subjected to the influence of digital intermediate frequency again; Therefore, the embodiment of the invention is carried out again synchronous in every subframe to the first phase of the NCO of all carrier waves, can will there be slight errors and influence when the multicarrier data are merged is stable lives by the NCO frequency, solved the problem that the data peak-to-average force ratio fluctuates in each subframe, and then improved the ACLR index of system, can give full play to simultaneously the performance of digital intermediate frequency chip, and the digital interpolation multiple is unrestricted.
It should be noted that the system synchronization signal that receives in embodiments of the present invention is the 5ms pulse synchronous signal in the system, can certainly be other the synchronizing signal that can realize this function, and this paper repeats no more.
Be that example is elaborated with the implementation of said method in a single aerial system and antenna system below:
The embodiment of the invention 2 is the implementation of said method in a single aerial system, as shown in Figure 4:
In the present embodiment, send heavy synchronizing signal mainly by FPGA (Field Programmable GateArray, finish field programmable gate array) that (but present embodiment is not limited thereto, also can be other chips of realizing this function, as asic chip etc.), FPGA bears the function that the multicarrier data are distributed from the base band to the digital intermediate frequency, promptly receive the data after Base-Band Processing and send to digital frequency conversion to handle;
In the implementation of single antenna, the value of the NCO first phase register in the at first default DUC chip is 0, again by FPGA receiving system 5ms synchronizing signal and produce a heavy synchronizing signal, according to described heavy synchronizing signal the NCO first phase of each carrier wave DUC passage in the DUC chip is re-set as the value (the NCO first phase that is about to each carrier wave DUC passage is re-set as 0) of above-mentioned default first phase register then, make the NCO first phase of each carrier wave DUC passage identical, the time-delay that comes into force is no more than 1 chip, the entry-into-force time point selection is at ascending time slot, to eliminate the influence to downlink data.
The embodiment of the invention 3 is the implementation of said method in antenna system, as shown in Figure 5:
In the present embodiment, equally producing heavy synchronizing signal with embodiment 2 is mainly finished by FPGA; In the implementation of smart antenna, at first with in the DUC chip and the value of NCO first phase register in the DDC chip all be preset as 0, receive the heavy synchronizing signal that sends respectively by FPGA then, be re-set as the value (the NCO first phase that is about to each carrier wave DUC passage is set to 0) of NCO first phase register in the above-mentioned default DUC chip again according to the NCO first phase of each the carrier wave DUC passage in the described heavy synchronizing signal DUC chip, be re-set as simultaneously the value (the NCO first phase that is about to each carrier wave DUC passage is set to 0) of NCO first phase register in the above-mentioned default DDC chip according to the NCO first phase of each the carrier wave DDC passage in the described heavy synchronizing signal DDC chip, identical with the NCO first phase that makes each carrier wave DUC passage respectively, the NCO first phase of DDC passage is identical, the time-delay that comes into force is no more than 1 chip, the entry-into-force time point selection produces heavy synchronous DUC signal at ascending time slot, to eliminate influence to downlink data, be chosen in descending time slot simultaneously and produce heavy synchronous DDC signal, to eliminate influence upstream data.
It should be noted that, though in the embodiment of the invention 2,3 all with chip in the value of NCO first phase register be made as 0, but this is a kind of preferred scheme, obviously working as the embodiment of the invention is not limited thereto, as long as the NCO first phase of each carrier wave numeral frequency conversion channel of heavy back synchronously is identical, then the value of this register is made as other numerical value and also can.
As can be seen, adopt method of the present invention, eliminated the aliquant carrier wave error of bringing of NCO control word, therefore guaranteed the peak-to-average force ratio of base band data, and then can improve the ACLR index; Can also give full play to simultaneously the performance of digital intermediate frequency chip, make the digital interpolation multiple unrestricted.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to finish by the relevant hardware of program command, and described procedure stores is in the particular memory medium.
Based on above-mentioned thought, the embodiment of the invention 4 has proposed a kind of device of the ACLR of improvement index again, as shown in Figure 6, comprising: default unit 601 and heavy lock unit 602; Wherein,
Described default unit 60l is used for: the digital intermediate frequency oscillator NCO first phase of preset number frequency conversion chip;
Described heavy lock unit 602 is used for: with the heavy synchronous same phase that is of the NCO first phase of each carrier wave numeral frequency conversion channel.
Wherein, described default unit is further used for the value of the NCO first phase register in the digital frequency conversion chip is set in advance.
In addition, described heavy lock unit also comprises: receiving element is put the unit with reseting; Wherein, described receiving element is used for: the receiving system synchronizing signal; Described reseting put the unit and is used for: produce heavy synchronizing signal according to the system synchronization signal that receives, and utilize this heavy synchronizing signal the NCO first phase of each carrier wave numeral frequency conversion channel in the digital frequency conversion chip to be re-set as the value of described first phase register.
It should be noted that the described system synchronization signal that receives is the 5ms pulse synchronous signal in the system.
Wherein, described digital frequency conversion chip is a Digital Up Convert DUC chip; Perhaps, described digital frequency conversion chip is Digital Up Convert DUC chip and Digital Down Convert DDC chip.
Concrete, in a single aerial system, the value of the NCO first phase register in the at first default DUC chip in default unit is 0, receiving element receiving system synchronizing signal then, put the unit according to the heavy synchronizing signal of described system synchronization signal generation and reset, and the NCO first phase of each carrier wave DUC passage in the DUC chip is re-set as 0 according to this heavy synchronizing signal, make the NCO first phase of each carrier wave DUC passage identical; Wherein, described system synchronization signal is the 5ms pulse synchronous signal in the system;
In antenna system, default unit at first with in the DUC chip and the value of NCO first phase register in the DDC chip all be preset as 0, receiving element receives synchronizing signal then, put the unit again according to the heavy synchronizing signal of described synchronizing signal generation and reset, and according to this heavy synchronizing signal the NCO first phase of each the carrier wave DUC passage in the DUC chip is re-set as 0, according to heavy synchronizing signal the NCO first phase of each the carrier wave DDC passage in the DDC chip is re-set as 0 simultaneously, NCO first phase identical with the NCO first phase that makes each carrier wave DUC passage respectively, the DDC passage is identical; Equally, described system synchronization signal is the 5ms pulse synchronous signal in the system.
It will be understood by those skilled in the art that and to use many different technologies and in the technology any one to come expression information, message and signal.For example, the message of mentioning in the above-mentioned explanation, information can be expressed as voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or above combination in any.
The professional can also further should be able to recognize, the unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein, can realize with electronic hardware, computer software or the combination of the two, for the interchangeability of hardware and software clearly is described, the composition and the step of each example described prevailingly according to function in the above description.These functions still are that software mode is carried out with hardware actually, depend on the application-specific and the design constraint of technical scheme.The professional and technical personnel can use distinct methods to realize described function to each specific should being used for, but this realization should not thought and exceeds scope of the present invention.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined herein General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a method of improving the neighboring trace leakage power than ACLR index is characterized in that, comprising:
Digital intermediate frequency oscillator NCO first phase in the preset number frequency conversion chip; Described default first phase is specially:
Value to the NCO first phase register in the digital frequency conversion chip sets in advance;
With the NCO first phase of each carrier wave numeral frequency conversion channel is same phase heavily synchronously; Described heavyly be specially synchronously: produce the heavy synchronizing signal of phase place according to the system synchronization signal; The NCO first phase of each carrier wave numeral frequency conversion channel in the digital frequency conversion chip is re-set as the value of described first phase register according to this heavy synchronizing signal;
Described digital frequency conversion chip is meant in a single aerial system it is Digital Up Convert DUC chip, is Digital Up Convert DUC chip and Digital Down Convert DDC chip in antenna system.
2. method according to claim 1 is characterized in that:
Described system synchronization signal is the 5ms pulse synchronous signal in the system.
3. according to any described method of claim 1 to 2, it is characterized in that:
The value of the described first phase register that sets in advance is 0.
4. a device that improves the neighboring trace leakage power than ACLR index is characterized in that, comprising: default unit and heavy lock unit; Wherein,
Described default unit is used for: the digital intermediate frequency oscillator NCO first phase of preset number frequency conversion chip; Described default unit is further used for the value of the NCO first phase register in the digital frequency conversion chip is set in advance;
Described heavy lock unit is used for: with the heavy synchronous same phase that is of the NCO first phase of each carrier wave numeral frequency conversion channel; Described heavy lock unit also comprises: receiving element is put the unit with reseting; Wherein, described receiving element is used for: the receiving system synchronizing signal; Described reseting put the unit and is used for: produce heavy synchronizing signal according to the system synchronization signal that receives, and utilize this heavy synchronizing signal the NCO first phase of each carrier wave numeral frequency conversion channel in the digital frequency conversion chip to be re-set as the value of described first phase register;
Described digital frequency conversion chip is meant in a single aerial system it is Digital Up Convert DUC chip, is Digital Up Convert DUC chip and Digital Down Convert DDC chip in antenna system.
5. device according to claim 4 is characterized in that:
Described system synchronization signal is the 5ms pulse synchronous signal in the system.
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| CN1494246A (en) * | 2002-11-01 | 2004-05-05 | 华为技术有限公司 | Methd of collecting code plate clock synchronized signal used under mobile communicatin environment |
| CN1520029A (en) * | 2002-12-11 | 2004-08-11 | 三星电子株式会社 | Digital controlled oscillator, digital cnverter and RF unit |
| CN1835389A (en) * | 2005-03-14 | 2006-09-20 | 华为技术有限公司 | Method able to eliminate frequency error of digital controlled oscillator and phase accumulator |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000253089A (en) * | 1999-02-26 | 2000-09-14 | Sanyo Electric Co Ltd | Digital costas loop circuit |
| CN1494246A (en) * | 2002-11-01 | 2004-05-05 | 华为技术有限公司 | Methd of collecting code plate clock synchronized signal used under mobile communicatin environment |
| CN1520029A (en) * | 2002-12-11 | 2004-08-11 | 三星电子株式会社 | Digital controlled oscillator, digital cnverter and RF unit |
| CN1835389A (en) * | 2005-03-14 | 2006-09-20 | 华为技术有限公司 | Method able to eliminate frequency error of digital controlled oscillator and phase accumulator |
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