CN101567214B - Line selector applicable to reading and wiring functions of nine-transistor memory unit - Google Patents
Line selector applicable to reading and wiring functions of nine-transistor memory unit Download PDFInfo
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- CN101567214B CN101567214B CN2009100722346A CN200910072234A CN101567214B CN 101567214 B CN101567214 B CN 101567214B CN 2009100722346 A CN2009100722346 A CN 2009100722346A CN 200910072234 A CN200910072234 A CN 200910072234A CN 101567214 B CN101567214 B CN 101567214B
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Abstract
A line selector applicable to reading and wiring functions of a nine-transistor memory unit belongs to the field of digital electronics and aims at solving the problem that the nine-transistor memory unit can not directly control and select a line needing to be read or written through a decoding line. The line selector comprises a three-input AND gate, a two-input AND gate and an NON gate. The first input end of the three-input AND gate is a write control signal input end; the third input end of the three-input AND gate is a NON gate end; the output end of the three-input AND gate is a line selection write enabling signal output end and connected with a WR wire of the nine-transistor memory unit; the second input end of the three-input AND gate and the first input end of the two-input AND gate are line address signal input ends; the second input end of the two-input AND gate and the input end of the NON gate are read control signal input ends; the output end of the NON gate is connected with the NON gate end of the tree-input AND gate; and the output end of the two-input AND gate is a line selection read enabling signal output end and is connected with an RD wire of the nine-transistor memory unit. The line selector is applied to line selection of a memory used for the nine-transistor memory unit.
Description
Technical field
The present invention relates to a kind of row selector that adapts to the nine-transistor memory unit read-write capability, belong to the digital and electronic field.
Background technology
Existing storer generally with six traditional tubular constructions as its storage unit (as Fig. 1), plurality of advantages such as it is fast that six transistor memory units have speed, and area is little.But back end is by gate pipe (N3 in its cellular construction, N4) directly link to each other with bit line WL, dividing potential drop owing to phase inverter and gate pipe in the read cycle makes the data of storing in the back end be more vulnerable to the influence of outside noise, this has caused the decline of its read stability and noise margin, and in order to satisfy the requirement of certain read stability, just require in its cross coupling inverter pull-down transistor (N1, size N2) will strengthen accordingly, this has just caused the increase of quiescent dissipation.
The structure of nine-transistor memory unit (as Fig. 2) can improve the read stability of storage unit and reduce power consumption, overcomes the shortcoming that six transistor memory units exist.In the read cycle, stored data " 1 " among the hypothesis Node1 that is without loss of generality, to high level, the WR signal remains on low level to BL by preliminary filling, and RD is promoted to high level to begin to read.This moment, N5, N7 opened, and BL is by N5, N7 discharge, and back end Node1 and bit line are isolated fully in this process, and its read stability is greatly improved.Because its read stability greatly improves, then the transistorized size of nine-transistor memory unit can minimize and need not consider that this has just reduced power consumption for read stability.
For six traditional transistor memory units, have only signal controlling of bit line WL in the read-write process, WL is high level in the read-write cycle.Therefore decipher the purpose that line can directly link to each other with bit line WL and select current line to reach.And in improved nine-transistor memory unit, used two signals of WR and RD.In write cycle time, the WR signal is high, and the RD signal is low, and in the read cycle, the WR signal is low, and the RD signal is high.This makes the decoding line can't directly control the row that selection need be read and write.
Summary of the invention
The objective of the invention is to solve nine-transistor memory unit and can't directly control the problem of the row that selection need be read and write, a kind of row selector that adapts to the nine-transistor memory unit read-write capability is provided by the decoding line.
The present invention includes three inputs and door, two inputs and door and not gate, three inputs are the write control signal input end with the first input end of door, and three inputs are the not gate end with the 3rd input end of door, and three inputs select to write the enable signal output terminal with the output terminal of door for row; Three inputs are the row address signal input end with second input end of door and the first input end of two inputs and door, two inputs are the read control signal input end with second input end of door and the input end of not gate, the output terminal of not gate links to each other with the not gate end of door with three inputs, and two inputs select to read the enable signal output terminal with the output terminal of door for row.
Advantage of the present invention: the present invention proposes a kind of row selector structure.The row address signal that its input end receives read-write control signal respectively and exported by the decoding line, its output terminal links to each other with WR line, RD line respectively.The row of selecting current needs to read and write by the decode results and the read-write control signal of address signal, and the correct read-write operation that carries out.
Description of drawings
Fig. 1 is six transistor memory unit structural representations, Fig. 2 is the nine-transistor memory unit structural representation, Fig. 3 is the structural representation of row selector of the present invention, and Fig. 4 is the physical circuit figure of row selector of the present invention, and Fig. 5 is the effect emulation figure that uses the nine-transistor memory unit of the inventive method.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 3 to Fig. 5, present embodiment comprises three inputs and door 1, two inputs and door 2 and not gate 3, three inputs are the write control signal input end with the first input end of door 1, three inputs are the not gate end with the 3rd input end of door 1, and three inputs select to write the enable signal output terminal with the output terminal of door 1 for row; Three inputs are the row address signal input end with second input end of door 1 and the first input end of two inputs and door 2, two inputs are the read control signal input end with second input end of door 2 and the input end of not gate 3, the output terminal of not gate 3 links to each other with the not gate end of door 1 with three inputs, and two inputs select to read the enable signal output terminal with the output terminal of door 2 for row.
Referring to structure of the present invention shown in Figure 3, the signal that the row address signal input end inserts is row address signal Row, is the result of code translator, decode results as current line is a high level, then row address signal Row is a high level, and promptly current behavior is effectively capable, represents this row selected; The signal that the write control signal input end inserts is write control signal Write, and is effective during high level; The signal that the read control signal input end inserts is read control signal Read, and is effective during high level; If this row is carried out write operation, then allow write control signal Write put high level, read control signal Read puts low level; If this row is carried out read operation, then allow read control signal Read put high level, write control signal Write puts low level; The WR line that enable signal output termination nine-transistor memory unit is write in selection connects, effective during high level, it is effective when row selects to read the RD line high level of enable signal output termination nine-transistor memory unit, WR height, the low representative of RD are carried out write operation to current selected line, and WR is low, the high representative of RD is carried out read operation to current selected line.
Below in conjunction with a specific embodiment its principle of work is described, include the capable nine-transistor memory unit of m in the storer with the nine-transistor memory unit formation, m is a natural number, every provisional capital is connected to row selector of the present invention, and the address of every row determines that by the result of code translator row address signal Row meets the result of code translator in the row selector of the present invention, decode results as current line is a high level, be that current behavior is effectively capable, represent this row selected, this row is carried out read-write operation.
Selected line is carried out the analysis of write operation, and three inputs are respectively with three input ends of door 1:
First input end (write control signal input end), write control signal Write high level;
Second input end (row address signal input end), row address signal Row high level, because high level is effective, high level represents that current line is selected;
The 3rd input end (not gate end), read control signal Read low level become high level and connect the not gate end behind not gate 3.
I.e. three inputs all are high level with three input ends of door 1, and the selection of then going is write enable signal output terminal output result and is high level, and promptly the WR line of nine-transistor memory unit connects high level, carries out write operation.
Two inputs are respectively with two input ends of door 2:
First input end (row address signal input end), row address signal Row high level, because high level is effective, high level represents that current line is selected;
Second input end (read control signal input end), read control signal Read low level.
I.e. two inputs are respectively high level and low level with two input ends of door 2, and it is low level that row selects to read enable signal output terminal output result, and promptly the RD line of nine-transistor memory unit connects low level, does not carry out read operation.
By row selector of the present invention, make the storer of using nine-transistor memory unit carry out correct write operation to the row of choosing, even not selected row write control signal this moment is that high level does not carry out any operation yet, be analyzed as follows:
Not selected as current line, row address signal Row low level then, in conjunction with the analysis of above-mentioned each port level, the input end one low two-supremes of three inputs and door 1, then exporting the result is low level, promptly the WR line of nine-transistor memory unit connects low level; Two low levels of input end of two inputs and door 2, then exporting the result is low level, promptly the RD line of nine-transistor memory unit connects low level, the not selected capable operation that does not does not read or write.
The analysis of selected line being carried out the analysis of read operation and write operation is similar, and three inputs are respectively with three input ends of door 1:
First input end (write control signal input end), write control signal Write low level;
Second input end (row address signal input end), row address signal Row high level, because high level is effective, high level represents that current line is selected;
The 3rd input end (not gate end), read control signal Read high level become low level and connect the not gate end behind not gate 3.
I.e. three inputs are high level with two of three input ends of door 1, and one is low level, and then exporting the result is low level, and promptly the WR line of nine-transistor memory unit connects low level, does not carry out write operation.
Two inputs are respectively with two input ends of door 2:
First input end (row address signal input end), row address signal Row high level, because high level is effective, high level represents that current line is selected;
Second input end (read control signal input end), read control signal Read high level.
I.e. two inputs all are high level with two input ends of door 2, and the output result is a high level, and promptly the RD line of nine-transistor memory unit connects high level, carries out read operation.
By row selector of the present invention, make the storer of using nine-transistor memory unit carry out correct read operation to the row of choosing, even being high level, not selected row read control signal do not carry out any operation yet, be analyzed as follows:
Not selected as current line, row address signal Row low level then, in conjunction with the analysis of above-mentioned level, three inputs are low with the input end three of door 1, and then exporting the result is low level, and promptly the WR line of nine-transistor memory unit connects low level; Input end one a low height of two inputs and door 2, then exporting the result is low level, promptly the RD line of nine-transistor memory unit connects low level, the not selected capable operation that does not does not read or write.
In sum, by the design of row selector of the present invention, realized to the correct selection of the row of the storage array formed by nine-transistor memory unit and to the acquisition of the correct logic of the control signal of storage unit.
Provide a concrete circuit diagram of realizing capable selection function of the present invention as shown in Figure 4.
Below in conjunction with experiment simulation design sketch shown in Figure 5, prove correctness by the memory application row selector of the present invention of nine-transistor memory unit.
With the nine-transistor memory unit is the complete memory that core is built a 8K size, the present invention is used wherein and to it carried out the read-write capability test, and test result is as follows:
The data of input described in the figure are 8 hexadecimal data, and Row is a row address signal, and Write is a write control signal, and Read is a read control signal, and sense data is 8 a hexadecimal data, should be identical with the input data, and clk is a clock signal.Find out that by figure write data 1 during 4ns, sense data 1 during 19ns; Write data 7 and f when 28ns and 40ns continuously, read 7 and f when 55ns and 63ns respectively.Correctness of the present invention and availability have been described.
Claims (2)
1. the row selector that adapts to the nine-transistor memory unit read-write capability, it is characterized in that, it comprises three inputs and door (1), two inputs and door (2) and not gate (3), three inputs are the write control signal input end with the first input end of door (1), three inputs are the not gate end with the 3rd input end of door (1), and three inputs select to write the enable signal output terminal with the output terminal of door (1) for row; Three inputs are the row address signal input end with second input end of door (1) and the first input end of two inputs and door (2), two inputs are the read control signal input end with second input end of door (2) and the input end of not gate (3), the output terminal of not gate (3) links to each other with the not gate end of door (1) with three inputs, and two inputs select to read the enable signal output terminal with the output terminal of door (2) for row.
2. the row selector of adaptation nine-transistor memory unit read-write capability according to claim 1 is characterized in that, write control signal input end, row address signal input end and read control signal input end all are that high level is effective.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100722346A CN101567214B (en) | 2009-06-10 | 2009-06-10 | Line selector applicable to reading and wiring functions of nine-transistor memory unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009100722346A CN101567214B (en) | 2009-06-10 | 2009-06-10 | Line selector applicable to reading and wiring functions of nine-transistor memory unit |
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| CN101567214A CN101567214A (en) | 2009-10-28 |
| CN101567214B true CN101567214B (en) | 2011-06-15 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6657878B2 (en) * | 2002-02-27 | 2003-12-02 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same |
| CN1524271A (en) * | 2001-01-31 | 2004-08-25 | 摩托罗拉公司 | Content addressable magnetic random access memory |
| CN1561522A (en) * | 2001-09-28 | 2005-01-05 | 睦塞德技术公司 | Circuit and method for performing variable width searches in a content addressable memory |
| US7009861B2 (en) * | 2003-02-20 | 2006-03-07 | Stmicroelectronics Pvt. Ltd. | Content addressable memory cell architecture |
| US7400523B2 (en) * | 2006-06-01 | 2008-07-15 | Texas Instruments Incorporated | 8T SRAM cell with higher voltage on the read WL |
-
2009
- 2009-06-10 CN CN2009100722346A patent/CN101567214B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524271A (en) * | 2001-01-31 | 2004-08-25 | 摩托罗拉公司 | Content addressable magnetic random access memory |
| CN1561522A (en) * | 2001-09-28 | 2005-01-05 | 睦塞德技术公司 | Circuit and method for performing variable width searches in a content addressable memory |
| US6657878B2 (en) * | 2002-02-27 | 2003-12-02 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same |
| US7009861B2 (en) * | 2003-02-20 | 2006-03-07 | Stmicroelectronics Pvt. Ltd. | Content addressable memory cell architecture |
| US7400523B2 (en) * | 2006-06-01 | 2008-07-15 | Texas Instruments Incorporated | 8T SRAM cell with higher voltage on the read WL |
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