CN101553925B - P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same - Google Patents

P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same Download PDF

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CN101553925B
CN101553925B CN200780042606XA CN200780042606A CN101553925B CN 101553925 B CN101553925 B CN 101553925B CN 200780042606X A CN200780042606X A CN 200780042606XA CN 200780042606 A CN200780042606 A CN 200780042606A CN 101553925 B CN101553925 B CN 101553925B
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conductor
diode
dielectric
silicide
connecting type
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CN101553925A (en
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S·布拉德·赫纳
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Sandy Technology Corp
SanDisk Technologies LLC
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SanDisk 3D LLC
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Priority claimed from US11/560,289 external-priority patent/US8018024B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only

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Abstract

A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer deposition. The diode ispreferably formed of deposited low- defect semiconductor material, crystallized in contact with a suicide. A monolithic three dimensional memory array of such cells can be formed in stacked memory le vels above the wafer substrate.

Description

Be adjacent to silicide and P-I-N diode of connecting with the anti-fuse of dielectric of crystallization and forming method thereof
The related application cross reference
This application case advocates that the title of application on November 15th, 2006 is the U.S. patent application case the 11/560th of " being adjacent to the P-I-N diode of connecting with the anti-fuse of dielectric (P-I-N Diode Crystallized Adjacent to a Silicide in Series witha Dielectric Antifuse) of silicide crystallization ", the title of No. 289 and on November 15th, 2006 application is for " being used for the method (Method for Making a P-I-N Diode Crystallized Adjacent to a Silicide in Series with aDielectric Antifuse ;) that making is adjacent to the P-I-N diode of connecting with the anti-fuse of dielectric of silicide crystallization " U.S. patent application case the 11/560th, No. 283 priority, each of described application case all are incorporated herein for the mode that all purposes are quoted in full.
Background technology
The present invention relates to comprise that electricity in series is formed at diode between the conductor and the Nonvolatile memery unit of dielectric rupture antifuse.In general, it is conducive to drop to the required voltage of this memory cell of programming minimum.
Summary of the invention
The present invention is defined by above claims, and any content all should not be considered as restriction to those claims in this paragraph.In general, the present invention is directed to Nonvolatile memery unit, it comprises the dielectric rupture antifuse that is formed by the anti-fuse materials of high-k and the semiconductor diode that is formed by the low resistivity semiconductor material.
A first aspect of the present invention provides a kind of and is used to form and the method for programming nonvolatile memory unit, and described method comprises: form connecting type p-i-n diode, described connecting type p-i-n diode comprises the semi-conducting material of deposition; Form the silicide, silicide-germanide or the Germanide layer that contact with the semi-conducting material of described deposition; Make the semi-conducting material crystallization of the described deposition that contacts with described silicide, silicide-germanide or Germanide layer; Formation has the dielectric materials layer greater than 8 dielectric constant; And making the part of described dielectric materials layer stand dielectric breakdown, wherein said memory cell comprises described connecting type p-i-n diode and described dielectric materials layer.
Another aspect of the present invention provides a kind of first memory level, and described first memory level comprises: a plurality of first almost parallels that form above substrate are coplanar conductor roughly; A plurality of second almost parallels that form above described first conductor are coplanar conductor roughly; Comprise the connecting type p-i-n diode of a plurality of vertical orientations of semi-conducting material, described semi-conducting material is adjacent to silicide, silicide-germanide or Germanide layer and crystallization; The a plurality of dielectric rupture antifuse that formed by the dielectric material that has greater than about 8 dielectric constant, each of wherein said connecting type p-i-n diode is placed between one in one in described first conductor and described second conductor, and each of wherein said dielectric rupture antifuse is placed between one between one in one in described first conductor and the described connecting type p-i-n diode or in one in described second conductor and the described connecting type p-i-n diode; And a plurality of memory cells, each memory cell comprises one in one and the described dielectric rupture antifuse in the described connecting type p-i-n diode.
The preferred embodiments of the present invention provide a kind of monolithic three dimensional memory array that is formed at the substrate top, described monolithic three dimensional memory array comprises: a) be monolithically formed in the first memory level of described substrate top, described first memory level comprises: i) a plurality of first almost parallels that extend along first direction coplanar conductor roughly; Ii) a plurality of second almost parallels that extend along the second direction that is different from described first direction coplanar conductor roughly, described second conductor is above described first conductor; Iii) by the connecting type p-i-n diode of a plurality of vertical orientations of forming of semi-conducting material of deposition, described semi-conducting material is adjacent to silicide, silicide-germanide or Germanide layer and crystallization, between one in one and described second conductor of each diode positioned vertical in described first conductor; Iv) a plurality of dielectric rupture antifuse that formed by the dielectric material that has greater than 8 dielectric constant; And v) a plurality of memory cells, each memory cell comprises one in one and the described dielectric rupture antifuse in the described diode of arranged in series; And b) is monolithically formed in the second memory level of described first memory level top.
One side more of the present invention provides a kind of device, and described device comprises: the connecting type p-i-n diode that comprises semi-conducting material; The silicide or the silicide-Germanide layer that contact with the semi-conducting material of described connecting type p-i-n diode; And comprise the dielectric rupture antifuse of dielectric material, and described dielectric material has 8 or bigger dielectric constant, and wherein said connecting type p-i-n diode and described dielectric rupture antifuse electricity in series are arranged between first conductor and second conductor.
Another aspect of the present invention provides a kind of and is used to form and the method for programming nonvolatile memory unit, and described method comprises: form connecting type p-i-n diode, described connecting type p-i-n diode comprises the semi-conducting material of deposition; Form the silicide, silicide-germanide or the Germanide layer that contact with the semi-conducting material of described deposition; Make the semi-conducting material crystallization of the described deposition that contacts with described silicide, silicide-germanide or Germanide layer; Formation has the dielectric materials layer greater than 8 dielectric constant; And making the part of described dielectric materials layer stand dielectric breakdown, wherein said memory cell comprises described connecting type p-i-n diode and described dielectric materials layer.
It is a kind of for the method that is monolithically formed the first memory level above substrate that additional aspect of the present invention provides, described method comprises: form roughly coplanar conductor of a plurality of first almost parallels above described substrate, described first conductor extends along first direction; Form the connecting type p-i-n diode of a plurality of vertical orientations above described first conductor, described connecting type p-i-n diode comprises with silicide, silicide-germanide or Germanide layer and contacts and the semi-conducting material of crystallization; Form roughly coplanar conductor of a plurality of second almost parallels, described second conductor is above described connecting type p-i-n diode, described second conductor extends along the second direction that is different from described first direction, between one in one and described second conductor of each connecting type p-i-n diode positioned vertical in described first conductor; And a plurality of dielectric rupture antifuse of formation, each dielectric rupture antifuse is placed between one in one and described first conductor in the described connecting type p-i-n diode or between one in one and described second conductor in the described connecting type p-i-n diode, wherein said dielectric rupture antifuse comprises dielectric material, and described dielectric material has the dielectric constant greater than about 8.
It is a kind of for the method that forms monolithic three dimensional memory array above substrate that the preferred embodiments of the present invention provide, described method comprises: a) be monolithically formed the first memory level above described substrate, described first memory level forms by the method that comprises following steps: i) form roughly coplanar conductor of a plurality of first almost parallels of extending along first direction; Ii) form roughly coplanar conductor of a plurality of second almost parallels of extending along the second direction that is different from described first direction, described second conductor is above described first conductor; Iii) form the connecting type p-i-n diode of a plurality of vertical orientations that formed by the semi-conducting material that deposits, the semi-conducting material of described deposition contacts and crystallization with silicide, silicide-germanide or Germanide layer, and each diode is arranged vertically between one in one and described second conductor in described first conductor; Iv) form a plurality of dielectric rupture antifuse that formed by the dielectric material that has greater than 8 dielectric constant; And v) forming a plurality of memory cells, each memory cell comprises one in one and the described dielectric rupture antifuse in the described diode of arranged in series; And b) above described first memory level, is monolithically formed the second memory level.
But each of the each aspect of the present invention of Miao Shuing and embodiment can be used or the use of combination with one another ground individually herein.
Now, these preferred aspect and embodiment are described with reference to the accompanying drawings.
Description of drawings
Fig. 1 is United States Patent (USP) the 6th, 952, the perspective view of No. 030 memory cell.
Fig. 2 is the perspective view that comprises the memory hierarchy of some memory cells.
Fig. 3 is circuit diagram, and it show to be used for the selected cell S of programming avoid simultaneously programming unintentionally the both half-selected unit H of crosspoint array and F and the bias scheme of the U of menu unit not.
Fig. 4 is circuit diagram, and it shows in crosspoint array at selected cell S, both half-selected unit H and F under the program voltage that reduces and the voltage on the U of menu unit not.
Fig. 5 is the sectional view of the memory cell that forms according to a preferred embodiment of the invention.
Fig. 6 is the sectional view according to the memory cell of alternate embodiment formation of the present invention.
Fig. 7 is the sectional view of the memory cell that another alternate embodiment forms according to the present invention.
Fig. 8 a-8c is the sectional view that is presented at each stage in the first memory level of the monolithic three dimensional memory array that formation forms according to a preferred embodiment of the invention.
Embodiment
Fig. 1 shows the United States Patent (USP) the 6th of people such as (Herner) in the Hull, 952, the embodiment of the memory cell of describing in No. 030 " density three-dimensional memory cell (High-density three-dimensional memory cell) " is called this patent ' 030 patent hereinafter.In this Nonvolatile memery unit, post 300 (comprising diode 302 and dielectric rupture antifuse 118) electricity in series is arranged between top conductor 400 and the bottom conductor 200.In the initial condition of this memory cell, when applying between top conductor 400 and bottom conductor 200 when reading voltage, minimum electric current flows between described top conductor 400 and described bottom conductor 200.Apply the memory cell that big relatively program current changes Fig. 1 enduringly, make after programming, read under the voltage more same that multiple current flows.Same this difference between current that reads under the voltage that applies allows and will distinguish through programming unit and programming unit not; For example, data " 0 " and data " 1 " are distinguished.
As in the Hull, waiting people in the U.S. patent application case the 10/955th of application on September 29th, 2004, in No. 549 " Nonvolatile memery units (Nonvolatile MemoryCell Without a Dielectric Antifuse Having High-and Low-Impedance States) that do not comprise the anti-fuse of dielectric with height and low impedance state " and hereinafter this patent application case is called ' 549 application cases, and the people is in the U.S. patent application case the 11/148th of application on June 8th, 2005 in the Hull etc., No. 530 " the Nonvolatile memery units of in polycrystalline semiconductor material, operating with ascending order (Nonvolatile Memory Cell Operating by Increasing Order in PolycrystallineSemiconductor Material ;) " and hereinafter this patent application case is called ' 530 application cases in the detailed description of (described two application cases are had by assignee of the present invention and are incorporated herein by reference), diode 302 is formed by the semi-conducting material that is in relative high resistivity state in first beginning and end programmer.Apply program voltage at diode 302 semi-conducting material is changed into the low resistivity state from high resistivity state.
In the unit of unit shown in similar Fig. 1, program voltage must be carried out two kinds of tasks.Described program voltage must be converted to low resistivity state from high resistivity state with the semi-conducting material of diode 302, and also must cause the dielectric material experience dielectric breakdown of dielectric rupture antifuse 118, during dielectric breakdown, for good and all form and pass at least one conducting path of dielectric rupture antifuse 118.
Fig. 2 shows the part of first memory level of the unit of those unit be arranged in the similar Fig. 1 in the crosspoint array that comprises a plurality of memory cells.Each memory cell comprises the post 300 (it comprises the diode 302 shown in Fig. 1 and anti-fuse 118) between one in one and the bottom conductor 200 that is placed in the top conductor 400.Top conductor 400 extends above bottom conductor 200 and along different directions (preferably, perpendicular to bottom conductor 200).But self vertical stacking of two, three or more this type of memory hierarchy is to form monolithic three dimensional memory array.
Fig. 3 graphic extension can be used for programming bias scheme of the memory cell in the cross point memory array of cross point memory array shown in similar Fig. 2.Suppose the program voltage (Gong Ying voltage only is example) that selected cell S will stand 10 volts herein.To select bit line B0 and be set at 10 volts and selected word line W0 is set at 0 volt, put 10 volts thereby cross over selected cell S.For avoiding programming unit F (itself and selected cell S share bit lines B0) unintentionally, unselected word line W1 is set at 9 volts; Therefore unit F only stands 1 volt, and this is lower than the connection voltage of diode.Similarly, bit selecting line B1 is not set at 1 volt; Therefore unit H (itself and selected cell S shared word line W0) only stands 1 volt.The U of menu unit (its not with selected cell S shared word line or bit line) does not stand-8 volts.Note, in this reduced graph, only show not bit selecting line B1 and a unselected word line W1 only.In the reality, will exist many unselected word lines to reach not bit selecting line.Array with N bit line and M word line will comprise the U unit of N-1 F unit, a M-1 H unit and a myriad of (N-1) * (M-1).
Diode in each of described U unit is under the reverse bias when voltage is lower than the puncture voltage of described diode, thereby it is minimum that the electric current that flows through this element is dropped to.(diode is conduction current asymmetrically, thereby in one direction than conduction current more easily on other direction.Yet), will there be some reverse leakage current inevitably, and because the U unit of big quantity, therefore the reverse leakage current between programming selected haplophase can be wasted the electric power of significant quantity.During the selected cell S of programming, waste electric power similarly although the forward current on the H unit of having programmed and the F unit is little.High programming voltage itself is difficult to produce usually.For all these reasons, need make the value of the required electric pulse in the word-select memory unit of programming in this cross point memory array drop to minimum.
Feature sizes is can be by the minimal characteristic of photoetching process formation.Note, for the device (for example, transistor) of horizontal orientation, in general, along with feature sizes reduces, operate the required voltage of described device and also reduce.Yet, in the memory cell of Fig. 1, because the vertical orientation of memory cell, the therefore semi-conducting material of conversion diode and make anti-fuse break the value of required electric pulse not along with feature sizes reduces in general.
In ' 510 application cases, it is right that dielectric rupture antifuse and the semiconductor diode that is formed by semi-conducting material (for example, silicon) are made into, the low resistivity state the when semi-conducting material of wherein said diode is in its formation, and need not conversion.
The diode of ' 030 patent and ' 549 application cases forms by following steps: deposited semiconductor material, for example be in the silicon of amorphous state, then carry out thermal annealing so that the silicon crystallization forms polysilicon (polycrystalline silicon) or polysilicon (polysilicon) diode.Described in ' 530 application cases, the material that has high lattice mismatch with it with the amorphous silicon of described deposition only when the amorphous silicon of deposition (for example, silicon dioxide and titanium nitride) contact and during crystallization, polysilicon is formed with the crystal defect of high quantity, thereby causes it to become high resistivity.Apply programming pulse by this high defective polysilicon and change described polysilicon apparently, cause it to become low resistivity.
Yet, found that amorphous silicon when deposition contacts with suitable silicide (for example, titanium silicide or cobalt silicide) layer and during crystallization, the quality through silicon metal of gained is much higher, defective still less and has much lower resistivity.The spacing of lattice of titanium silicide or cobalt silicide is in close proximity to the spacing of lattice of silicon, and it is believed that amorphous silicon contacts with suitable silicide layer and during with favourable oriented crystallization, described silicide provides template for the crystal growth of silicon, thereby makes the formation of defective drop to minimum.Be different from and only be adjacent to the high defect silicon that high defect silicon has the material crystallization of high lattice mismatch with it, apply big electric pulse and can not change considerablely and contact with silicide layer and this low defective of crystallization, the resistivity of low-resistivity silicon.
By with dielectric rupture antifuse therewith low defective, that the low-resistivity diode is made into is right, can form program voltage only need be enough to memory cell that dielectric rupture antifuse is broken; Diode is by being low-resistivity in its initial condition and having need not to suffer high resistivity to form to the semi-conducting material of low-resistivity conversion.
In the embodiment of ' 510 application cases, will hang down defect diode and the dielectric rupture antifuse that is formed by conventional dielectric material (silicon dioxide) be made into right.Dielectric rupture antifuse in this device must be enough thick in to realize reliable insulation, therefore needs big relatively program voltage.Can reduce this program voltage by the thickness that reduces silicon dioxide antifuse.Yet, when silicon dioxide antifuse becomes thinner, the described anti-fuse easier defectiveness that becomes, this will allow undesired Leakage Current.
Normally heat growth of described silicon dioxide layer (it serves as anti-fuse).Can improve the quality of anti-fuse by anti-fuse is grown down at higher temperature (for example, 1000 degrees centigrade), and reduce defective.Yet high temperature has other shortcoming, causes undesired diffusion in the CMOS control circuit of dopant in diode and below being formed at memory hierarchy, thereby damages and may damage described device.
Material has characteristic dielectric constant k.The dielectric constant of material is described it as the behavior of insulator.Good insulator (for example, the silicon dioxide that forms in a usual manner) has 3.9 low-k.Vacuum be defined as having 1 minimum may dielectric constant.Many materials (for example, comprise HfO 2And Al 2O 3) be regarded as dielectric, but the dielectric constant that has is higher than the dielectric constant of silicon dioxide.
Higher-k material (for example, the HfO that serves as dielectric rupture antifuse 2Or Al 2O 3) layer can be thicker than lower-k material (for example, the silicon dioxide) layer that has the same electrical behavior in difference qualitatively not quite simultaneously.
The gloomy people such as (McPherson) of Mike's amber suffers dielectric breakdown having demonstrated material with high dielectric constant k among " dielectric breakdown of suggestion and the total relation between the dielectric constant (the Proposed universal relationship between dielectricbreakdown and dielectric constant) " of 2002 IEDM journal 633-636 pages or leaves under the electric field that relatively advanced low-k materials is low.Reason for having described in early days need reduce the program voltage in the memory array.In the present invention, diode that will the low defective deposited semiconductor material of crystallization forms by being adjacent to silicide with by have the dielectric rupture antifuse that height-the k material forms greater than about 8 dielectric constant k be made into right.Term " semi-conducting material of deposition " refers to the semi-conducting material (for example, silicon, germanium or silicon-germanium alloy) that deposited, and gets rid of the monocrystalline wafer substrate that can construct described device on it.The required voltage of programming unit only is to make the described anti-fuse required voltage that breaks by making anti-fuse stand dielectric breakdown.The anti-fuse that forms height-k material is for reducing program voltage in the anti-fuse of keeping high reliability before programming with low current leakage after programming.
Note, height-k dielectric material has been carried out research for using in transistorized gate oxide, because height-comparable gate oxide of k dielectric material (that is silicon dioxide) is made to such an extent that thinlyyer have identical or better electric capacity simultaneously.Yet these gate oxide play the effect that is different from anti-fuse described herein in transistor.Experience dielectric breakdown when not planning to make any point of these gate oxide in the life-span of described device.
In a preferred embodiment, use ald (ALD) to form the dielectric rupture antifuse of height-k material.Height-k material layer that the progress that the ALD technology obtains has recently allowed to form as thin as a wafer and quality is high, for example, 50,30,20 or 10 dusts or still less.This thin layer has high quality like this and makes leakage current at acceptable low degree, and this thin layer needs lower puncture voltage.
The gloomy people of grade of Mike's amber describes has following additional advantage than high-k dielectric: described high-k dielectric often represents the more uniform puncture behavior of lower-k dielectric (for example, silicon dioxide).When the dielectric rupture antifuse of memory array is crossed over the program voltage of wide region and when breaking, described program voltage enough height so that anti-fuse high-end the breaking of distribution, even low voltage will satisfy the most memory cells in the array.Distribute more closely and allow further to reduce program voltage.
Many high-k dielectrics can form under low relatively temperature by various depositing operations (comprising ALD).In general, it is always favourable to making complex semiconductor device to reduce treatment temperature, minimum because this can make dopant spread, peel off etc. to drop to.
Diode is conduction current asymmetrically, thus ratio easier conduction under reverse bias under forward bias.Reverse leakage current, namely the electric current in the reverse bias current downflow is unwanted.Superlinearity ground reduces reverse leakage current along with the negative voltage that reduces on the diode.For example, as in the present invention, in the diode with the 0.15 micron feature sizes that is formed by the low resistivity semiconductor material, when diode-7 volts of following times, reverse leakage current is-7.5 * 10 -11Peace.When voltage was-5.5 volts, reverse leakage current roughly was reduced to-3.0 * 10 -11Peace.Under-4.5 volts of voltages, reverse leakage current is reduced to 1.6 * 10 -11The A peace.In the crosspoint array, the selected required low voltage of cell S of recovering programming can be crossed over the not low negative voltage of the U of menu unit generation, for example, translates into Fig. 4, supposes that the program voltage on the selected cell S only is required to be 5.4 volts depicted in figure 2.Be that the voltage on the selected bit line B0 is 5 volts under 5.4 volts the situation crossing over selected cell S, selected word line W0 is in 0 volt.If bit selecting line B1 is not set at 1 volt and unselected word line W1 and is set at 4.4 volts, unit H and F all stand 1 volt so.The U of menu unit does not stand-3.4 volts, and this is markedly inferior in the example of Fig. 3-8 volts.
In described monolithic memory arrays so so far, in general preferably use silicon to form diode.Germanium has the band gap littler than silicon, and has found that the diode that the alloy by silicon and germanium forms has the reverse leakage current higher than pure silicon diode.Leakage current increases along with the umber of germanium.In cross point memory array, because the U of menu unit only is not in-3.4 volts, so leakage current will be obviously lower, thereby alleviate this shortcoming.As in the Hull, waiting people in the U.S. patent application case 11/125 of application on May 9th, 2005,606 " the high-density nonvolatile memory arrays that comprise semiconductor diode of Zhi Zuoing (High-Density Nonvolatile Memory Array Fabricated at LowTemperature Comprising Semiconductor Diodes ;) at low temperatures " described in, this application case is had by assignee of the present invention and is incorporated herein by reference and is called below ' 606 application cases, with the conventional method depositing silicon and make the required temperature of its crystallization usually not with aluminium and copper metallization (its not tolerable high temperature) compatibility.So described in the application case, use the silicon-germanium diode with sufficient high Ge content that total making temperature is reduced, thereby allow to use these low resistivity metal, improve device performance.
Fig. 5 shows the memory cell that forms according to a preferred embodiment of the invention.Bottom conductor 200 comprises the adhesion layer 104 that is preferably titanium nitride and the conducting shell 106 that is preferably tungsten.Be formed at bottom conductor 200 tops by the dielectric rupture antifuse 118 that height-the k dielectric material forms.For example be that the barrier layer 110 of titanium nitride is between the connecting type p-i-n of dielectric rupture antifuse 118 and vertical orientation diode 302.In certain embodiments, can omit layer 110.Post 300 comprises barrier layer 110 and diode 302.Silicide layer 122 (being preferably cobalt silicide or titanium silicide) is the part of top conductor 400, and top conductor 400 further comprises for example conducting shell of titanium nitride layer 404 and tungsten layer 406.(as seeing, silicide only is formed on silicide formation metal and contacts part with the silicon of diode 302; The part that is decorated with cross-hauling of layer 122 is unreacted metal, but not silicide.) top conductor 400 (it is shown as and post 300 misalignment a little of underliing) is preferably trade shape, show with the section form that extends map sheet.Comprise HfO for the preferred material that in anti-fuse 118, uses 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and ZrSiAlON.The silicon of diode 302 is preferably with deposited amorphous, and then makes its crystallization.In certain embodiments, make diode 302 crystallizations, then peel off silicide 122 so that do not exist silicide preferred in the resulting device.Can there be some additional layer (not shown)s, for example, barrier layer and adhesion layer; Another selection is to omit some included barrier layers in certain embodiments.
Fig. 6 shows alternate embodiment.Form among the embodiment of bottom conductor 200 as Fig. 5.Post 300 comprises dielectric rupture antifuse 118 and the conductive barrier layer 125 that barrier layer 110 (being preferably titanium nitride), connecting type p-i-n diode 302, silicide layer 122, conductive barrier layer 123, height-k dielectric material form.Top conductor 400 comprises conductive adhesion layer 404 (being preferably titanium nitride) and conducting shell 406 (for example, tungsten).
Fig. 7 shows another alternate embodiment.Form among the embodiment of bottom conductor 200 as Fig. 5 and 6.Post 300 comprises barrier layer 110 (being preferably titanium nitride) and connecting type p-i-n diode 302.Short column 304 (forming from post 300 etchings with different etching steps) comprises silicide layer 122 and conductive barrier layer 123.Top conductor 400 comprises conductive adhesion layer 402 (being preferably titanium nitride) and conducting shell 406 (for example, tungsten).The dielectric rupture antifuse 118 that height-k dielectric material forms is between top conductor 400 and conductive barrier layer 123.Dielectric rupture antifuse 118 can be that continuous blanket covers thing, or can be with top conductor 400 patternings, as shown in the figure.Can dream up many other alternate embodiments that comprise connecting type p-i-n diode and height-k dielectric rupture antifuse similarly.
Each of these embodiment all is the semiconductor devices that comprise the following: by the connecting type p-i-n diode that the semi-conducting material that deposits forms, wherein said semi-conducting material has been adjacent to silicide, germanide or silicide-Germanide layer and crystallization; And with the dielectric rupture antifuse of described diode electrically arranged in series, described dielectric rupture antifuse comprises the dielectric material that has greater than 8 dielectric constant.In each embodiment, the diode of vertical orientation all is placed between bottom conductor and the top conductor, and dielectric rupture antifuse all is placed between diode and the top conductor or between diode and the bottom conductor.In these examples, no matter top conductor still is bottom conductor does not all comprise silicon layer.
Term " connecting type p-i-n diode " is described by what semi-conducting material formed at one end to have heavy doping p-type semi-conducting material and has the diode of heavy doping n-type semi-conducting material at the other end, between p-type district and n-type district, have the lightly doped semi-conducting material of intrinsic-OR, but the dielectric rupture antifuse that between p-type district and n-type district, before it breaks, is enough to prevent that most electric currents from flowing.The p-i-n diode is preferably for using in the large memories array, because this diode can make the leakage current under the reverse bias drop to minimum.
In in these unit any one, before programming, anti-fuse 118 is intact and stops electric current to flow.During programming, when supply program voltage between top conductor 400 and bottom conductor 200, the part of dielectric rupture antifuse experience dielectric breakdown, thus the conducting path of dielectric rupture antifuse 118 passed in formation between connecting type p-i-n diode 302 and the top conductor 400 or between connecting type p-i-n diode 302 and bottom conductor 200.
In an embodiment of the present invention, preferably can will be placed in by the dielectric rupture antifuse that height-the k dielectric material forms between two metals or the metallic layers (for example, titanium nitride or conductive metal silicide).These conducting shells help to cross over anti-fuse and set up electric capacity, thus allow anti-fuse than be placed between the semiconductor layer at anti-fuse or semiconductor layer and metal or metallic layers between situation under more easily break.
Detailed example with the monolithic three dimensional memory array that provides formation to form according to a preferred embodiment of the invention.For complete purpose, will provide specific process conditions, size, method and material.Yet, should be appreciated that this type of details does not plan to become restrictive, and can revise, omit or enlarge the many details in these details, and the result still belongs within the scope of the present invention.For example, from ' 030 patent, ' 549, ' 530 some details that reach ' 510 application cases can be useful.For avoiding that the present invention is thickened, the present invention will not included from all details of described patent and these application cases, does not plan to get rid of relevant teaching but will understand.
Example
Translate into Fig. 8 a, the formation of memory starts from substrate 100.This substrate 100 can be any semiconductive substrates known in this technology, for example, epitaxial loayer or any other semiconductive material on monocrystalline silicon, IV-IV compound (for example, silicon-germanium or silicon-germanium-carbon), III-V compound, II-VII compound, this type of substrate.Described substrate can comprise the integrated circuit that is manufactured in wherein.
Above substrate 100, form insulating barrier 102.Insulating barrier 102 can be silica, silicon nitride, Si-C-O-H film, or arbitrary other suitable insulation material.
Above substrate 100 and insulator 102, form first conductor 200.Can comprise between insulating barrier 102 and the conducting shell 106 that adhesion layer 104 is to help that conducting shell 106 is adhered to insulating barrier 102.If on cover conducting shell 106 and be tungsten, so preferably use titanium nitride as adhesion layer 104.Conducting shell 106 can comprise any conductive material known in this technology, and for example, tungsten or other material comprise tantalum, titanium, copper, cobalt or its alloy.
In case deposited all layers that will form conductor rail, will use any suitable shelter and etch process comes patterning and the described layer of etching so, with formation as among Fig. 8 a with the coplanar conductor 200 roughly of the almost parallel shown in the section form.Conductor 200 extends map sheet.In one embodiment, deposition is also passed through the lithographic patterning photoresist, and the described layer of etching, and then uses standard process techniques to remove described photoresist.
Next, on the conductor rail 200 and between deposition of dielectric materials 108.Dielectric material 108 can be any known electrical insulating material, for example silica, silicon nitride or silicon oxynitride.In a preferred embodiment, will be used as dielectric material 108 by the silicon dioxide of high-density plasma method deposition.
At last, remove the excess dielectric material 108 on conductor rail 200 tops, expose the top of the conductor rail 200 that is separated by dielectric material 108, and stay the general plane surface.Resulting structures is shown among Fig. 8 a.Can remove to form plane surface by what any technology known in this technology (for example, chemical-mechanical planarization (CMP) or eat-back) carried out that this dielectric crosses filler.In alternate embodiment, conductor 200 can change into by method for embedding and forming.
Translate into Fig. 8 b, next form the thin layer 118 have greater than height-k dielectric material of about 8 dielectric constant k.(for simplicity's sake, from Fig. 8 b and configuration subsequently, omit substrate 100, but will suppose its existence.) value of dielectric constant k of this material is preferably between 8 and 50, most preferably between about 8 and about 25.This layer preferably about 10 and about 200 dusts between, for example, about 20 and about 100 dusts between.The preferred material of layer 118 comprises HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and ZrSiAlON.In certain embodiments, can mix two or more material in these materials.Most preferred material comprises HfO 2(it has about 25 dielectric constant) or Al 2O 3(it has about 9 dielectric constant).In a preferred embodiment, layer 118 forms by ALD, to form the film of very high-quality.Preferably, high-quality film is fine and close (as far as possible near its solid density); Has the complete covering that does not almost have pin hole; Has low-density electric defective.In general, to be thicker than the material that has than low-k will be preferred to the material that makes on film quality difference very much not have high dielectric constant.For example, the Al that forms by ALD 2O 3Film preferably have about 5 and about 80 dusts between, the thickness of about 30 dusts preferably, and the HfO that forms by ALD 2Film preferably have about 5 and about 100 dusts between, the thickness of about 40 dusts preferably.Layer 118 will serve as dielectric rupture antifuse.In certain embodiments, deposit conductive barrier layer (not shown) can be preferred before sedimentary deposit 118.This barrier layer (for example, the titanium nitride of about 100 dusts) will provide uniform outer surface, deposit height-k dielectric rupture antifuse layer 118 at described uniform outer surface, and this can improve the uniformity of described height-k dielectric rupture antifuse layer.
Barrier layer 111 is deposited on the layer 118.Described barrier layer can be have any suitable thickness () any suitable conduction block material for example, 50 to 200 dusts, preferably 100 dusts, for example, titanium nitride.In certain embodiments, can omit barrier layer 111.
Next, deposition will be patterned into the semi-conducting material of some posts.Described semi-conducting material can be silicon, germanium, silicon-germanium alloy or other semiconductor or semiconducting alloy that is fit to.For simplicity's sake, this explanation is called silicon with semi-conducting material, but should be appreciated that, the those skilled in the art can change any material in the suitable material of selection these other into.
Can form bottom heavily doped region 112 by any deposition known in this technology and doping method.But depositing silicon and then to its doping, but preferably by during depositing silicon, making the donor gas that n type dopant atom (for example phosphorus) is provided flow in-situ doped described silicon.Heavily doped region 112 preferably about 100 and about 800 dusts thick between.
Then, can form intrinsic region 114 by any method known in this technology.District 114 can be any alloy of silicon, germanium or silicon or germanium and have about 1100 and about 3300 dusts between, the thickness of about 2000 dusts preferably.The silicon of heavily doped region 112 and intrinsic region 114 is preferably unbodied when deposition.
The semiconductor region 114 that has just deposited and 112 will be patterned and be etched with formation post 300 together with the barrier layer 111 of underliing, height-k dielectric layer 118 and barrier layer 110.Post 300 should have the spacing peace treaty identical width identical approximately with the conductor 200 of below, so that each post 300 all is formed on the top of conductor 200.Some misalignment of tolerable.
Can use arbitrary suitable shelter and etch process forms post 300.For example, can deposit, use standard photolithography techniques patterning and etching photoresist, then remove described photoresist.Another selection is can have bottom antireflective coating (BARC) above it at the hard mask of stacked semiconductor layer top certain other material of formation (for example, silicon dioxide), then patterning and the described hard mask of etching.Similarly, can be with dielectric antireflective coatings (DARC) as hard mask.
Chen (Chen) on 5 December 2003 pending U.S. Application No. 10/728 436 number "with the use of alternating phase-shift internal non-print window photomask features (hotomask Features with Interior NonprintingWindow Using Alternating Phase Shifting)" or Chen (Chen) on April 1, 2004 pending U.S. application No. 10/815 312 number "with no window chrome non-printing phase shift photomask features (hotomask Featureswith Chromeless Nonprinting Phase Shifting Window)" in (the said two assignee of the present application has a cause of action and incorporated herein by reference) describes the photolithography technique can be advantageously used to perform the formation of a memory array according to the present invention, used in any of the photolithography step.
On the semiconductor column 300 and between deposition of dielectric materials 108, to fill the gap between the described semiconductor column.Dielectric material 108 can be any known electrical insulating material, for example silica, silicon nitride or silicon oxynitride.In a preferred embodiment, use silicon dioxide as insulating material.
Next, remove the dielectric material on post 300 tops, expose the top of the post 300 that is separated by dielectric material 108, and stay the general plane surface.This that can carry out that dielectric crosses filler by any technology known in this technology (for example, CMP or eat-back) removes.At CMP or after eat-backing, carry out ion and implant, to form heavy doping p-type top region 116.Described p-type dopant is preferably the boron of shallow implantation, wherein implant energy and for example be 2keV, and dosage is about 3x.10/cm.This implantation step is finished the formation of diode 302.Resulting structures is shown among Fig. 8 b.In the diode that has just formed, bottom heavily doped region 112 is the p-type for n-type top-heavy doped region 116; Significantly, can the reverse polarity of diode.
In a word, pile up by depositing semiconductor layers above first conductor 200; Form patterning and the described stacked semiconductor layer of etching with post 300 in single patterning step form post 300.After finishing device, connecting type p-i-n diode is placed in the described post.
Translate into Fig. 8 c, after cleaning had been formed on any native oxide on post 300 tops, deposition one deck 120 silicides formed metal, for example, titanium, cobalt, chromium, tantalum, platinum, nickel, niobium or palladium.Layer 120 is preferably titanium or cobalt; If layer 120 is titanium, so its thickness preferably about 10 and about 100 dusts between, about 20 dusts most preferably.The back of layer 120 is titanium nitride layers 404.Two layers 120 and 404 preferably about 20 and about 100 dusts between, about 50 dusts most preferably.Next, deposition one deck 406 conductive materials, for example, tungsten.With layer 406,404 and 120 patternings and be etched to the top conductor 400 of some trade shape, described top conductor 400 preferably extends along the direction perpendicular to bottom conductor 200.
Next, on the conductor 400 and between the deposition of dielectric materials (not shown).Described dielectric material can be any known electrical insulating material, for example, and silica, silicon nitride or silicon oxynitride.In a preferred embodiment, silica is used as this dielectric material.
The formation of first memory level has been described.Can above this first memory level, form some extra memory hierarchies to form monolithic three dimensional memory array.The array of just having described only is an example; And can otherwise change, for example, comprise any one of the memory cell shown in Fig. 6 and 7.
With reference to Figure 10 c, notice that the layer 120 that silicide forms metal contacts with the silicon of top-heavy doped region 116.During heating step subsequently, the metal of layer 120 will with a certain partial reaction of the silicon of heavily doped region 116, to form the silicide layer (not shown).This silicide layer forms being lower than to make under the required temperature of silicon crystallization, and formation will still be amorphous to a great extent in district 112,114 and 116 therefore the time.If silicon-germanium alloy is used for top-heavy doped region 116, can form the silicide-Germanide layer of cobalt silicide-germanium cobalt for example or titanium silicide-germanium titanium so.
Preferably, after forming all memory hierarchies, carry out single recrystallization annealing temperature so that diode 302 for example kept about 60 seconds and crystallization down at 750 degrees centigrade, though can when forming each memory hierarchy, anneal to it.The gained diode will be polycrystalline usually.Because the semi-conducting material of these diodes is with described semi-conducting material has good lattice coupling with it silicide or silicide-Germanide layer contacts and crystallization, so the semi-conducting material of diode 302 will be to hang down defective and low-resistivity.
If with HfO 2Be used for dielectric rupture antifuse 118, should be careful so treatment temperature is remained on HfO 2Crystallization temperature below, described crystallization temperature can be about 700 to about 800 degrees centigrade.Intact crystal HfO 2Antifuse layer has than amorphous HfO 2The leakage that layer is much higher.
In certain embodiments, can share conductor between memory hierarchy, that is, top conductor 400 will serve as the bottom conductor of next memory hierarchy.In other embodiments, above the first memory level of Fig. 8 c, form the interlevel dielectric (not shown), its surface is through complanation, and because therefore being configured in this and beginning on the interlevel dielectric of complanation of second memory level do not have shared conductor.
The present invention allows to reduce program voltage.In the embodiment of ' 030 patent, the program voltage that is enough to the unit of nearly all (for example, more than 99%) in the programmed array comprises that leap will programmed cells be at least 8 volts pulse.In an embodiment of the present invention, the similar array of just having described can reduce program voltage.For example, can come nearly all unit in the programmed array less than the programming pulse of about 8 volts (and in certain embodiments, with less than 6 volts or less than 4.0 volts).
In certain embodiments, when being in the reverse bias, diode applies programming pulse preferably.This can have the following advantages: reduce or eliminate the leakage of the not menu unit in the leap array; As the U.S. patent application case the 11/496th of applying on July 28th, 2006 storehouse agate people such as (Kumar), No. 986 " use comprises the method (Method For Using A Memory CellComprising Switchable Semiconductor Memory Element With Trimmable Resistance ;) of the memory cell with the switchable semiconductor memory component that can repair resistance " described in, described patent application case is had by assignee of the present invention and is incorporated herein by reference.
Monolithic three dimensional memory array is that a kind of wherein a plurality of memory hierarchies are formed at single substrate (for example, wafer) top and do not have the memory array of intermediate substrate.The some layers that form a memory hierarchy directly deposit or grow on some layers of existing one or more level.On the contrary, as the United States Patent (USP) the 5th in sharp enlightening (Leedy), 915, in No. 167 " three-D structure memory (Three dimensional structure memory) ", construct some stacked storages together by forming some memory hierarchies and described memory hierarchy self is attached at independent substrate.Can before engaging, make described substrate attenuation or it is removed from memory hierarchy, but because memory hierarchy is formed on the independent substrate at first, so this type of memory is not real monolithic three dimensional memory array.
The monolithic three dimensional memory array that is formed at the substrate top comprises at least: the first memory level, and it is formed at first of described substrate top and highly locates; And the second memory level, it is formed at described first highly different second and highly locates.In this multilayer level array, can above substrate, form the memory hierarchy of three, four, eight or any actual number.
Rui Digen people such as (Radigan) is in the U.S. patent application case the 11/444th of application on May 31st, 2006; No. 936 " in order to the hard mask of conduction (Conductive Hard Mask toProtect Patterned Features During Trench Etch ;) of the patterned feature of protection during the ditch trench etch " in described and be used to form the alternative method of wherein using mosaic-like structure to form the similar array of conductor, described patent application case is assigned with assignee of the present invention and is incorporated herein by reference whereby.Can change into and use people's such as Rui Digen method to form according to array of the present invention.
This paper has described detailed manufacture method, but also can use any other method that forms same structure and the result still belongs to scope of the present invention.
More than describe several forms only described in many forms that the present invention can take in detail.For this reason, this detailed description is intended as illustrative and the indefiniteness explanation.Scope of the present invention will only be defined by above claim (comprising the claim that all are equivalent).

Claims (44)

1. semiconductor device, it comprises:
By the connecting type p-i-n diode that the semi-conducting material that deposits forms, wherein said semi-conducting material has been adjacent to silicide, silicide-germanide or Germanide layer and crystallization; And
With the dielectric rupture antifuse of described diode electrically arranged in series, described dielectric rupture antifuse comprises the dielectric material that has greater than 8 dielectric constant;
Wherein said dielectric rupture antifuse is formed by a depositing operation, and its thickness is 50 dusts or still less, and is placed between first metallic layers and second metallic layers.
2. semiconductor device as claimed in claim 1, wherein said semi-conducting material is polycrystalline.
3. semiconductor device as claimed in claim 1, wherein said dielectric material is selected from by HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and the group that forms of ZrSiAlON.
4. semiconductor device as claimed in claim 3, wherein said dielectric material is HfO 2Or Al 2O 3
5. semiconductor device as claimed in claim 1, wherein said silicide, silicide-germanide or Germanide layer are a) titanium silicide, titanium silicide-germanium titanium or germanium titanium, perhaps b) cobalt silicide, cobalt silicide-germanium cobalt or germanium cobalt.
6. semiconductor device as claimed in claim 1, wherein said semi-conducting material comprises silicon, germanium and/or silicon-germanium alloy.
7. semiconductor device as claimed in claim 6, between the top conductor above wherein said connecting type p-i-n diode vertical orientation and the bottom conductor that is placed in described connecting type p-i-n diode below and the described connecting type p-i-n diode, and described dielectric rupture antifuse is placed between described connecting type p-i-n diode and the described top conductor or between described connecting type p-i-n diode and the described bottom conductor.
8. semiconductor device as claimed in claim 7, wherein said top conductor or described bottom conductor do not comprise silicon layer.
9. semiconductor device as claimed in claim 7, wherein said silicide, silicide-germanide or Germanide layer above the described connecting type p-i-n diode and described dielectric rupture antifuse below described connecting type p-i-n diode.
10. semiconductor device as claimed in claim 1, wherein said dielectric rupture antifuse are that 20 dusts are thick or still less.
11. semiconductor device as claimed in claim 1, wherein said dielectric rupture antifuse forms by ald.
12. semiconductor device as claimed in claim 7, the part of wherein said dielectric rupture antifuse has experienced dielectric breakdown, thereby passes the conducting path of described dielectric rupture antifuse forming between described connecting type p-i-n diode and the described top conductor or between described connecting type p-i-n diode and described bottom conductor.
13. semiconductor device as claimed in claim 7, wherein said bottom conductor, described connecting type p-i-n diode and described top conductor all are formed on the Semiconductor substrate top.
14. semiconductor device as claimed in claim 6, wherein said connecting type p-i-n diode is the cylindricality formula.
15. a first memory level, it comprises:
Be formed at the first a plurality of parallel and coplanar conductor of substrate top;
Be formed at the second a plurality of parallel and coplanar conductor of described first conductor top;
Comprise the connecting type p-i-n diode of a plurality of vertical orientations of semi-conducting material, described semi-conducting material is adjacent to silicide, silicide-germanide or Germanide layer and crystallization;
The a plurality of dielectric rupture antifuse that formed by the dielectric material that has greater than 8 dielectric constant,
In the wherein said dielectric rupture antifuse each is to be formed and thickness is 50 dusts or still less by a depositing operation, and is placed between first metallic layers and second metallic layers;
Each of wherein said connecting type p-i-n diode is placed between one in one in described first conductor and described second conductor, and
Each of wherein said dielectric rupture antifuse is placed between one between one in one in described first conductor and the described connecting type p-i-n diode or in one in described second conductor and the described connecting type p-i-n diode;
And a plurality of memory cells, each memory cell comprises one in one and the described dielectric rupture antifuse in the described connecting type p-i-n diode.
16. first memory level as claimed in claim 15, wherein said dielectric material is selected from by HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and the group that forms of ZrSiAlON.
17. first memory level as claimed in claim 15, wherein said semi-conducting material comprises silicon, germanium and/or silicon-germanium alloy.
18. first memory level as claimed in claim 15, wherein said dielectric rupture antifuse are placed in described connecting type p-i-n diode below.
19. first memory level as claimed in claim 15, wherein said dielectric rupture antifuse are placed in described connecting type p-i-n diode below and described silicide, silicide-germanide or Germanide layer are placed in described connecting type p-i-n diode top.
20. first memory level as claimed in claim 15, wherein the second memory level is monolithically formed in described first memory level top at least.
21. a monolithic three dimensional memory array that is formed at the substrate top, it comprises
A) be monolithically formed in the first memory level of described substrate top, described first memory level comprises:
I) along first direction a plurality of first conductors that extend, parallel and coplanar;
Ii) along the second direction that is different from described first direction a plurality of second conductors that extend, parallel and coplanar, described second conductor is above described first conductor;
Iii) by the connecting type p-i-n diode of a plurality of vertical orientations of forming of semi-conducting material of deposition, described semi-conducting material is adjacent to silicide, silicide-germanide or Germanide layer and crystallization, between one in one and described second conductor of each diode positioned vertical in described first conductor;
Iv) a plurality of dielectric rupture antifuse that formed by the dielectric material that has greater than 8 dielectric constant; In the wherein said dielectric rupture antifuse each is formed by a depositing operation, and its thickness is 50 dusts or still less, and is placed between first metallic layers and second metallic layers; And
V) a plurality of memory cells, each memory cell comprise one in one and the described dielectric rupture antifuse in the described diode of arranged in series; And
B) be monolithically formed in the second memory level of described first memory level top.
22. monolithic three dimensional memory array as claimed in claim 21, wherein said dielectric material is selected from by HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and the group that forms of ZrSiAlON.
23. one kind is used to form and the method for programming nonvolatile memory unit, described method comprises:
Form connecting type p-i-n diode, described connecting type p-i-n diode comprises the semi-conducting material of deposition;
Form the silicide, silicide-germanide or the Germanide layer that contact with the semi-conducting material of described deposition;
Make the semi-conducting material crystallization of the described deposition that contacts with described silicide, silicide-germanide or Germanide layer;
Formation has the dielectric materials layer greater than 8 dielectric constant; Wherein said dielectric materials layer is formed by a depositing operation, and its thickness is 50 dusts or still less, and is placed between first metallic layers and second metallic layers; And
Make the part of described dielectric materials layer stand dielectric breakdown,
Wherein said memory cell comprises described connecting type p-i-n diode and described dielectric materials layer.
24. method as claimed in claim 23 wherein deposits described dielectric materials layer by ald.
25. to be 20 dusts thick or still less for method as claimed in claim 23, wherein said dielectric materials layer.
26. method as claimed in claim 23 is wherein from by HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and the group that forms of ZrSiAlON in select described dielectric material.
27. method as claimed in claim 26, wherein said dielectric material are HfO 2Or Al 2O 3
28. method as claimed in claim 23, the semi-conducting material of wherein said deposition comprises silicon, germanium or silicon-germanium alloy.
29. method as claimed in claim 23, wherein said silicide, silicide-germanide or germanide are a) titanium silicide, titanium silicide-germanium titanium or germanium titanium, or b) cobalt silicide, cobalt silicide-germanium cobalt or germanium cobalt.
30. method as claimed in claim 23, wherein described connecting type p-i-n diode is placed between first conductor and second conductor, and wherein described dielectric materials layer is placed in a) between the described connecting type p-i-n diode and described first conductor or b) between described connecting type p-i-n diode and described second conductor.
31. method as claimed in claim 30 wherein realizes that by apply program voltage between described first conductor and described second conductor described described part that makes described dielectric materials layer stands the step of dielectric breakdown.
32. method as claimed in claim 31, wherein said program voltage are no more than 8 volts.
33. method as claimed in claim 30, wherein with described connecting type p-i-n diode vertical orientation, and positioned vertical is between described first conductor and between described second conductor, and wherein said second conductor is above described first conductor.
34. method as claimed in claim 33, the step of the described connecting type p-i-n of wherein said formation diode comprises:
Form described first conductor;
After the step of described first conductor of described formation, depositing semiconductor layers piles up above described first conductor;
In single patterning step with form patterning and the described stacked semiconductor layer of etching of post; And
After the step of described patterning and the described stacked semiconductor layer of etching, above described post, form described second conductor.
35. method as claimed in claim 23, the wherein described memory cell of programming during the described described part that makes described dielectric materials layer stands the step of dielectric breakdown.
36. method as claimed in claim 23, wherein said semi-conducting material is polycrystalline.
37. a method that is used for being monolithically formed the first memory level above substrate, described method comprises:
Form a plurality of first parallel and coplanar conductors above described substrate, described first conductor extends along first direction;
Form the connecting type p-i-n diode of a plurality of vertical orientations above described first conductor, described connecting type p-i-n diode comprises with silicide, silicide-germanide or Germanide layer and contacts and the semi-conducting material of crystallization;
Form a plurality of second parallel and coplanar conductors, described second conductor is above described connecting type p-i-n diode, described second conductor extends along the second direction that is different from described first direction, between one in one and described second conductor of each connecting type p-i-n diode positioned vertical in described first conductor; And
Form a plurality of dielectric rupture antifuse, each dielectric rupture antifuse is placed between one in one and described first conductor in the described connecting type p-i-n diode or between one in one and described second conductor in the described connecting type p-i-n diode
Wherein said dielectric rupture antifuse comprises dielectric material, and described dielectric material has the dielectric constant greater than 8; And each in the wherein said dielectric rupture antifuse is formed by a depositing operation, and its thickness is 50 dusts or still less, and is placed between first metallic layers and second metallic layers.
38. method as claimed in claim 37 is wherein from by HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and the group that forms of ZrSiAlON in select described dielectric material.
39. method as claimed in claim 37, wherein said semi-conducting material comprises silicon, germanium and/or silicon-germanium alloy.
40. method as claimed in claim 37 wherein a) is placed in described dielectric rupture antifuse described diode below and described silicide, silicide-germanide or Germanide layer be placed in described diode top.
41. method as claimed in claim 37, wherein said substrate comprises monocrystalline silicon.
42. method as claimed in claim 37 wherein is monolithically formed second memory level at least above described first memory level.
43. a method that is used for forming monolithic three dimensional memory array above substrate, described method comprises:
A) be monolithically formed the first memory level above described substrate, described first memory level forms by the method that comprises following steps:
I) form the first a plurality of parallel and coplanar conductor that extends along first direction;
Ii) form the second a plurality of parallel and coplanar conductor that extends along the second direction that is different from described first direction, described second conductor is above described first conductor;
Iii) form the connecting type p-i-n diode of a plurality of vertical orientations that formed by the semi-conducting material that deposits, the semi-conducting material of described deposition contacts and crystallization with silicide, silicide-germanide or Germanide layer, between one in one and described second conductor of each diode positioned vertical in described first conductor;
Iv) form a plurality of dielectric rupture antifuse that formed by the dielectric material that has greater than 8 dielectric constant; In the wherein said dielectric rupture antifuse each is formed by a depositing operation, and its thickness is 50 dusts or still less, and is placed between first metallic layers and second metallic layers; And
V) form a plurality of memory cells, each memory cell comprises one in one and the described dielectric rupture antifuse in the described diode of arranged in series; And
B) above described first memory level, be monolithically formed the second memory level.
44. method as claimed in claim 43 is wherein from by HfO 2, Al 2O 3, ZrO 2, TiO 2, La 2O 3, Ta 2O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO x, HfSiAlON, and the group that forms of ZrSiAlON in select described dielectric material.
CN200780042606XA 2006-11-15 2007-11-13 P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same Active CN101553925B (en)

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US11/560,283 US7682920B2 (en) 2003-12-03 2006-11-15 Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
US11/560,283 2006-11-15
US11/560,289 2006-11-15
US11/560,289 US8018024B2 (en) 2003-12-03 2006-11-15 P-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
PCT/US2007/023855 WO2008060543A2 (en) 2006-11-15 2007-11-13 P-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse and methods of forming the same

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