CN101529361B - Computer device power management system and method - Google Patents

Computer device power management system and method Download PDF

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Publication number
CN101529361B
CN101529361B CN2007800400430A CN200780040043A CN101529361B CN 101529361 B CN101529361 B CN 101529361B CN 2007800400430 A CN2007800400430 A CN 2007800400430A CN 200780040043 A CN200780040043 A CN 200780040043A CN 101529361 B CN101529361 B CN 101529361B
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processor
power
grade
power rating
timer
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CN101529361A (en
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T·P·索耶斯
D·M·巴洛
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Examine Vincent Zhi Cai management company
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Hewlett Packard Development Co LP
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The present invention discloses a computer device power management system comprises a controller configured to throttle a processor of a computer device responsive to an overcurrent condition associated with a power source powering the computer device, the controller configured to adjust a power state of the processor to at least one of a plurality of predetermined power states based on a level of the throttle.

Description

Computer device power management system and method
Technical field
The present invention relates generally to the computer device power management, relates more specifically to computer device power management system and method.
Background technology
Computer equipment generally is configured to battery and/or the power supply of interchange (AC) adapter.Think that battery and/or AC adapter supplied the power of particular level before reaching electric current restriction.If near and/or reach electric current restriction, the magnitude of current that the processor of computer equipment is slowed down and draws from power supply to reduce.Yet the deceleration of processor has adverse influence to the performance of computer equipment.In addition, the deceleration processor causes limited energy-conservation (for example, cause lower processor working frequency and certain energy-conservation although slow down, the operating voltage grade of processor maybe also in greatest level).
Summary of the invention
According to an aspect of the present invention, a kind of computer device power management system is provided, has comprised: be used for to the relevant overcurrent conditional response of power supply for computer equipment power supply, with the device of the processor deceleration of computer equipment; Be used for the power rating of processor being adjusted to one by one the device of at least one preset power state of a plurality of preset power states based on the grade of slowing down; And the device that is used for the quantity of the power state transition in the limiting processor predetermined time cycle.
According to another aspect of the present invention, a kind of computer device power management method is provided, has comprised: to the relevant overcurrent conditional response of power supply for computer equipment power supply, with the processor deceleration of computer equipment; Based on the grade of slowing down the power rating of processor is adjusted at least one the preset power state in a plurality of preset power states one by one; And the quantity of the power state transition in the limiting processor predetermined time cycle.
Description of drawings
In order more completely to understand the present invention and advantage thereof, with reference now to the following explanation relevant, in the accompanying drawings with accompanying drawing:
Fig. 1 is the schematic diagram that the embodiment of computer device power management system is shown;
Fig. 2 is the schematic diagram of embodiment that the controller circuitry of power management system is shown;
Fig. 3 is based on the exemplary sequential chart of the signal relevant with the controller circuitry of Fig. 2; And
Fig. 4 is the process flow diagram that the embodiment of computer device power management method is shown.
Embodiment
Through Fig. 1 to 4 with reference to accompanying drawing, can understand the preferred embodiments of the present invention and advantage thereof well, use identical Reference numeral for identical and corresponding part in the different accompanying drawings.
Fig. 1 is the schematic diagram that the embodiment of computer device power management system 10 is shown.In the embodiment shown in fig. 1, implementation system 10 in computer equipment 12.Computer equipment 12 can comprise the computer equipment of any kind with processor 14, for example, but is not limited to notebook computer or kneetop computer, personal digital assistant, flat computer, the perhaps portable or non-portable electric appts of other type.In the embodiment shown in fig. 1, computer equipment 12 is configured to exchanging (AC) adapter 20 and/or battery 22 power supplies.In Fig. 1, battery 22 is illustrated as internal cell.Yet, should be understood that battery 22 also can comprise external cell.Processor 14 can comprise general procedure platform or the processing platform relevant with the function of pattern generator/system or other type.
In the embodiment shown in fig. 1, system 10 comprises controller 30, the power that it is used to manage and/or control computer equipment 12 is drawn from adapter 20 and/or battery 22.Controller 30 can comprise hardware, software, firmware or their combination.For example; In the embodiment shown in fig. 1; Controller 30 comprises the logic 32 of the ordered list that can be executable instruction; This ordered list can embed use by instruction execution system, equipment or device or get in touch in any computer-readable medium of use instruction execution system, equipment or install computer-based system for example, comprise the system of processor, other system that maybe can from instruction execution system, equipment or device, get instruction and execute instruction with them.In the context of this document, " computer-readable medium " can be can comprise, store, transmit, propagate or transmit use by instruction execution system, equipment or device or get in touch any means of the program of use with them.Computer-readable medium can be, for example, but is not limited to electronics, magnetic, light, electromagnetism, infrared or semiconductor system, unit, or propagation medium.In the embodiment shown in fig. 1, controller 30 is illustrated as and is disposed in the basic input/output (BIOS) 40.Yet, should be understood that, can store and/or be provided with controller 30 with other mode.
In Fig. 1, processor 14 is configured to have a plurality of different power states, makes each power rating comprise to be used for the different predetermined work frequency of processor 14.For example in the embodiment shown in fig. 1, processor 14 is configured to have power rating P0 (marking with 50), power rating P1 (marking with 52), power rating P2 (marking with 54), up to power rating Pn (marking with 60).In this example; Power rating P0 representes the frequency of operation of processor 14 at its maximum or normal working frequency place; And the frequency of operation of that power rating P1 representes to successively decrease to each power rating among the Pn and predetermined processor 14 (for example; Power rating P1 has the frequency of operation less than P0, and power rating P2 has the frequency of operation less than P1, or the like).Yet, should be understood that, can use other mode to identify and/or arrange the power rating (for example, power rating P0 represent lowest power state and Pn representes the peak power state) of processor 14.In Fig. 1, controller 30 also comprises timer 34 (timer internal of for example preferably in firmware, implementing).Timer 34 is used to be limited in the quantity of the power rating change of carrying out on the inherent processor 14 of cycle scheduled time; Thereby prevent that power rating from changing generation too continually (this can have adverse effect to the performance of processor 14, and can cause the handling interrupt of overfrequency).Therefore, for example, in certain embodiments, timer 34 be used for the restricted number that the power rating of processor 14 changes be per second once; Yet, should be understood that, can use other timing scheme.
In operation, the magnitude of current drawn from adapter 20 and/or battery 22 of controller 30 monitoring and processor 14 slowed down (for example, when in specific power rating) reach their rated current restrictions separately to prevent adapter 20 and/or battery 22.For example, the overcurrent condition General Definition current class attempting to draw from adapter 20 and/or battery 22 when computer equipment 12 near and/or when reaching their separately rated current restrictions.Adapter 20 and/or battery 22 are configured to generate and/or send the analog current restricting signal that shows the overcurrent condition.Controller 30 is used to generate overcurrent protection (OCP) signal that is used for processor 14 decelerations from the analog current signal of adapter 20 and/or battery 22 receptions.For example, the OCP signal generally is width modulation (PWM) signal with fixed amplitude (for example, 3.3 volts).As it is used in the text; The time that " deceleration " of processor expression stops required number percent through the clock period property ground with processor 14 is lowered the operating rate or the frequency of processor 14; Thereby reduce the effective velocity or the frequency of processor 14, and correspondingly reduce from the quantity of power of adapter 20 and/or battery 22 absorptions.
Except the deceleration of processor 14, controller 30 is configured to automatically and/or dynamically to regulate based on the deceleration grade of processor 14 power rating of processor 14.For example, when the deceleration grade of the embodiment monitoring processor 14 of system 10 should carry out the increasing or decreasing to the power rating of processor 14 so that confirm.Therefore, for example, if the deceleration grade of processor 14 is increased to above predetermined threshold value, controller 30 power rating of processor 14 that automatically successively decreases, thus cause reducing from the power that adapter 20 and/or battery 22 are drawn.Correspondingly, along with the reduction of the deceleration grade of the reduction of the load on adapter 20 and/or the battery 22 and processor 14, controller 30 automatically increases progressively the power rating of processor 14.In general, the reduction of the power rating of processor 14 causes being used to the reduction of the voltage of processor 14 power supplies, thereby causes having practiced thrift significantly the power of drawing from adapter 20 and/or battery 22.
Fig. 2 is the schematic diagram of embodiment that the controller circuitry 70 of controller 30 is shown.In the embodiment shown in Figure 2, circuit 70 comprises the resistor R that forms voltage divider 72 1, R 2And R 3, this voltage divider 72 is used for importing by V respectively to comparer 74 and 76 UPPERAnd V LOWERTwo different reference that mark.In addition, circuit 70 comprises the low-pass filter 78 that is used for generating from the OCP signal average OCP signal (being designated as AVG_OCP), and this low-pass filter 78 comprises resistor R 4With capacitor C 1The mean deceleration grade (Fig. 1) of AVG_OCP signal indicating processor 14.In the embodiment shown in Figure 2, circuit 70 also comprises the resistor R of the input that is connected respectively to comparer 74 and 76 5And R 6, stride the resistor R that comparer 74 is connected with 76 respectively 7And R 8, and be connected comparer 74 and 76 output and the resistor R between the logic level voltage (for example, 3.3 volts) separately 9And R 10As shown in Figure 2, the output of comparer 74 is defined as increment signal (in Fig. 2, being shown " INC "), and the output of comparer 76 is defined as decrement signals (in Fig. 2, being shown " DEC ").
In operation, comparer 74 and 76 output be used to determine whether based on as the deceleration grade of the processor 14 that shown of average OCP signal come the power rating of increasing or decreasing processor 14 (Fig. 1).Through will understanding the operation of circuit 70 better with reference to Fig. 3, Fig. 3 is based on the exemplary embodiment of the sequential chart of the signal relevant with circuit shown in Figure 2 70.In the embodiment shown in fig. 3; The state that sequential chart illustrates the OCP signal (for example; 0 volt or 3.3 volts), AVG_OCP voltage of signals grade (for example; Between 0 volt and 3.3 volts), increment (I NC) and the state of decrement (DEC) signal, the power rating of processor 14, and the timer internal 34 of controller 30.
With reference to Fig. 2 and 3, as long as average OCP signal (AVG_OCP) is lower than fixed threshold (V UPPER), the output of comparer 74 (increment signal) is high (HI), and as long as average OCP signal (AVG_OCP) is higher than fixed threshold (V UPPER), comparer 74 is output as low (LO).In addition, as long as average OCP signal (AVG_OCP) is lower than fixed voltage threshold (V LOWER), the output of comparer 76 (decrement signals) is HI, and as long as average OCP signal (AVG_OCP) is higher than fixed voltage threshold (V LOWER), the output of comparer 76 (decrement signals) is LO.Therefore, with reference to Fig. 3, the T in the sequential position 1Locate or T in the sequential position 1Near, OCP signal indicating processor 14 (Fig. 1) is slowed down; Therefore, average OCP signal (AVG_OCP) begins to increase from about 0 volt, shows the deceleration grade of the increase of processor 14.As shown in Figure 3, because the AVG-OCP signal compares V UPPERAnd V LOWERThreshold value is all low, the T in the sequential position 1Place's increment and decrement signals are all in the HI state.
The T in the sequential position 2The place, the AVG-OCP signal is increased to V LOWEROn, thereby show the deceleration grade of the increase of processor 14 (Fig. 1), and to cause decrement signals be LO.Along with the increase of the deceleration grade of processor 14, T in the sequential position 3The place, the AVG_OCP signal is increased to V UPPEROn, be LO thereby cause increment signal.To increment and decrement signals all is the LO response, and controller 30 and/or BIOS 40 make the power rating of processor 14 be decremented to state P1 from state P0.Therefore, in the P1 power rating, not only the electric current from adapter 20 and/or battery 22 absorptions reduces, and the frequency of operation of processor 14 also reduces with the voltage that is used to processor 14 power supplies.
The T in the sequential position 4The place, the deceleration grade reduces, and makes the AVG_OCP signal be lower than V UPPERThereby causing increment signal is HI.The T in the sequential position 5The place, the further minimizing of the amount of deceleration of processor 14 causes the AVG_OCP signal to be reduced to V LOWERBelow, be HI thereby cause increment signal.In the embodiment shown in fig. 3, timer internal (for example, the timer 34 of Fig. 1) is used to determine whether the power rating of increasing or decreasing processor 14.For example, in certain embodiments, whenever the incremented of processor 14/when successively decreasing, start timer internal 34.After timer 34 expires, assessment increment and decrement signals.Therefore, after timer internal 34 expires, if increment and decrement signals all are HI, the incremented of processor 14, and if increment and decrement signals all be LO, the decremented of processor 14.Yet, if increment signal is HI and decrement signals is LO after timer internal 34 expires, do not carry out processor 14 power rating increase progressively or/successively decrease, up to increment and decrement signals all be HI or all be the moment of LO till.Therefore, with reference to Fig. 3, the T in the sequential position 3Place's initialization timer internal 34.The T in the sequential position 5The place, although increment and decrement signals all are HI, timer internal 34 does not also expire, thereby does not increase progressively the power rating of processor 14.The T in the sequential position 6The place, timer internal 34 expires, and because increment and decrement signals all are H I, controller 30 and/or BIOS 40 make the power rating of processor 14 be incremented to state P0 from state P1.
The T in the sequential position 7The place, timer 34 expires and increment and decrement signals all are LO, and this causes the power rating of processor 14 to be converted to P1 from P0.The T in the sequential position 8The place, timer internal 34 expires, and reappraise increment and decrement signals.The T in the sequential position 8The place is because increment and decrement signals remain LO (for example, because the AVG_OCP signal is kept above V LOWERAnd V UPPER), controller 30 and/or BIOS 40 make the power rating of processor 14 be decremented to power rating P2 once more from power rating P1.Should be understood that, if the AVG_OCP signal keeps below V in other timer 34 cycles LOWERAnd V UPPER(for example, increment and decrement signals all remain LO), after each timer cycle, the power rating of processor 14 successively decreases one by one, till reaching minimum power rating.
The T in the sequential position 9The place, timer 34 expires.Yet, because increment signal is H I and decrement signals is LO, do not carry out the incremented/decremented of processor 14, up to, like T in the sequential position 10Shown in, till increment and decrement signals all are HI, are incremented to power rating P1 at this moment processor 14 from power rating P2, and reinitialize timer 34.It is to be further understood that if the AVG_OCP signal keeps below V in other timer 34 cycles UPPERAnd V LOWER(for example, increment and decrement signals all remain HI), after each timer cycle, the power rating of processor 14 increases progressively one by one, till reaching P0.Therefore, if the AVG_OCP signal remains on V UPPERAnd V LOWERBetween the threshold value (for example, increment signal be HI and decrement signals is LO), the power rating of processor 14 remains unchanged.
In the embodiment shown in Fig. 1 and 2, the deceleration and the adjusting of the power rating of single processor have been described.Yet, should be understood that, can on a plurality of processing platforms, use said system 10 and method.For example, can be at graphic memory processor, graphics engine processor, or carry out together or independently in other processing platform and slow down and power state transition.In addition, in the embodiment shown in Figure 2, circuit 30 is configured to export two signals (that is, increment and decrement signals).Yet, should be understood that, can use other mode configuration circuit 30 (for example, output is used for the individual signals of increasing or decreasing processor power states).In addition, should be understood that the function of circuit 30 can all or at least in part be carried out by software/firmware.
Fig. 4 is the process flow diagram that the embodiment of computer device power management method is shown.This method begins at piece 400 places of inspection timer 34.At decision block 402 places, confirm whether timer 34 expires.If timer 34 has expired, method advances to decision block 404, confirms wherein whether increment and decrement signals all are HI.If increment and decrement signals all are HI, method advances to decision block 406, and wherein in its highest available grades (for example, P0) whether the power rating of definite processor 14.If also not in its highest ranking, method advances to piece 408 to the power rating of processor 14, wherein state of incremented of processor 14 or grade (for example, from P2 to P1).Method advances to piece 410, wherein initialization and/or startup timer 34.If the power rating of confirming processor 14 at decision block 406 places is not carried out power state adjustment in its highest ranking on processor 14, and method advances to piece 400, wherein reexamines and/or supervision timer 34.
Not all be HI if confirm increment and decrement signals at decision block 404 places, method advances to decision block 412, confirms wherein whether increment and decrement signals all are LO.If increment and decrement signals are not all to be LO, on processor 14, do not carry out power state adjustment, and method advances to piece 400, wherein reexamine and/or supervision timer 34.If confirm that at piece 412 places increment and decrement signals all are LO, method advances to decision block 414, confirms that wherein whether processor 14 is in its minimum available power state.If processor 14 is not carried out power state adjustment in its minimum available power state on processor 14, and method advances to piece 400, wherein reexamines and/or supervision timer 34.If confirm processor 14 at decision block 414 places also not in its minimum available power state, method advances to piece 416, wherein state of decremented of processor 14 or grade (for example, from P1 to P2).Method advances to piece 410, wherein initialization and/or otherwise start timer 34.
Therefore; In operation; Based on as average OCP signal show deceleration grade, the incremented of processor 14 or the power consumption of one or more grades of successively decreasing of the processor 14 of (increment of also exporting like comparer 74 and 76 and the HI or the LO condition of decrement signals show) with control computer equipment 12.Therefore, the embodiment of system 10 provides and utilizes deceleration and power state adjustment to control from the variable processor control of the power of adapter 20 and/or battery 22 absorptions.Should be understood that, in said method, possibly omit with the order that is different from order shown in Figure 4 and accomplish, the specific function of perhaps carrying out simultaneously.And, should be understood that, can change method shown in Figure 4, to contain of the present invention any further feature or the aspect of describing in other part in this manual.In addition, embodiment can implement in software, and can be suitable on different platforms and operating system, moving.

Claims (8)

1. a computer device power management system (10) comprising:
Be used for to be the relevant overcurrent conditional response of the power supply (20,22) of computer equipment (12) power supply, the device that the processor (14) of computer equipment (12) is slowed down;
Be used for the power rating of processor (14) being adjusted to one by one the device of at least one preset power state of a plurality of preset power states based on the grade of slowing down; And
The device that is used for the quantity of the power state transition in limiting processor (14) predetermined time cycle.
2. the system of claim 1 (10), it further comprises the device of the average overcurrent protection signal that is used to generate the grade that shows deceleration.
3. the system of claim 1 (10), the device that wherein is used for regulating comprises: if the grade that is used for slowing down is increased to the device that processor (14) is decremented to one by one at least one preset power state of said a plurality of preset power states above predetermined threshold.
4. the system of claim 1 (10), the wherein said device that is used to regulate comprises: the device that is used for after timer (34) expires, regulating the power rating of processor (14).
5. computer device power management method comprises:
To the overcurrent conditional response of being correlated with, with processor (14) deceleration of computer equipment (12) with the power supply (20,22) that is computer equipment (12) power supply;
Based on the grade of slowing down the power rating of processor (14) is adjusted at least one the preset power state in a plurality of preset power states one by one; And
The quantity of the power state transition in limiting processor (14) predetermined time cycle.
6. method as claimed in claim 5, it further comprises the average overcurrent protection signal that generates the grade that shows deceleration.
7. method as claimed in claim 5, wherein adjusting comprises: if the grade of slowing down is increased to above predetermined threshold, processor (14) is decremented at least one the preset power state in said a plurality of preset power state one by one.
8. method as claimed in claim 5, wherein adjusting comprises: the power rating of after timer (34) expires, regulating processor (14).
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US11/588,918 2006-10-27
US11/588,918 US7689851B2 (en) 2006-10-27 2006-10-27 Limiting power state changes to a processor of a computer device
PCT/US2007/021873 WO2008054618A2 (en) 2006-10-27 2007-10-11 Computer device power management system and method

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