CN101515294A - Method for hardware realization of SQL instruction - Google Patents

Abstract

The invention discloses a method for the hardware realization of SQL instruction. A SQL core is designed to execute the SQL instruction, the SQL core and a general processor are simultaneous present. The instruction set supported by the designed core includes create table, drop table, select, insert, update and delete, the realization of the above instructions is performed by a microinstruction way. Compared with the traditional software method, the method for the hardware realization of SQL instruction has higher execution efficiency because the SQL instruction is in customized optimization and realized by a special circuit. The SQL core has another characteristic that a plurality of SQL cores are arranged on a single chip and the parallelism is increased.

Description

The hardware implementation method of SQL instruction

Technical field

The present invention relates to database and architecture field, relate in particular to a kind of hardware implementation method of SQL instruction.

Background technology

Database technology has experienced less than the semicentennial time since being born, and has just formed solid theory, ripe commercial product and application fields, and the researcher constantly adds, and becomes one by the research field of extensive concern.Along with emerging in an endless stream of the continuous growth of the information content, new technology, database technology is faced with unprecedented challenge.

In the face of various data modes, people have proposed various data model (hierarchical model, network model, relational model, object oriented programming model, plate structure model etc.), have also proposed many new database technologys (XML data management, data stream management, Web data integration, data mining etc.).

Increase along with e-bank, E-government and Mobile business application, the mobile data that needs to handle also increases rapidly, in order to satisfy growing data processing demand and to make things convenient for application and development, also increasing to the demand of the toy data base management system on the mobile device.

In the various database technologys, database machine (knowledge base machine), memory database, SOC (system on a chip) (SoC) technology constitute the technical foundation of native system jointly.

Database machine (Database Machine), being a kind of computing machine with special-purpose purpose of English for the high-level data operating function that needs with the direct supporting database of hardware administrative institute, is that people are in order to improve the Database Systems performance and to support extensive high speed information to handle and a kind of special purpose computer of proposition.It is the product with research be combined intos such as database technology, VLSI technology and Computer Architectures.Database machine can be used as the fundamental mechanism or the basic module of knowledge base machine, thereby supports knowledge processing efficiently.Database machine research has formed a relatively independent technology-oriented discipline that is combined and formed by Computer Architecture and database technology already through ten years development.

Tradition based on the relational database system of disk (with Oracle, DB2 etc. are representative), hereinafter to be referred as DRDB (Disk-Resident Databases), because master data base disk resident, issued transaction often relates to the disk I operation, the optimization aim of its architecture Design is how to reduce the number of times of read-write disk, is difficult to satisfy the demand of following based on network application system to the high-performance data access ability.Memory database (MMDB:Main Memory Database) technology then provides a kind of solution of good real time data management for above-mentioned application.

The key distinction is between MMDB and the DRDB: MMDB master data base memory-resident, the optimization aim of architecture Design is to improve internal memory and CPU service efficiency, because issued transaction need not to carry out disk access, use the application system performance of MMDB to be greatly improved.Compare with DRDB, the advantage of MMDB is as follows: finish same function, required machine instruction reduces greatly; No longer need Buffer Manager, eliminated copying data expense extra between disk and the internal memory; In the organization and administration of data and index, be extensive use of pointer, simplified memory management, reduced memory cost.

Present often integrated many functional units on a chip, thus on single chip, form a complete system, such system be called SOC (system on a chip) (System on Chip, SoC).The method for designing of SoC can effectively reduce the complicacy that designs on the sheet.The multiprocessor SOC (system on a chip) (multiprocessor SoC MPSoC) is a kind of special SOC (system on a chip), has two or more processors exactly on a chip, certainly these processors can be isomorphism also can be isomery.Usually comprised some general processors in the multiprocessor SOC (system on a chip) and be used for the hardware module of dedicated computing with some.MPSoC has been applied in fields such as communication, multimedia and network widely now, and these fields require high-performance, low energy consumption and high flexibility usually.IBM Cell is typical case's representative of a heterogeneous multi-nucleus processor.

Summary of the invention

In order to adapt to increasing data access amount and more and more higher performance requirement to the existing database system, when improving database data access speed and concurrency, simplify the design of DBMS, the workload when alleviating general processor in database access, security when strengthening database access, the hardware implementation method that the object of the present invention is to provide a kind of database structure inquiry (SQL) to instruct.

The technical scheme that technical solution problem of the present invention is adopted is:

1) start-up course of SQL nuclear:

The startup of SQL nuclear is triggered by general processor, program run with database manipulation is on general processor, when general processor is carried out the SQL instruction, general processor transmission SQL instructs on the SQL nuclear, the resolution component that SQL nuclear at first instructs by SQL, SQL nuclear PC value is set instructs article one microinstruction address in the corresponding microinstruction sequence for this SQL, be provided with after the end of PC value, SQL nuclear begins to carry out the microinstruction sequence process for getting micro-order, deliver in the hardware logic parts and carry out, when the hardware logic parts are carried out the OVER micro-order, this SQL instruction is carried out and is finished;

2) SQL instruction set:

Comparing DBMS in the software fulfillment database carries out the explanation of SQL, have the basic SQL instruction set of a cover, comprise create table, drop table, select, insert, delete and update, for these 6 assembly instructions, be respectively them and designed order format, the parameter spread pattern, the access criteria of parameter, OPADD and form as a result as a result, these instructions are independently assembly instructions for the hardware realization system of SQL instruction, there is not constraint mutually between the instruction, the SQL instruction is come complete by SQL nuclear, SQL nuclear is the nuclear of an isomery customization;

3) the micro-order framework of SQL nuclear:

The method of micro-order has been adopted in the realization that SQL checks SQL instruction, i.e. SQL instruction meeting is broken down into the function that microinstruction sequence is finished the SQL instruction in isomery nuclear, these micro-orders are not examined outside finding or visit by SQL, for general processor, the interface that SQL nuclear offers it is exactly 6 basic SQL assembly instructions;

4) concurrent working of SQL nuclear and general processor:

In the process of general processor executive routine, when running into the SQL instruction, it sends to SQL nuclear with this SQL instruction, examine the operation of finishing database by SQL, in SQL nuclear executable operations, general processor moves the concurrency that other tasks increase general purpose core and isomery nuclear, when resources of chip is sufficient, a plurality of SQL nuclears are set at chip internal, can reach bigger database manipulation concurrency like this, the scheduling of SQL nuclear is simultaneously determined by general purpose core.

The useful effect that the present invention has is:

At first the present invention has improved the execution efficient of the operation of database.In traditional database access solution, the SQL instruction is transferred to DBMS and is handled, and after DBMS obtained the SQL instruction, instruction made an explanation and carries out to SQL, and it is high that the efficient of this mode is not directly carried out the SQL instruction by hardware.After simple SQL instruction was designed to assembly instruction, it was 6 basic SQL instructions that DBMS only need optimize and decompose complicated database manipulation.Secondly the present invention can effectively improve the concurrency between the database manipulation.When application program is carried out sequence of operations to database simultaneously, if DBMS judges these operations and does not have the conflict of data on concurrent, general processor just can be distributed to different operations different SQL nuclear so, can effectively improve concurrent to database access like this.The 3rd, the present invention can effectively alleviate the burden of general processor, increases handling capacity.Because this moment, general processor no longer needed to finish task to database manipulation, make like this general processor can be under the assistance of SQL nuclear concurrent more task, increase handling capacity.

Description of drawings

Accompanying drawing is the start-up course of SQL specific core.

Embodiment

At first come the registers group and the micro-order set of the specific core of place of matchmakers's design.In the specific core of design, have 35 registers, the length of each register is 32.In these 35 registers, general-purpose register has 24, is respectively R0-R23,11 of special registers, and name and function are as follows respectively:

IP-database operating instruction counter

PC-sub-instructions counter

RT-Table I D-table name mapping table base address

Id-domain name mapping table base address, RD-territory

RB-table id-address mapping table base address

RA-result stores the base address

TB-shows the base address

Rtid-Table I D

RL-table record length

RC-table record counter

The Flags-sign

In designed specific core, design 19 micro-orders altogether and finished the execution that 6 SQL instruct, the form of micro-order, operational code, function etc. are described below respectively:

* N is the storehouse instruction of whether fetching data; C is a carry; Whether F is for being to see Table instruction; Z is whether result of calculation is 0; Whether T is for shifting.

SID: form Sid src, flag

000000	src	flag
			6bit[31:26]	25bit[26:1]	1bit[0]

Function: look-up table ID, if there is no then export newly-generated Table I D.Operational code: 000000 operand: Src points to the base address of table name, 25; Flag represents one zone bit, and set is 1 when building table, otherwise is 0, and operand type is counted immediately.The register that changes: after carrying out end, find Table I D if build when showing, deposit special register Rtid in, zone bit FF is 0, otherwise FF is 1, the Table I D of special register for generating; In other whens instruction, finding Table I D, to put FF be 1, is 0 otherwise put FF; Zone bit F represents that this instruction is for building the table instruction.

ADD: form add rd, rs, rt

010000	rs	Rt	rd
					6[31:26]	5[25:21]	5[20:16]	5[15:11]	11[10:0]

Function: calculating two register interior elements does not have symbol shaping data sum.Operational code: 010000; Operand: rs, rt, rd, type is deposited type.The register that changes: the data in rs and two registers of rt are done the addition of no symbol shaping data, and the result is saved in the rd register.If carry is arranged, then putting zone bit C is 1, is 0 otherwise put C.Note: be used to calculate memory address, the 0-10 position of ignoring instruction is total to 11bits.

ADDI: form addi rd, rs, imm

010101	Rs	rd	Imm
				6	5	5	16

Function: counter register rs interior element and 16 additive operation sums of counting immediately.Operational code: 010101; Operand: rd, rs are register type; Imm is 16 and counts immediately.The register that changes: the data in the rs are done the shaping addition with counting imm immediately, itself and be saved in the rd register.If carry is arranged, then putting zone bit C is 1, is 0 otherwise put C.Note: if operation result is 0, then putting zone bit Z is 1, is 0 otherwise put z.

SUB: form sub rd, rs, rt

011000	Rs	Rt	Rd
					6	5	5	5	11

Function: calculate rt and two register interior elements of rs and do the poor of shaping subtraction.Operational code: 011000; Operand: rs, rt, rd is for depositing type.The register that changes: the data in rs and two registers of rt are done subtraction, and the result is saved in the rd register.If operation result is 0, then putting zone bit Z is 1, is 0 otherwise put z.Note: be used to calculate memory address, the 0-10 position of ignoring instruction is total to 11bits.

MUL: form mul rd, rs, rt

010100	Rs	rt	Rd
					6	5	5	5	11

Function: calculate rt, two register interior elements of rs shaping multiplication is long-pending.Operational code: 010100; Operand: rs, rt, rd is for depositing type.The register that changes: the data in rs and two registers of rt are done no symbol shaping data multiply each other, the result is saved in the rd register.Note: the 0-10 position of ignoring instruction is total to 11bits.

AND: form and rd, rs, rt

010001	Rs	rt	rd
					6	5	5	5	11

Function: the element in rt and two registers of rs is done position and computing.Operational code: 010001; Operand: rs, rt, rd is for depositing type.The register that changes: the data in rs and two registers of rt are done position and computing, and the result is saved in the rd register.Note: the 0-10 position of ignoring instruction is total to 11bits.

OR: form or rd, rs, rt

010011	rs	rt	rd
					6	5	5	5	11

Function: the element in rt and two registers of rs is done an exclusive disjunction.Operational code: 010011; Operand: rs, rt, rd is for depositing type.The register that changes: the data in rs and two registers of rt are done an exclusive disjunction, and the result is saved in the rd register.Note: the 0-10 position of ignoring instruction is total to 11bits.

MOV: form mov rd, rs

001000	rs	rd
				6	5	5	16

Function: the element in the rs register is copied in the rd register.Operational code: 001000; Operand: rs, rt, rd is for depositing type.The register that changes: the data in the rs register are copied in the rd register.Note: the 0-15 position of ignoring instruction is total to 16bits.

SL (SHIFT LEFT): form sl rd, rt, shamt

000010	rt	rd	shamt	Undefined
					6	5	5	5	11

Function: the element in the rt register is moved to left some, and the result is stored in the rd register.Operational code: 000010; Operand: rs, rt is for depositing type; Shamt, type constant.The register that changes: binary data in the rt register is moved to left, the constant decision that the figure place that moves to left is provided by shamt, result calculated is stored in the rd register.Note: the 0-10 position of ignoring instruction is total to 11bits.

SH (SHIFT RIGHT): form sr rd, rt, shamt

000011	rt	rd	shamt	Undefined
					6	5	5	5	11

Function: the element in the rt register is moved to right some, and the result is stored in the rd register.Operational code: 000011; Operand: rs, rt is for depositing type; Shamt, type constant.The register that changes: binary data in the rt register is moved to right, the constant decision that the figure place that moves to right is provided by shamt, result calculated is stored in the rd register.Note: the 0-10 position of ignoring instruction is total to 11bits.

LOAD: form ld rs, rt, offset

110000	rs	rt	offset
				6	5	5	16

Function:, calculate the memory address that needs loading with several immediately additions of address in the rs register and offset.Operational code: 110000; Operand: rs, rt is for depositing type; Offset is for counting immediately.The register that changes: count additions immediately with what binary address and offset in the rs register provided, calculating the address, be stored in the rt register, use for processor.

LI (LOAD IMMEDIATE): form li rd, imm

111000	Rd	imm
			6	5	21

Function: the data that imm is represented copy in the register rd, the memory address that need load as processor.Operational code: 111000; Operand: rs is for depositing type; Imm is for counting immediately.The register that changes: the number immediately of imm representative is copied in the register rd.The number immediately of note: imm representative can only be represented 21 bit address.

LFP (LOAD FROM PARAMEM): form lfp rs, rt, offset

111100	rs	rt	offset
				6	5	5	16

Function: read in rs for base address offset be that the data of side-play amount are in rd register pointed.Operational code: 111100; Operand: rs, rd are register type; Offset is for counting type immediately;

ST (STORE): form st rs, rt, offset

101000	rs	Rt	offset
				6	5	5	16

Function: with several immediately additions of data in the rs register and offset, the data in the storage rt are to the memory address that calculates gained.Operational code: 101000; Operand: rs, rt is for depositing type; Offset, type imm.The register that changes: reading of data in rt and two registers of rs only, saving result not have the register of change in internal memory.

STR (STORE TO RESULT): form str rs, rt, offset

101100	Rs	Rt	Offset
				6	5	5	16

Function: it is in the address of side-play amount that rd content of registers pointed is stored in rs to base address offset.Operational code: 101100; Data type is the same with the LFP instruction.

BEQ: form beq rs, rt, label

000100	rs	Rt	Label
				6	6	6	16

Function: judge whether data equate in rs and the rt, if rt=rs, the instruction that then jumps to the label sensing continues to carry out.Operational code: 000100; Operand: rs, rt is for depositing type; Label is for counting immediately.The register that changes: reading of data in rt and two registers of rs, the result is saved among the PC, carries out as next bar instruction.Note: during redirect, establishing zone bit T is 1, otherwise is made as 0.Maximum 16 of jump address.

BNE: form bne rs, rt, label

000101	rs	rt	label
				6	6	6	16

Function: judge whether data equate in rs and the rt, if rt!=rs then jumps to the instruction continuation execution that label points to.Operational code: 000101; Operand: rs, rt is for depositing type; Label is for counting immediately.The register that changes: reading of data in rt and two registers of rs, the result is saved among the PC, carries out as next bar instruction.Note: during redirect, establishing zone bit T is 1, otherwise is made as 0.Maximum 16 of jump address

JMP: form jmp label

000110	label
		6	26

Function: unconditional jump instruction.Operational code: 000101: operand: label is for counting immediately.The register that changes: directly, be saved among the PC, carry out as next bar instruction with the memory address of label representative.Note: during redirect, establishing zone bit T is 1.Maximum 26 of jump address.

CMP: form cmp rs, rt

000111	rs	rt	undefined
				6	5	5	16

Function: judge whether data equate in rs and the rt.Operational code: 000111; Operand: rs, rt is for depositing type.The register that changes: do not change buffer status, the data in rs and the rt are subtracted, if the result is 0, then putting zone bit Z is 1, is 0 otherwise put z.Note: the 0-15 position of ignoring instruction is total to 16bit.

OVER: form over

111111	undefined
		6	26

Function: the instruction of terminator program.Operational code: 111111; Operand: do not have.The register that changes: do not change buffer status, directly stop the operation of present procedure.Note: the 0-25 position of ignoring instruction is total to 26bit.

For 6 SQL instructions, be respectively them and designed the microinstruction sequence of carrying out.During these microinstruction sequences are stored and store on non-volatile.For every SQL instruction, all there is a unique microinstruction sequence entry address corresponding with it.In designed specific core, the program counter register PC of specific core can be set up, and general processor is exactly to start specific core by the PC value that specific core is set.Every the SQL instruction finishes with the OVER micro-order, is used for showing that this SQL task is done.The start-up course of specific core as shown in drawings.

When running into a SQL instruction in the process that general processor is only carried out, general processor can instruct out this SQL and see off, resolution unit receives the PC value that this SQL instruction can be provided with specific core later on according to the content of instruction, if at this moment specific core is in busy condition, the SQL of general processor needs to wait for so.After setting up PC, specific core can be taken out micro-order according to the PC value and be carried out from microinstruction sequence, and implementation is known always and run into till the OVER micro-order.Run into the OVER micro-order and illustrated that current SQL instruction is complete, specific core changes idle condition over to.

Claims (1)

1. the hardware implementation method of SQL instruction is characterized in that:

1) start-up course of SQL nuclear:

The startup of SQL nuclear is triggered by general processor, and the program run with database manipulation is on general processor, and when general processor was carried out the SQL instruction, general processor transmission SQL instructed on the SQL nuclear.SQL nuclear is at first by the resolution component of SQL instruction, SQL nuclear PC value is set instructs article one microinstruction address in the corresponding microinstruction sequence for this SQL.After the PC value is set finishes, SQL nuclear begins to carry out the microinstruction sequence process for getting micro-order, delivers in the hardware logic parts and carries out, and when the hardware logic parts are carried out the OVER micro-order, end is carried out in this SQL instruction;

2) SQL instruction set:

Compare DBMS in the software fulfillment database explanation of SQL is carried out, have the basic SQL instruction set of a cover, comprise create table, drop table, select, insert, delete and update.For these 6 assembly instructions, be respectively them and designed the access criteria of order format, parameter spread pattern, parameter, OPADD and form as a result as a result, these instructions are independently assembly instructions for the hardware realization system of SQL instruction, there is not constraint mutually between the instruction, the SQL instruction is come complete by SQL nuclear, SQL nuclear is the nuclear of an isomery customization;

3) the micro-order framework of SQL nuclear:

The method of micro-order has been adopted in the realization that SQL checks SQL instruction, i.e. SQL instruction meeting is broken down into the function that microinstruction sequence is finished the SQL instruction in isomery nuclear, these micro-orders are not examined outside finding or visit by SQL, for general processor, the interface that SQL nuclear offers it is exactly 6 basic SQL assembly instructions;

4) concurrent working of SQL nuclear and general processor:

In the process of general processor executive routine, when running into the SQL instruction, it sends to SQL nuclear with this SQL instruction, examine the operation of finishing database by SQL, in SQL nuclear executable operations, general processor moves the concurrency that other tasks increase general purpose core and isomery nuclear, when resources of chip is sufficient, a plurality of SQL nuclears are set at chip internal, can reach bigger database manipulation concurrency like this, the scheduling of SQL nuclear is simultaneously determined by general purpose core.

Images