CN101505186B - Multi-mode high-speed modem - Google Patents
Multi-mode high-speed modem Download PDFInfo
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- CN101505186B CN101505186B CN200910073964A CN200910073964A CN101505186B CN 101505186 B CN101505186 B CN 101505186B CN 200910073964 A CN200910073964 A CN 200910073964A CN 200910073964 A CN200910073964 A CN 200910073964A CN 101505186 B CN101505186 B CN 101505186B
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Abstract
The invention relates to a modem in the field of new-generation broadband communication satellites, in particular to a multi-mode high-speed modem. The multi-mode high-speed modem, under the control support of a main control program, comprises a modulation baseband board (2), a modulation intermediate frequency board (3), a demodulation intermediate frequency board (4), a modulation baseband board (5), a main control unit (6), a CPCI bus board (1) and a power supply (8). The technical proposal has the functions of dynamical program loading, error code test, and the displaying of frequency spectrums and constellation diagrams of key nodes based on improving the transmission efficiency of satellite communication systems and enhancing the university and flexibility of satellite communication terminals.
Description
Technical field
The present invention relates to a kind of modulator-demodulator in new generation broadband communication satellite field, especially a kind of high speed modem with multi-modulation scheme.
Background technology
Existing modulator-demodulator majority is made up of keypad, supervisory circuit, LCD, modulating baseband unit, modulated medium frequency unit, demodulation intermediate frequency unit, baseband demodulation unit; Can be through button operation modification of this machine or the state of this machine of monitoring; And liquid crystal display displays through being connected with supervisory circuit; LCD can only show the state of this machine that monitors, and does not possess signals collecting and analytic function.The equipment flank speed can only reach 45Mbps, and the modulation system of employing is: BPSK, QPSK, 8PSK.Port A, B are respectively outside base band code stream input and output port.
Along with the information capacity of satellite communication constantly increases, the message capacity of existing satellite and the development that the transmitted power problem of lower has limited application demand.How in limited satellite bandwidth and under the lower transmitting power, transmission data as much as possible are problems that press for solution.
In addition; Development along with China's satellite communication cause; Various novel modulation demodulation systems are applied, and original communication equipment can not be eliminated, and therefore existing satellite communication system becomes more and more numerous and diverse; Use department is faced with a large amount of mutual incompatible communication equipments, has hindered the further application of satellite communication.Press for the modulator-demodulator that development is suitable for multiple satellite communication system, can realize interconnecting with existing multiple satellite communication terminal.
On software was realized, the software upgrading of all unit of existing equipment must realize through download cable on unit module directly that opening and extensibility are relatively poor.When adding new hardware, also need upgrade simultaneously to monitoring software; And monitoring unit transfer of data, storage and disposal ability are relatively poor; The display capabilities of LCD is limited, can not realize the function such as frequency spectrum and planisphere demonstration of error code testing, key node.
Summary of the invention
For solving the deficiency that exists in the prior art; The invention provides a kind of be core with the software and radio technique, in the efficiency of transmission that improves satellite communication system and strengthen on the basis of versatility, flexibility of satellite communication terminal, realize the collection and the download of data.
For realizing above-mentioned purpose, multi-mode high-speed modem of the present invention under the control support of primary control program, comprising:
Modem module is used to receive outside base band code stream and this base band code stream is handled, changed;
Power supply is used for each parts power supply supply, parallelly connected with each parts power supply;
Main control unit is used to realize the information exchange with display control terminal, and realizes the control to modem module;
The cpci bus plate is used to realize the information exchange of main control unit and modem module.
Above-mentioned modem module comprises,
The modulating baseband plate is used for converting the outside base band code stream that receives to zero intermediate frequency orthogonal signalling and output;
The modulated medium frequency plate is used to the various clock signals that provide the modulating baseband plate required, and the zero intermediate frequency orthogonal signalling are carried out being modulated to the L frequency range after the quadrature mixing, and through bandpass filtering and output level control output;
The demodulation IF board is used to receive the output signal of modulated medium frequency plate, and this signal and fixed-frequency source are mixed to the C frequency range, are converted to fixed intermediate frequency 900MHZ and amplify back output;
The baseband demodulation plate is used to adjust the clock signal of demodulation IF board, the output signal of receiving demodulation IF board, and after this signal carried out parallel demodulation and channel decoding, export the clock signal and the data message of this decoding.
Above-mentioned modulating baseband plate is made up of high speed fpga chip, high-speed digital-analog conversion chip, Clock management chip and memory, and the high speed fpga chip is used to receive outside base band stream sign indicating number, also converts this base band stream sign indicating number to orthogonal signalling output; The high-speed digital-analog conversion chip provides work clock, receives orthogonal signalling and this conversion of signals is the output of zero intermediate frequency orthogonal signalling for the high speed fpga chip; The Clock management chip is used to provide the work clock of high-speed digital-analog conversion chip; The high speed fpga chip links to each other with the cpci bus plate through memory, is used for data acquisition and download.
The baseband demodulation plate is made up of high speed analog-to-digital conversion chip, high speed fpga chip, memory, the output signal of described high speed analog-to-digital conversion chip receiving demodulation IF board and to exporting behind this signal bandpass sampling; The high speed fpga chip be used to receive the high speed analog-to-digital conversion chip the output signal, separate and be in harmonious proportion the clock signal and the data message of this decoding of output of decoding back; The high speed fpga chip links to each other with the cpci bus plate through memory, is used for data acquisition and download.
Adopt technique scheme, its effect is following:
1, set up hardware platform basis cpci bus plate, modulating baseband plate, baseband demodulation plate, modulated medium frequency plate, main control unit and demodulation IF board card all insert in the CPCI cabinet, and platform has extensibility, can increase signal handling capacity through increasing the CPCI integrated circuit board;
2, main control unit is different with original monitoring unit; Operating system has been installed; Through the cpci bus plate other integrated circuit boards are carried out the DMA read-write operation; Make the present invention have the frequency spectrum and the planisphere Presentation Function of program dynamic load, error code testing, key node, increase the internal state monitoring capacity, improved availability.
3, the frequency spectrum of the key node in error code testing, modulating baseband plate and the demodulation baseband board two boards card and planisphere all can be through the information exchanges between main control unit and the cpci bus plate; On display, show, can also adapt to different bit rates and modulation system through the new FPGA program of cpci bus plate heavy duty;
4, utilize the bandpass sampling technology can realize multi-modulation scheme (with modulation systems such as the QPSK that realizes with two kinds of patterns of burst continuously, 8PSK, 16APSK) and variable bit rate; Flank speed can reach 155M; Can be operated under the utmost point low signal-to-noise ratio condition; Effectively reduce requirement, improved the efficiency of transmission of communication system satellite transmission power and bandwidth.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further to specify:
Fig. 1 is existing modem structure theory diagram;
Fig. 2 is the structural principle block diagram of existing modulating baseband plate;
Fig. 3 is the structural principle block diagram of existing baseband demodulation plate;
Fig. 4 is a structural principle block diagram of the present invention;
Fig. 5 is the structural principle block diagram of modulating baseband plate of the present invention;
Fig. 6 is the structural principle block diagram of baseband demodulation plate of the present invention.
Embodiment
Existing modem structure theory diagram by shown in Figure 1 can know that it comprises keypad 17, supervisory circuit 18, LCD 19, modulating baseband unit 20, modulated medium frequency unit 21, demodulation intermediate frequency unit 22, baseband demodulation unit 23 modulator-demodulator of prior art.Supervisory circuit 18 inputs are connected with keypad 17 outputs; Through button operation modification of this machine or the state of this machine of monitoring; And LCD 19 demonstrations through being connected with supervisory circuit 18 outputs; LCD 19 can only show the state of this machine that monitors, and does not possess signals collecting and analytic function.The equipment flank speed can only reach 45Mbps, and the modulation system of employing is: BPSK, QPSK, 8PSK.Port A, B are respectively outside base band code stream input and output port.
Structural principle block diagram by existing modulating baseband plate shown in Figure 2 can be known; The modulating baseband plate of existing equipment is made up of fpga chip 24, analog-digital chip 25,26 and phase-locked loop 27; Wherein the clock of fpga chip 24, analog-digital chip 25,26 is provided by phase-locked loop 27, and I, the Q quadrature serial signal of fpga chip 24 outputs are given analog-digital chip 25,26 respectively and carried out the DAC conversion.The fpga chip 24 of existing equipment, analog-digital chip 25,26 and phase-locked loop 27 all can't be when two-forty operate as normal.
Structural principle block diagram by existing baseband demodulation plate shown in Figure 3 can know that the baseband demodulation plate of existing equipment is made up of modulus conversion chip 28,29, fpga chip 30, DDS (Direct Digital Frequency Synthesizers) module 31.Wherein fpga chip 30 clocks are provided by DDS module 31, and the clock of modulus conversion chip 28,29 is provided through fpga chip 30 by DDS module 31, and the zero intermediate frequency orthogonal signalling of demodulation IF board 22 outputs are given analog- digital chip 28,29 respectively and carried out the ADC conversion.
Shown in Figure 4 is structural principle block diagram of the present invention.Set forth embodiment of the present invention below in conjunction with Fig. 4.
Know that by shown in Figure 4 multi-mode high-speed modem of the present invention is under the control support of primary control program; Comprise modem module 16, main control unit 6 (CR9), display control terminal 7; Cpci bus plate 1 (CPCISPEC2.0-008) provides power supply 8 power supply, parallelly connected with each parts power end, and this modem module comprises modulating baseband plate 2; Modulated medium frequency plate 3, demodulation IF board 4, baseband demodulation plate 5.
Wherein modulating baseband plate 2 inputs 4 pin are connected with external input port A, and the data type of port A can be: the digital signal of serial or parallel, can adopt the burst or the data flow of continuation mode.With the modulation system be below the sequential serial data of QPSK set forth signal processing in the present invention and conversion process (other modulation systems, coded system and continuously or burst mode all can change loading procedure and realize through cpci bus): modulating baseband plate 2 inputs 1 pin links to each other with modulated medium frequency plate 3 outputs 3 pin; For modulating baseband plate 2 provides needed various clock signal; Modulating baseband plate 2 forms the QPSK data flow through mapping after continuous serial data stream LDPC is encoded; Behind the shaping interpolation filtering, deliver to DAC again and carry out digital-to-analogue conversion; Zero intermediate frequency orthogonal signalling 2 pin, 3 pin with output link to each other with modulated medium frequency plate 3 inputs 4 pin, 5 pin then, as the input signal of modulated medium frequency plate 3; The input signal of modulated medium frequency plate 3 directly is modulated to the L frequency range after the quadrature mixing, through bandpass filtering and output level control, deliver to demodulation IF board 4 inputs 4 pin by output 1 pin again; Baseband demodulation plate 5 outputs 6 pin are adjusted the clock signal that demodulation IF board 4 outputs 1 pin sends baseband demodulation plate 5 inputs 1 pin to through the crystal oscillator of adjustment demodulation IF board 4 inputs 5 pin; Demodulation IF board 4 at first is mixed to the C frequency range with fixed-frequency source with the L frequency band signals; After the variable frequency synthesizer is converted to input signal fixed intermediate frequency 900MHz amplification, give the input signal of baseband demodulation plate 5 inputs 2 pin again as this plate by output 2 pin; This signal obtains near the digital medium-frequency signal the 300MHz by the ADC bandpass sampling; Through obtaining baseband I, Q signal after the orthogonal digital down-conversion; Again through behind the matched filter, regularly recover, carrier wave recovers the back and accomplishes parallel channel decoding; The clock and the data of decoding output are exported by output 3 pin, 4 pin, and the final modulation of accomplishing links to each other with external output port B, C; Main control unit 6 inputs 1 pin links to each other with LCD 7 outputs 1 pin through data wire; Cpci bus plate 1 port one～5 pin link to each other with modulating baseband plate 2 ports 5 pin, modulated medium frequency plate 3 ports 2 pin, demodulation IF board 4 ports 3 pin, baseband demodulation plate 5 ports 5 pin and main control unit 6 ports 2 pin respectively; Main control unit 6 can be realized the data download, gathers and calculate through cpci bus plate 1, and can realize the frequency spectrum and the planisphere Presentation Function of error code testings, key node at LCD 7.Power supply 8 delivery outlets+V1 ,+V2 ,+the corresponding power end of V3 power end and connecing with each parts.Mode of operation, data rate, modulation system and coded system all can be realized with cpci bus plate 1 control modulating baseband plate 2 ports 5 pin, the different FPGA program of baseband demodulation plate 5 ports 5 pin heavy duty through main control unit 6 by LCD; The L frequency range (can be realized through the main control unit 6 and the frequency synthesizer of cpci bus plate 1 control modulated medium frequency plate 3 ports 2 pin by LCD in the section of 950Mhz～1450Mhz) by being provided with equally of frequency.
Know by shown in Figure 5; Modulating baseband plate 2 of the present invention is made up of high speed FPGA (field programmable gate array) chip 9, high-speed digital-analog conversion chip 10, Clock management chip 11, memory 12; Its high speed fpga chip 9 inputs 10 pin are connected with outside base band code stream input port A; High speed fpga chip 9 inputs 1 pin links to each other with high-speed digital-analog conversion chip 10 outputs 1 pin; For high speed fpga chip 9 provides clock, high-speed digital-analog conversion chip 10 inputs 9 pin are connected with Clock management chip 11 outputs 1 pin, and Clock management chip 11 provides work clock for high-speed digital-analog conversion chip 10; High speed fpga chip 9 outputs 2～5 pin are the digital output orthogonal signal of modulating baseband plate 2; Every pin is represented one group of I, Q orthogonal signalling; Four circuit-switched data and line output, every road speed can reach 155Mbps, and serial rate can reach 620Mbps; Four channel parallel datas are connected with high-speed digital-analog conversion chip 10 inputs 2～5 pin respectively, and high-speed digital-analog conversion chip 10 outputs 10 pin, 11 pin are connected with modulated medium frequency plate 3 inputs 4 pin, 5 pin respectively as the analog signal after changing; High speed fpga chip 9, Clock management chip 11 each input 8 pin link to each other with power supply 8 outputs+V1 voltage end; High-speed digital-analog conversion chip 10 inputs 8 pin link to each other with power supply 8 outputs-V2 voltage end; Each input 9 pin links to each other with the ground end; High speed fpga chip 9 ports 7 pin link to each other with 1 pin of cpci bus plate 1 through memory 12, realize data acquisition and download.
Know that by shown in Figure 6 baseband demodulation plate 5 of the present invention is made up of high speed analog-to-digital conversion chip 13, high speed fpga chip 14, memory 15.Wherein high speed analog-to-digital conversion chip 13 inputs 1 pin links to each other with demodulation IF board 4 output 900Mbps intermediate-freuqncy signals 1 pin; By exporting four tunnel flank speeds at output 5～8 pin behind high speed analog-to-digital conversion chip 13 bandpass samplings is that the parallel data of 300Mbps is connected with high speed fpga chip 14 inputs 1～4 pin, carries out parallel demodulation and decoding; High speed fpga chip 14 outputs 6 pin are adjusted the clock signal that demodulation IF board 4 outputs 2 pin send high speed fpga chip 14 inputs, 5 pin and high speed analog-to-digital conversion chip 13 inputs 3 pin to through the crystal oscillator of adjustment demodulation IF board 4 inputs 5 pin; High speed fpga chip 14 outputs 10 pin, 11 pin are respectively high-speed coding data flow and clock, are connected with outside port B, C; High speed analog-to-digital conversion chip 13 links to each other with power supply 8 outputs+V1 voltage end with 7 pin with high speed fpga chip 14 inputs 2 pin, and input 4 pin link to each other with the ground end with 8 pin.High speed fpga chip 14 ports 9 pin link to each other with 4 pin of cpci bus plate 1 through memory 15, realize data acquisition and download.
In the present invention, the signals sampling frequency surpasses 1GHz, and the data-signal transfer rate of chip chamber also surpasses 155MHz; Under high like this speed; The wiring situation of printed board will influence the correct transmission of data, so we adopt the design software-Cadence with copying, establishes correct wiring rule; Through the potential problems that exist in the effective artificial circuit of Cadence meter simulation software, effectively avoid the competition and the risk of sequential logic through adjustment layout, wiring.
Though more than combine accompanying drawing to describe execution mode of the present invention, those skilled in the art can make various distortion or modification within the scope of the appended claims.
Claims (1)
1. multi-mode high-speed modem under the control support of primary control program, comprising:
Modem module (16) is used to receive outside base band code stream and this base band code stream is handled, changed;
Power supply (8) is used for each parts power supply supply, parallelly connected with each parts power supply;
It is characterized in that:
Main control unit (6) is used for the information exchange of realization and display control terminal (7), and realizes the control to modem module (16);
Cpci bus plate (1) is used to realize the information exchange of main control unit (6) and modem module (9);
Wherein, described modem module (16) comprises,
Modulating baseband plate (2) is used for converting the outside base band code stream that receives to zero intermediate frequency orthogonal signalling and output;
Modulated medium frequency plate (3) is used for the zero intermediate frequency orthogonal signalling are carried out being modulated to the L frequency range after the quadrature mixing, and through bandpass filtering and output level control output;
Demodulation IF board (4) is used to receive the output signal of modulated medium frequency plate (3), and this signal and fixed-frequency source are mixed to the C frequency range, are converted to fixed intermediate frequency 900MHZ and amplify back output;
Baseband demodulation plate (5) is used to adjust the clock signal of demodulation IF board (4), the output signal of receiving demodulation IF board (4), and after this signal carried out parallel channel decoding, export the clock signal and the data message of this decoding;
Wherein, Described modulating baseband plate (2) is made up of high speed fpga chip (9), high-speed digital-analog conversion chip (10), Clock management chip (11) and memory (12), and described high speed fpga chip (9) is used to receive outside base band stream sign indicating number, also converts this base band stream sign indicating number to orthogonal signalling output; High-speed digital-analog conversion chip (10) provides work clock, receives orthogonal signalling and this conversion of signals is the output of zero intermediate frequency orthogonal signalling for high speed fpga chip (9); Clock management chip (11) is used to provide the work clock of high-speed digital-analog conversion chip (10); High speed fpga chip (9) links to each other, is used for data acquisition and download through memory (12) with cpci bus plate (1);
Wherein, Described baseband demodulation plate (5) is made up of high speed analog-to-digital conversion chip (13), high speed fpga chip (14), memory (15), the output signal of described high speed analog-to-digital conversion chip (13) receiving demodulation IF board (4) and to exporting behind this signal bandpass sampling; High speed fpga chip (14) be used to receive high speed analog-to-digital conversion chip (13) the output signal, separate and be in harmonious proportion the clock signal and the data message of this decoding of output of decoding back; High speed fpga chip (14) links to each other, is used for data acquisition and download through memory (15) with cpci bus plate (1).
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| CN200910073964A CN101505186B (en) | 2009-03-20 | 2009-03-20 | Multi-mode high-speed modem |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101674272B (en) * | 2009-10-26 | 2012-01-25 | 西安空间无线电技术研究所 | System and method for recovering high-speed parallel 8PSK carriers |
| CN104407532B (en) * | 2014-09-30 | 2017-08-11 | 清华大学 | Digital demodulator based on industry control machine platform |
| CN104767560B (en) * | 2015-05-06 | 2017-12-12 | 中国科学院遥感与数字地球研究所 | Portable two-channel tests modulating equipment and its modulator approach |
| CN108111457B (en) * | 2017-12-25 | 2020-10-16 | 中国电子科技集团公司第五十四研究所 | Device for high-speed demodulation under bandwidth-limited condition |
| FR3099673B1 (en) * | 2019-07-31 | 2021-08-27 | Thales Sa | PROCESS FOR DETERMINING THE CONSTRAINTS OF A NON-GEOSTATIONARY SYSTEM WITH RESPECT TO ANOTHER NON-GEOSTATIONARY SYSTEM |
| CN113114347B (en) * | 2021-06-15 | 2021-09-14 | 凯睿星通信息科技(南京)股份有限公司 | Method and system for automatically matching modem operating modes |
| CN113708829A (en) * | 2021-10-28 | 2021-11-26 | 广东粤港澳大湾区硬科技创新研究院 | Satellite signal processing method and device and satellite baseband equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1059241A (en) * | 1990-05-30 | 1992-03-04 | 海崖微型计算机产品公司 | The telecommunication installation of global LIM structure and this module of application |
| CN2807630Y (en) * | 2005-06-30 | 2006-08-16 | 上海协航通信技术有限公司 | High-speed wireless data transmission modem |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1059241A (en) * | 1990-05-30 | 1992-03-04 | 海崖微型计算机产品公司 | The telecommunication installation of global LIM structure and this module of application |
| CN2807630Y (en) * | 2005-06-30 | 2006-08-16 | 上海协航通信技术有限公司 | High-speed wireless data transmission modem |
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