CN101504680B - Clock offset locality optimizing analysis method - Google Patents
Clock offset locality optimizing analysis method Download PDFInfo
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Abstract
The invention discloses a method for local optimization analysis of clock deviation, and belongs to the technical field of clock deviation adjustment of the back end of an ASIC chip design flow on a zero-deviation clock tree. The method adopts a method of inserting a clock buffer to adjust the clock deviation and finally integrally improves the performance and the stability of a circuit. The optimization method can be embedded in a comprehensive design tool of a general clock tree in the industry and is integrated with the prior standard physical design flow.
Description
Technical field
Invention relates to a kind of clock offset locality optimizing analysis method, belongs to asic chip design cycle rear end the zero-deviation clock trees is carried out the technical field that clock jitter is adjusted.
Background technology
In VLSI (very large scale integrated circuit) designs (VLSI), the design that clock signal networks distributes is a very important job.Because clock signal is a control signal, time reference (time reference) as synchronizing circuit (synchronous circuit) data transmission of chip internal, compare with other control signal of chip internal, clock signal has maximum fan-out (fanout), the longest wiring distance and the highest characteristics such as upset rate usually.This makes the design and the realization of clock distributing network, is important problem very always.Clock signal directly influences the performance (performance) and the stability (reliability) of circuit.Along with the progress of manufacturing process technology, integrated circuit (IC) design has entered the System on Chip/SoC development phase (system on chip), so the design difficulty of clock distributing network is bigger, and importance is more outstanding.
Clock jitter is the difference of clock source to the clock delay of different register clock end.For avoiding the influence of clock jitter to circuit performance, the design of present clock tree mostly is to be purpose to dwindle clock jitter as far as possible.Yet, promptly enabling to avoid fully clock jitter (i.e. zero clock jitter), the minimum value of clock period will be subject to the maximal value of the signal transmission delay between the sequential adjunct register in the circuit.If can effectively utilize the clock jitter between adjunct register, can promote the speed and the stability of circuit, reach high performance design.Current, how to utilize clock jitter to promote circuit performance and Study on Stability is more and more deep.
Summary of the invention
Goal of the invention is to provide a kind of clock offset locality optimizing analysis method at the defective that prior art exists.
Invention is adopted following technical scheme for achieving the above object:
The invention clock offset locality optimizing analysis method is characterized in that comprising the steps:
The first step: initialization
The abundant value x0 of self timing path, the abundant value x1 of prime sequential, the back level abundant value x2 of sequential and cycle labeling flag=1 are set;
Second step: when cycle labeling flag greater than 0, then obtain sequential divided dose slack_new with dividing equally after described 3 the abundant values summation of the first step, entered for the 3rd step; Flag equals 0 when cycle labeling, then changes for the 7th step;
The 3rd step: ask difference to obtain catching end clock delay added value Tcapture_incr abundant value x1 of prime sequential and described sequential divided dose slack_new of second step, ask difference to obtain transmitting terminal clock delay minimizing value Tlaunch_decr back level abundant value x2 of sequential and described sequential divided dose slack_new of second step;
The 4th step: when catch end clock delay added value Tcapture_incr make late-class circuit retention time in violation of rules and regulations, then level sequential abundant value x1 in back is set to the retention time allowance h_min_c of late-class circuit, returns second and goes on foot;
When catch end clock delay added value Tcapture_incr do not make late-class circuit retention time in violation of rules and regulations, then entered for the 5th step;
The 5th step: when data tranmitting data register end minimizing value Tlaunch_decr make front stage circuits retention time in violation of rules and regulations, then the abundant value x1 of prime sequential is set to the retention time allowance h_min_l of front stage circuits, returns second and goes on foot;
When making, data tranmitting data register end minimizing value Tlaunch_decr the retention time violation of front stage circuits then do not enter for the 6th step;
The 6th step: flag puts 0 with cycle labeling, returns the circulation of second step and adjusts end;
The 7th step: will catching end clock delay added value Tcapture_incr and transmitting terminal clock delay minimizing value Tlaunch_decr addition, to obtain positive clock jitter value be useful clock jitter;
The 8th step: when described useful clock jitter of the 7th step make self circuit retention time in violation of rules and regulations, then will catch end clock delay added value Tcapture_incr and transmitting terminal clock delay minimizing value Tlaunch_decr and be reduced into original k doubly, k is the ratio of actual adjusted value of deviation and useful clock jitter;
The 9th step: the abundant value x0 of self timing path is added that useful clock jitter obtains new allowance s_new Time Created of crucial timing path, deducts useful clock jitter with the abundant value x0 of self timing path and obtains new retention time allowance h_new.
Invention has proposed the optimized Algorithm that the clock allowance is divided equally, and the method that adopts clock buffer to insert is adjusted clock jitter, finally improves the performance and the stability of circuit on the whole.This optimization method can embed in the universal timepiece tree comprehensive Design instrument of industry, integrates with existing standard physical design cycle.Be connected step before and after the clock offset locality optimizing by the Tcl script, realized that automatic clock jitter optimizes and revises.Under the prerequisite that does not influence other temporal constraint conditions of circuit, realize the clock jitter adjustment, finally improved the performance and the stability of circuit on the whole.
Description of drawings
Fig. 1 is the process flow diagram of algorithm.
Fig. 2 is the timing path figure between the sequential adjunct register, and what represent among the figure is two registers, and some combinational circuits are arranged therebetween, and clock is by the input end of clock of some buffers arrival registers, and the time factor of various piece is identified among the figure among the figure.
Fig. 3 is timing path figure behind the parameter predigesting.
Fig. 4 is the influence figure of clock jitter to circuit performance and stability.
Fig. 5 be with Fig. 3 sequential circuit be abstracted into constraints graph G (V, E), starting point and terminal point trigger in the corresponding sequential circuit of wherein node V, the combinational logic path that connects two nodes is abstracted into two directed edges, on one side e
IjExpression allowance s Time Created, another side e
JiExpression retention time allowance h.
Fig. 6 is crucial timing path locality time sequence parameter figure, and block scheme is represented register among the figure, and oval figure expression combinatorial path with s beginning ground parametric representation Time Created, keeps in this world with the parametric representation of h beginning, and min and max represent the longest shortest path respectively.It from Launch_reg/CK to Capture_reg/D crucial timing path.The timing path relevant with these two circuit nodes also has 4 groups, and time sequence parameter also has 8.
Fig. 7 is the time sequence parameter constraints graph with Fig. 6.Register is abstracted into node, and timing path is represented with directed edge.When increasing the clock delay of circuit node, be that the sequential allowance of terminal point will increase with it, and be that the sequential allowance of starting point will reduce with it.
Fig. 8 is that clock jitter improves circuit performance figure.Positive clock jitter can increase allowance Time Created, has subtracted the circuit clock cycle, has put forward the circuit travelling speed.Can be by reducing transmitting terminal clock delay (Tlaunch_decr), or increase and catch end time delay (Tcapture_incr) and generate positive clock jitter.
Embodiment
Be elaborated below in conjunction with the technical scheme of accompanying drawing to invention:
Shown in Figure 1, algorithm is begun by the initialization to some data, and initialization data is from the sequential key path, extraction is from static timing analysis (STA) instrument, comprise critical path self, parameter Time Created in prime, level path, back, setting the circulation zone bit simultaneously is 1.Cyclic process is: divide equally allowance, judge whether allowance is influential to prime, level path, back, if it is influential, the retention time of using prime, back level is divided equally allowance again as new abundant value, till the retention time of satisfying the front and back level requires to divide equally again, if not having influence puts and is designated 0 and jumps out circulation, and then calculate final allowance and judged whether the retention time in violation of rules and regulations, if there is then the usage ratio factor adjust, be not as the criterion by the result of circulation adjustment if having then.
Concrete steps are as follows:
The first step: initialization
The abundant value x0 of self timing path, the abundant value x1 of prime sequential, the back level abundant value x2 of sequential and cycle labeling flag=1 are set;
Second step: when cycle labeling flag greater than 0, then obtain sequential divided dose slack_new with dividing equally after described 3 the abundant values summation of the first step, entered for the 3rd step; Flag equals 0 when cycle labeling, then changes for the 7th step;
The 3rd step: ask difference to obtain catching end clock delay added value Tcapture_incr abundant value x1 of prime sequential and described sequential divided dose slack_new of second step, ask difference to obtain transmitting terminal clock delay minimizing value Tlaunch_decr back level abundant value x2 of sequential and described sequential divided dose slack_new of second step;
The 4th step: when catch end clock delay added value Tcapture_incr make late-class circuit retention time in violation of rules and regulations, then level sequential abundant value x1 in back is set to the retention time allowance h_min_c of late-class circuit, returns second and goes on foot;
When catch end clock delay added value Tcapture_incr do not make late-class circuit retention time in violation of rules and regulations, then entered for the 5th step;
The 5th step: when data tranmitting data register end minimizing value Tlaunch_decr make front stage circuits retention time in violation of rules and regulations, then the abundant value x1 of prime sequential is set to the retention time allowance h_min_l of front stage circuits, returns second and goes on foot;
When making, data tranmitting data register end minimizing value Tlaunch_decr the retention time violation of front stage circuits then do not enter for the 6th step;
The 6th step: flag puts 0 with cycle labeling, returns the circulation of second step and adjusts end;
The 7th step: will catching end clock delay added value Tcapture_incr and transmitting terminal clock delay minimizing value Tlaunch_decr addition, to obtain positive clock jitter value be useful clock jitter;
The 8th step: when described useful clock jitter of the 7th step make self circuit retention time in violation of rules and regulations, then will catch end clock delay added value Tcapture_incr and transmitting terminal clock delay minimizing value Tlaunch_decr and be reduced into original k doubly, k is the ratio of actual adjusted value of deviation and useful clock jitter;
The 9th step: the abundant value x0 of self timing path is added that useful clock jitter obtains new allowance s_new Time Created of crucial timing path, deducts useful clock jitter with the abundant value x0 of self timing path and obtains new retention time allowance h_new.
The clock offset locality optimizing method is with the abstract constraints graph G (V that becomes of circuit, E), the trigger in the corresponding sequential circuit of node set V wherein, the combinational logic path that connects two nodes is abstracted into two directed edge E, represent allowance Time Created on one side, another side is represented the retention time allowance.After in the chip design flow process, extracting the sequential allowance of crucial timing path and front and back level thereof, allowance is divided equally, improve the performance and the stability of circuit on the whole.
Only to influential each other, promptly the clock deviation has the characteristics of locality to clock jitter between the sequential adjunct register.When the design clock trees, not necessarily want zero clock jitter, to two register R that sequential is adjacent
iWith R
j, clock delay T
CiWith T
CjNot necessarily identical, as long as satisfy Time Created and retention time constraint condition.This moment register R
iTo register R
jData routing still can operate as normal.
Positive clock jitter is equivalent to time of providing extra, for signal from register R
iBe passed to register R
jTherefore,, can reduce the clock period, improve the highest frequency that circuit can correctly be worked if can take positive clock jitter to critical path; With above-mentioned opposite, negative clock jitter can avoid circuit race condition to occur, therefore can improve the safety allowance of circuit, increases the stability of circuit.
The Time Created of ifs circuit crucial timing path and retention time, crucial timing path checked and balance, and performance and stability are exactly a pair of contradiction so.But actual conditions, the two generally is in the different piece of circuit, can not influence the stability of circuit when promptly improving performance, and vice versa.
Course of work detailed annotation
Fig. 2 has listed time sequence parameter values all in the register timing path, comprises the interconnection line time-delay.The prerequisite that synchronizing circuit can be worked is that sequential will satisfy:
T
Hold+ T
Cj＜T
C-＞Q, cd+ T
Logic, cd+ T
Int, cd+ T
CiAnd
T+T
Cj＞T
C-＞Q+ T
Logic+ T
Int+ T
Setup+ T
Ci, T
C-＞Q,, cdAnd T
C-＞QBe respectively the attribute of register self, minimum propagation delay and maximum propagation time-delay; T
SetupAnd T
HoldBe respectively the attribute of register self, Time Created and retention time; T
Logic, cdAnd T
LogicBe respectively the minimum time-delay and the maximum delay of combinational logic; T
Int, cdAnd T
IntThe minimum time-delay and the maximum delay of interconnection line; T
CiAnd T
CjBe the clock delay T in the relative global clock of register source
Skewij=T
Cj-T
CiWhen the clock time-delay does not wait, just produced clock jitter.
Fig. 3 represents the definition of clock jitter and the valid interval value of clock deviation.
With T Time Created
SetupWith retention time T
HoldCount path maximum delay T respectively
MaxWith minimum time-delay T
MinAs in.As T
Min=T
C-＞Q, cd+ T
Logic, cd+ T
Int, cd-T
HoldAnd T
Max=T
C-＞Q+ T
Logic+ T
Int+ T
SetupShown in, long data path delay is meant and adds the path delay of terminal point register after Time Created that short data path delay is meant the path delay after the retention time that deducts the terminal point register.So simplify and be mainly the notion that highlights clock jitter and the influence of temporal constraint.Finally, deviation effective range such as the T after the simplification
Max-T＜T
Skewij＜T
MinShown in.
Fig. 4 is illustrated in the effective scope of clock jitter, and positive clock jitter can increase allowance Time Created, improves the performance of circuit; And negative clock jitter can increase the stability of circuit.S=T
Skewij+ T-T
MaxAnd h=T
Min-T
SkewijDefined the allowance and retention time allowance Time Created of same timing path respectively.Time Created, crucial timing path determined circuit performance, and allowance s represents value from violation Time Created critical conditions with Time Created.Corresponding with it, represent from retention time critical value in violation of rules and regulations with retention time allowance h.For same timing path, it is cost that circuit performance and stability increase to sacrifice the opposing party.But in real circuit, Time Created crucial timing path and retention time, crucial timing path was distributed in the zones of different of circuit, therefore might improve the stability and the performance of circuit simultaneously.
Fig. 5 be with Fig. 3 sequential circuit be abstracted into constraints graph G (V, E).Starting point and terminal point trigger in the corresponding sequential circuit of node V wherein, the combinational logic path that connects two nodes is abstracted into two directed edges, on one side e
IjExpression allowance s Time Created, another side e
JiExpression retention time allowance h.If the clock delay of certain node is increased Δ, be that the sequential allowance of the directed edge of terminal point will increase Δ then, and be the sequential allowance minimizing Δ of the directed edge of starting point with it with it; Vice versa.Through after such processing, after obtaining corresponding circuit sequence allowance, the adjustment of clock jitter has been simplified to the problem of calculating the clock delay value.
Fig. 6 is the locality time sequence parameter figure that register Launch_reg/CK holds register Capture_reg/D end timing path.Fig. 2 and Fig. 3 only represent an isolated timing path, but actual conditions as shown in Figure 5, have comprised other 4 groups of timing paths and 8 other time sequence parameters.Register L_ends is to be the destination set of the timing path of starting point with register Launch_reg among the figure; Register L_starts is to be the starting point set of the timing path of terminal point with register Launch_reg; Register C_ends is to be the destination set of the timing path of starting point with register Capture_reg; Register C_starts be with register Capture_reg be terminal point timing path play point set, empty frame table shows the set of representing register, not necessarily has only a register.
With expression minimum Time Created of the allowance of s beginning, with the expression minimum hold time allowance of h beginning.For the sake of simplicity, be the timing path of terminal point with register Launch_reg, be called the prime timing path; With register Capture_reg is the timing path of starting point, is called back level timing path.
Fig. 7 is the time sequence parameter constraints graph corresponding with Fig. 6.With register abstract be node, and the sequential allowance is abstracted into directed edge.When increasing the clock delay (clock delay) of circuit node, be that the sequential allowance of terminal point will increase with it, and be that the sequential allowance of starting point will reduce with it.Through such processing, when carrying out clock offset locality optimizing, can simplify deal with data, only consider to be subjected to the time sequence parameter of negative effect.
Fig. 8 represents how to carry out the clock jitter adjustment is improved circuit performance figure.The crucial timing path that we pay close attention to be from Launch_reg/CK to Capture_reg/D this, suppose that it has limited the performance of circuit, promptly determined the minimum clock cycle of circuit.Positive clock jitter can increase allowance Time Created, has subtracted the circuit clock cycle, has put forward the circuit travelling speed.As among Fig. 3 about the definition of clock jitter, can be by reducing transmitting terminal clock delay Tlaunch_decr, or increase and catch end time delay Tcapture_incr and produce positive clock jitter.Among the figure mark positive clock jitter it is produced the time sequence parameter of negative effect.According to Fig. 5 as can be known, the increase of clock delay or reduce to increase the allowance of part time sequence parameter.Data volume is to simplify the process ignored the parameter that the sequential allowance increases.
Claims (1)
1. a clock offset locality optimizing analysis method is characterized in that comprising the steps:
The first step: initialization
The abundant value x0 of self timing path, the abundant value x1 of prime sequential, the back level abundant value x2 of sequential and cycle labeling flag=1 are set;
Second step: when cycle labeling flag greater than 0, then obtain sequential divided dose slack_new with dividing equally after described 3 the abundant values summation of the first step, entered for the 3rd step; Flag equals 0 when cycle labeling, then changes for the 7th step;
The 3rd step: ask difference to obtain catching end clock delay added value Tcapture_incr abundant value x1 of prime sequential and described sequential divided dose slack_new of second step, ask difference to obtain transmitting terminal clock delay minimizing value Tlaunch_decr back level abundant value x2 of sequential and described sequential divided dose slack_new of second step;
The 4th step: when catch end clock delay added value Tcapture_incr make late-class circuit retention time in violation of rules and regulations, then level sequential abundant value x2 in back is set to the retention time allowance h_min_c of late-class circuit, returns second and goes on foot;
When catch end clock delay added value Tcapture_incr do not make late-class circuit retention time in violation of rules and regulations, then entered for the 5th step;
The 5th step: when transmitting terminal clock delay minimizing value Tlaunch_decr make front stage circuits retention time in violation of rules and regulations, then the abundant value x1 of prime sequential is set to the retention time allowance h_min_1 of front stage circuits, returns second and goes on foot;
When making, transmitting terminal clock delay minimizing value Tlaunch_decr the retention time violation of front stage circuits then do not enter for the 6th step;
The 6th step: flag puts 0 with cycle labeling, returns the circulation of second step and adjusts end;
The 7th step: will catching end clock delay added value Tcapture_incr and transmitting terminal clock delay minimizing value Tlaunch_decr addition, to obtain positive clock jitter value be useful clock jitter;
The 8th step: when described useful clock jitter of the 7th step make self circuit retention time in violation of rules and regulations, then will catch end clock delay added value Tcapture_incr and transmitting terminal clock delay minimizing value Tlaunch_decr and be reduced into original k doubly, k is the ratio of actual adjusted value of deviation and useful clock jitter;
The 9th step: the abundant value x0 of self timing path is added that useful clock jitter obtains new allowance s_new Time Created of crucial timing path, deducts useful clock jitter with the abundant value x0 of self timing path and obtains new retention time allowance h_new.
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| WO2011054385A1 (en) * | 2009-11-05 | 2011-05-12 | Areva T&D Uk Limited | Method of monitoring the grading margin between time-current characteristics of intelligent electronic devices |
| CN102682158B (en) * | 2012-04-16 | 2013-12-25 | 东南大学 | Digital circuit working frequency optimizing method based on clock jitter planning algorithm |
| CN109947173B (en) * | 2019-03-18 | 2020-12-18 | 上海安路信息科技有限公司 | Maximum clock deviation calculation method and calculation system |
| CN111459878B (en) * | 2020-04-02 | 2023-05-23 | 京微齐力(北京)科技有限公司 | Method and system for automatically reducing clock delay deviation |
| CN111949589B (en) | 2020-07-22 | 2022-05-24 | 浪潮(北京)电子信息产业有限公司 | Clock control method, device, equipment and storage medium |
| CN112632887B (en) * | 2020-12-18 | 2023-04-18 | 展讯通信（上海）有限公司 | Clock delay adjusting method and device of memory, storage medium and terminal |
| CN116861842B (en) * | 2023-09-04 | 2023-12-19 | 珠海凌烟阁芯片科技有限公司 | Implementation method and related device for adjustable segmented reverse clock tree |
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Assignee: Wuxi Dongji Electronic Co.,Ltd. Assignor: Southeast University Contract record no.: 2012320000337 Denomination of invention: Clock offset locality optimizing analysis method Granted publication date: 20100901 License type: Exclusive License Open date: 20090812 Record date: 20120329 |